root / hw / qxl.c @ 6f2b175a
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/*
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* Copyright (C) 2010 Red Hat, Inc.
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*
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* written by Yaniv Kamay, Izik Eidus, Gerd Hoffmann
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* maintained by Gerd Hoffmann <kraxel@redhat.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 or
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* (at your option) version 3 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu-common.h" |
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#include "qemu-timer.h" |
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#include "qemu-queue.h" |
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#include "monitor.h" |
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#include "sysemu.h" |
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#include "qxl.h" |
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#undef SPICE_RING_PROD_ITEM
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#define SPICE_RING_PROD_ITEM(r, ret) { \
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typeof(r) start = r; \ |
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typeof(r) end = r + 1; \
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uint32_t prod = (r)->prod & SPICE_RING_INDEX_MASK(r); \ |
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typeof(&(r)->items[prod]) m_item = &(r)->items[prod]; \ |
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if (!((uint8_t*)m_item >= (uint8_t*)(start) && (uint8_t*)(m_item + 1) <= (uint8_t*)(end))) { \ |
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abort(); \ |
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} \ |
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ret = &m_item->el; \ |
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} |
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#undef SPICE_RING_CONS_ITEM
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#define SPICE_RING_CONS_ITEM(r, ret) { \
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typeof(r) start = r; \ |
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typeof(r) end = r + 1; \
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uint32_t cons = (r)->cons & SPICE_RING_INDEX_MASK(r); \ |
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typeof(&(r)->items[cons]) m_item = &(r)->items[cons]; \ |
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if (!((uint8_t*)m_item >= (uint8_t*)(start) && (uint8_t*)(m_item + 1) <= (uint8_t*)(end))) { \ |
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abort(); \ |
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} \ |
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ret = &m_item->el; \ |
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} |
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#undef ALIGN
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#define ALIGN(a, b) (((a) + ((b) - 1)) & ~((b) - 1)) |
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|
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#define PIXEL_SIZE 0.2936875 //1280x1024 is 14.8" x 11.9" |
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#define QXL_MODE(_x, _y, _b, _o) \
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{ .x_res = _x, \
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.y_res = _y, \ |
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.bits = _b, \ |
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.stride = (_x) * (_b) / 8, \
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.x_mili = PIXEL_SIZE * (_x), \ |
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.y_mili = PIXEL_SIZE * (_y), \ |
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.orientation = _o, \ |
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} |
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#define QXL_MODE_16_32(x_res, y_res, orientation) \
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QXL_MODE(x_res, y_res, 16, orientation), \
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QXL_MODE(x_res, y_res, 32, orientation)
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#define QXL_MODE_EX(x_res, y_res) \
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QXL_MODE_16_32(x_res, y_res, 0), \
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QXL_MODE_16_32(y_res, x_res, 1), \
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QXL_MODE_16_32(x_res, y_res, 2), \
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QXL_MODE_16_32(y_res, x_res, 3)
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static QXLMode qxl_modes[] = {
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QXL_MODE_EX(640, 480), |
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QXL_MODE_EX(800, 480), |
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QXL_MODE_EX(800, 600), |
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QXL_MODE_EX(832, 624), |
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QXL_MODE_EX(960, 640), |
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QXL_MODE_EX(1024, 600), |
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QXL_MODE_EX(1024, 768), |
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QXL_MODE_EX(1152, 864), |
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QXL_MODE_EX(1152, 870), |
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QXL_MODE_EX(1280, 720), |
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QXL_MODE_EX(1280, 760), |
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QXL_MODE_EX(1280, 768), |
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QXL_MODE_EX(1280, 800), |
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QXL_MODE_EX(1280, 960), |
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QXL_MODE_EX(1280, 1024), |
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QXL_MODE_EX(1360, 768), |
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QXL_MODE_EX(1366, 768), |
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QXL_MODE_EX(1400, 1050), |
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QXL_MODE_EX(1440, 900), |
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QXL_MODE_EX(1600, 900), |
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QXL_MODE_EX(1600, 1200), |
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QXL_MODE_EX(1680, 1050), |
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QXL_MODE_EX(1920, 1080), |
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#if VGA_RAM_SIZE >= (16 * 1024 * 1024) |
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/* these modes need more than 8 MB video memory */
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QXL_MODE_EX(1920, 1200), |
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QXL_MODE_EX(1920, 1440), |
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QXL_MODE_EX(2048, 1536), |
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QXL_MODE_EX(2560, 1440), |
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QXL_MODE_EX(2560, 1600), |
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#endif
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#if VGA_RAM_SIZE >= (32 * 1024 * 1024) |
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/* these modes need more than 16 MB video memory */
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QXL_MODE_EX(2560, 2048), |
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QXL_MODE_EX(2800, 2100), |
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QXL_MODE_EX(3200, 2400), |
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#endif
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}; |
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static PCIQXLDevice *qxl0;
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static void qxl_send_events(PCIQXLDevice *d, uint32_t events); |
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static int qxl_destroy_primary(PCIQXLDevice *d, qxl_async_io async); |
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static void qxl_reset_memslots(PCIQXLDevice *d); |
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static void qxl_reset_surfaces(PCIQXLDevice *d); |
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static void qxl_ring_set_dirty(PCIQXLDevice *qxl); |
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void qxl_guest_bug(PCIQXLDevice *qxl, const char *msg, ...) |
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{
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qxl_send_events(qxl, QXL_INTERRUPT_ERROR); |
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if (qxl->guestdebug) {
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va_list ap; |
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va_start(ap, msg); |
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fprintf(stderr, "qxl-%d: guest bug: ", qxl->id);
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vfprintf(stderr, msg, ap); |
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fprintf(stderr, "\n");
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va_end(ap); |
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} |
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} |
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void qxl_spice_update_area(PCIQXLDevice *qxl, uint32_t surface_id,
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struct QXLRect *area, struct QXLRect *dirty_rects, |
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uint32_t num_dirty_rects, |
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uint32_t clear_dirty_region, |
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qxl_async_io async, struct QXLCookie *cookie)
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{
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if (async == QXL_SYNC) {
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qxl->ssd.worker->update_area(qxl->ssd.worker, surface_id, area, |
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dirty_rects, num_dirty_rects, clear_dirty_region); |
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} else {
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assert(cookie != NULL);
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spice_qxl_update_area_async(&qxl->ssd.qxl, surface_id, area, |
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clear_dirty_region, (uint64_t)cookie); |
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} |
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} |
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static void qxl_spice_destroy_surface_wait_complete(PCIQXLDevice *qxl, |
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uint32_t id) |
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{
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qemu_mutex_lock(&qxl->track_lock); |
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qxl->guest_surfaces.cmds[id] = 0;
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qxl->guest_surfaces.count--; |
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qemu_mutex_unlock(&qxl->track_lock); |
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} |
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static void qxl_spice_destroy_surface_wait(PCIQXLDevice *qxl, uint32_t id, |
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qxl_async_io async) |
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{
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QXLCookie *cookie; |
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if (async) {
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cookie = qxl_cookie_new(QXL_COOKIE_TYPE_IO, |
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QXL_IO_DESTROY_SURFACE_ASYNC); |
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cookie->u.surface_id = id; |
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spice_qxl_destroy_surface_async(&qxl->ssd.qxl, id, (uint64_t)cookie); |
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} else {
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qxl->ssd.worker->destroy_surface_wait(qxl->ssd.worker, id); |
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qxl_spice_destroy_surface_wait_complete(qxl, id); |
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} |
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} |
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static void qxl_spice_flush_surfaces_async(PCIQXLDevice *qxl) |
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{
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spice_qxl_flush_surfaces_async(&qxl->ssd.qxl, |
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(uint64_t)qxl_cookie_new(QXL_COOKIE_TYPE_IO, |
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QXL_IO_FLUSH_SURFACES_ASYNC)); |
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} |
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void qxl_spice_loadvm_commands(PCIQXLDevice *qxl, struct QXLCommandExt *ext, |
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uint32_t count) |
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{
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qxl->ssd.worker->loadvm_commands(qxl->ssd.worker, ext, count); |
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} |
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void qxl_spice_oom(PCIQXLDevice *qxl)
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{
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qxl->ssd.worker->oom(qxl->ssd.worker); |
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} |
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void qxl_spice_reset_memslots(PCIQXLDevice *qxl)
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{
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qxl->ssd.worker->reset_memslots(qxl->ssd.worker); |
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} |
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static void qxl_spice_destroy_surfaces_complete(PCIQXLDevice *qxl) |
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{
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qemu_mutex_lock(&qxl->track_lock); |
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memset(&qxl->guest_surfaces.cmds, 0, sizeof(qxl->guest_surfaces.cmds)); |
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qxl->guest_surfaces.count = 0;
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qemu_mutex_unlock(&qxl->track_lock); |
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} |
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static void qxl_spice_destroy_surfaces(PCIQXLDevice *qxl, qxl_async_io async) |
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{
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if (async) {
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spice_qxl_destroy_surfaces_async(&qxl->ssd.qxl, |
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(uint64_t)qxl_cookie_new(QXL_COOKIE_TYPE_IO, |
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QXL_IO_DESTROY_ALL_SURFACES_ASYNC)); |
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} else {
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qxl->ssd.worker->destroy_surfaces(qxl->ssd.worker); |
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qxl_spice_destroy_surfaces_complete(qxl); |
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} |
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} |
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void qxl_spice_reset_image_cache(PCIQXLDevice *qxl)
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{
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qxl->ssd.worker->reset_image_cache(qxl->ssd.worker); |
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} |
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void qxl_spice_reset_cursor(PCIQXLDevice *qxl)
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{
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qxl->ssd.worker->reset_cursor(qxl->ssd.worker); |
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qemu_mutex_lock(&qxl->track_lock); |
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qxl->guest_cursor = 0;
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qemu_mutex_unlock(&qxl->track_lock); |
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} |
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static inline uint32_t msb_mask(uint32_t val) |
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{
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uint32_t mask; |
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do {
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mask = ~(val - 1) & val;
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val &= ~mask; |
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} while (mask < val);
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return mask;
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} |
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static ram_addr_t qxl_rom_size(void) |
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{
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uint32_t rom_size = sizeof(QXLRom) + sizeof(QXLModes) + sizeof(qxl_modes); |
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rom_size = MAX(rom_size, TARGET_PAGE_SIZE); |
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rom_size = msb_mask(rom_size * 2 - 1); |
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return rom_size;
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} |
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static void init_qxl_rom(PCIQXLDevice *d) |
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{
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QXLRom *rom = memory_region_get_ram_ptr(&d->rom_bar); |
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QXLModes *modes = (QXLModes *)(rom + 1);
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uint32_t ram_header_size; |
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uint32_t surface0_area_size; |
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uint32_t num_pages; |
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uint32_t fb, maxfb = 0;
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int i;
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memset(rom, 0, d->rom_size);
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rom->magic = cpu_to_le32(QXL_ROM_MAGIC); |
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rom->id = cpu_to_le32(d->id); |
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rom->log_level = cpu_to_le32(d->guestdebug); |
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rom->modes_offset = cpu_to_le32(sizeof(QXLRom));
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rom->slot_gen_bits = MEMSLOT_GENERATION_BITS; |
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rom->slot_id_bits = MEMSLOT_SLOT_BITS; |
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rom->slots_start = 1;
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rom->slots_end = NUM_MEMSLOTS - 1;
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rom->n_surfaces = cpu_to_le32(NUM_SURFACES); |
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modes->n_modes = cpu_to_le32(ARRAY_SIZE(qxl_modes)); |
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for (i = 0; i < modes->n_modes; i++) { |
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fb = qxl_modes[i].y_res * qxl_modes[i].stride; |
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if (maxfb < fb) {
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maxfb = fb; |
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} |
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modes->modes[i].id = cpu_to_le32(i); |
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modes->modes[i].x_res = cpu_to_le32(qxl_modes[i].x_res); |
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modes->modes[i].y_res = cpu_to_le32(qxl_modes[i].y_res); |
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modes->modes[i].bits = cpu_to_le32(qxl_modes[i].bits); |
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modes->modes[i].stride = cpu_to_le32(qxl_modes[i].stride); |
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modes->modes[i].x_mili = cpu_to_le32(qxl_modes[i].x_mili); |
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modes->modes[i].y_mili = cpu_to_le32(qxl_modes[i].y_mili); |
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modes->modes[i].orientation = cpu_to_le32(qxl_modes[i].orientation); |
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} |
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if (maxfb < VGA_RAM_SIZE && d->id == 0) |
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maxfb = VGA_RAM_SIZE; |
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ram_header_size = ALIGN(sizeof(QXLRam), 4096); |
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surface0_area_size = ALIGN(maxfb, 4096);
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num_pages = d->vga.vram_size; |
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num_pages -= ram_header_size; |
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num_pages -= surface0_area_size; |
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num_pages = num_pages / TARGET_PAGE_SIZE; |
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rom->draw_area_offset = cpu_to_le32(0);
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rom->surface0_area_size = cpu_to_le32(surface0_area_size); |
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rom->pages_offset = cpu_to_le32(surface0_area_size); |
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rom->num_pages = cpu_to_le32(num_pages); |
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rom->ram_header_offset = cpu_to_le32(d->vga.vram_size - ram_header_size); |
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d->shadow_rom = *rom; |
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d->rom = rom; |
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d->modes = modes; |
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} |
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static void init_qxl_ram(PCIQXLDevice *d) |
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{
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uint8_t *buf; |
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uint64_t *item; |
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buf = d->vga.vram_ptr; |
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d->ram = (QXLRam *)(buf + le32_to_cpu(d->shadow_rom.ram_header_offset)); |
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d->ram->magic = cpu_to_le32(QXL_RAM_MAGIC); |
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d->ram->int_pending = cpu_to_le32(0);
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d->ram->int_mask = cpu_to_le32(0);
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d->ram->update_surface = 0;
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SPICE_RING_INIT(&d->ram->cmd_ring); |
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SPICE_RING_INIT(&d->ram->cursor_ring); |
| 330 |
SPICE_RING_INIT(&d->ram->release_ring); |
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SPICE_RING_PROD_ITEM(&d->ram->release_ring, item); |
| 332 |
*item = 0;
|
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qxl_ring_set_dirty(d); |
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} |
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|
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/* can be called from spice server thread context */
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static void qxl_set_dirty(MemoryRegion *mr, ram_addr_t addr, ram_addr_t end) |
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{
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memory_region_set_dirty(mr, addr, end - addr); |
| 340 |
} |
| 341 |
|
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static void qxl_rom_set_dirty(PCIQXLDevice *qxl) |
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{
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qxl_set_dirty(&qxl->rom_bar, 0, qxl->rom_size);
|
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} |
| 346 |
|
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/* called from spice server thread context only */
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static void qxl_ram_set_dirty(PCIQXLDevice *qxl, void *ptr) |
| 349 |
{
|
| 350 |
void *base = qxl->vga.vram_ptr;
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intptr_t offset; |
| 352 |
|
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offset = ptr - base; |
| 354 |
offset &= ~(TARGET_PAGE_SIZE-1);
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assert(offset < qxl->vga.vram_size); |
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qxl_set_dirty(&qxl->vga.vram, offset, offset + TARGET_PAGE_SIZE); |
| 357 |
} |
| 358 |
|
| 359 |
/* can be called from spice server thread context */
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| 360 |
static void qxl_ring_set_dirty(PCIQXLDevice *qxl) |
| 361 |
{
|
| 362 |
ram_addr_t addr = qxl->shadow_rom.ram_header_offset; |
| 363 |
ram_addr_t end = qxl->vga.vram_size; |
| 364 |
qxl_set_dirty(&qxl->vga.vram, addr, end); |
| 365 |
} |
| 366 |
|
| 367 |
/*
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* keep track of some command state, for savevm/loadvm.
|
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* called from spice server thread context only
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*/
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static void qxl_track_command(PCIQXLDevice *qxl, struct QXLCommandExt *ext) |
| 372 |
{
|
| 373 |
switch (le32_to_cpu(ext->cmd.type)) {
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| 374 |
case QXL_CMD_SURFACE:
|
| 375 |
{
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| 376 |
QXLSurfaceCmd *cmd = qxl_phys2virt(qxl, ext->cmd.data, ext->group_id); |
| 377 |
uint32_t id = le32_to_cpu(cmd->surface_id); |
| 378 |
PANIC_ON(id >= NUM_SURFACES); |
| 379 |
qemu_mutex_lock(&qxl->track_lock); |
| 380 |
if (cmd->type == QXL_SURFACE_CMD_CREATE) {
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qxl->guest_surfaces.cmds[id] = ext->cmd.data; |
| 382 |
qxl->guest_surfaces.count++; |
| 383 |
if (qxl->guest_surfaces.max < qxl->guest_surfaces.count)
|
| 384 |
qxl->guest_surfaces.max = qxl->guest_surfaces.count; |
| 385 |
} |
| 386 |
if (cmd->type == QXL_SURFACE_CMD_DESTROY) {
|
| 387 |
qxl->guest_surfaces.cmds[id] = 0;
|
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qxl->guest_surfaces.count--; |
| 389 |
} |
| 390 |
qemu_mutex_unlock(&qxl->track_lock); |
| 391 |
break;
|
| 392 |
} |
| 393 |
case QXL_CMD_CURSOR:
|
| 394 |
{
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| 395 |
QXLCursorCmd *cmd = qxl_phys2virt(qxl, ext->cmd.data, ext->group_id); |
| 396 |
if (cmd->type == QXL_CURSOR_SET) {
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| 397 |
qemu_mutex_lock(&qxl->track_lock); |
| 398 |
qxl->guest_cursor = ext->cmd.data; |
| 399 |
qemu_mutex_unlock(&qxl->track_lock); |
| 400 |
} |
| 401 |
break;
|
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} |
| 403 |
} |
| 404 |
} |
| 405 |
|
| 406 |
/* spice display interface callbacks */
|
| 407 |
|
| 408 |
static void interface_attach_worker(QXLInstance *sin, QXLWorker *qxl_worker) |
| 409 |
{
|
| 410 |
PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); |
| 411 |
|
| 412 |
dprint(qxl, 1, "%s:\n", __FUNCTION__); |
| 413 |
qxl->ssd.worker = qxl_worker; |
| 414 |
} |
| 415 |
|
| 416 |
static void interface_set_compression_level(QXLInstance *sin, int level) |
| 417 |
{
|
| 418 |
PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); |
| 419 |
|
| 420 |
dprint(qxl, 1, "%s: %d\n", __FUNCTION__, level); |
| 421 |
qxl->shadow_rom.compression_level = cpu_to_le32(level); |
| 422 |
qxl->rom->compression_level = cpu_to_le32(level); |
| 423 |
qxl_rom_set_dirty(qxl); |
| 424 |
} |
| 425 |
|
| 426 |
static void interface_set_mm_time(QXLInstance *sin, uint32_t mm_time) |
| 427 |
{
|
| 428 |
PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); |
| 429 |
|
| 430 |
qxl->shadow_rom.mm_clock = cpu_to_le32(mm_time); |
| 431 |
qxl->rom->mm_clock = cpu_to_le32(mm_time); |
| 432 |
qxl_rom_set_dirty(qxl); |
| 433 |
} |
| 434 |
|
| 435 |
static void interface_get_init_info(QXLInstance *sin, QXLDevInitInfo *info) |
| 436 |
{
|
| 437 |
PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); |
| 438 |
|
| 439 |
dprint(qxl, 1, "%s:\n", __FUNCTION__); |
| 440 |
info->memslot_gen_bits = MEMSLOT_GENERATION_BITS; |
| 441 |
info->memslot_id_bits = MEMSLOT_SLOT_BITS; |
| 442 |
info->num_memslots = NUM_MEMSLOTS; |
| 443 |
info->num_memslots_groups = NUM_MEMSLOTS_GROUPS; |
| 444 |
info->internal_groupslot_id = 0;
|
| 445 |
info->qxl_ram_size = le32_to_cpu(qxl->shadow_rom.num_pages) << TARGET_PAGE_BITS; |
| 446 |
info->n_surfaces = NUM_SURFACES; |
| 447 |
} |
| 448 |
|
| 449 |
static const char *qxl_mode_to_string(int mode) |
| 450 |
{
|
| 451 |
switch (mode) {
|
| 452 |
case QXL_MODE_COMPAT:
|
| 453 |
return "compat"; |
| 454 |
case QXL_MODE_NATIVE:
|
| 455 |
return "native"; |
| 456 |
case QXL_MODE_UNDEFINED:
|
| 457 |
return "undefined"; |
| 458 |
case QXL_MODE_VGA:
|
| 459 |
return "vga"; |
| 460 |
} |
| 461 |
return "INVALID"; |
| 462 |
} |
| 463 |
|
| 464 |
static const char *io_port_to_string(uint32_t io_port) |
| 465 |
{
|
| 466 |
if (io_port >= QXL_IO_RANGE_SIZE) {
|
| 467 |
return "out of range"; |
| 468 |
} |
| 469 |
static const char *io_port_to_string[QXL_IO_RANGE_SIZE + 1] = { |
| 470 |
[QXL_IO_NOTIFY_CMD] = "QXL_IO_NOTIFY_CMD",
|
| 471 |
[QXL_IO_NOTIFY_CURSOR] = "QXL_IO_NOTIFY_CURSOR",
|
| 472 |
[QXL_IO_UPDATE_AREA] = "QXL_IO_UPDATE_AREA",
|
| 473 |
[QXL_IO_UPDATE_IRQ] = "QXL_IO_UPDATE_IRQ",
|
| 474 |
[QXL_IO_NOTIFY_OOM] = "QXL_IO_NOTIFY_OOM",
|
| 475 |
[QXL_IO_RESET] = "QXL_IO_RESET",
|
| 476 |
[QXL_IO_SET_MODE] = "QXL_IO_SET_MODE",
|
| 477 |
[QXL_IO_LOG] = "QXL_IO_LOG",
|
| 478 |
[QXL_IO_MEMSLOT_ADD] = "QXL_IO_MEMSLOT_ADD",
|
| 479 |
[QXL_IO_MEMSLOT_DEL] = "QXL_IO_MEMSLOT_DEL",
|
| 480 |
[QXL_IO_DETACH_PRIMARY] = "QXL_IO_DETACH_PRIMARY",
|
| 481 |
[QXL_IO_ATTACH_PRIMARY] = "QXL_IO_ATTACH_PRIMARY",
|
| 482 |
[QXL_IO_CREATE_PRIMARY] = "QXL_IO_CREATE_PRIMARY",
|
| 483 |
[QXL_IO_DESTROY_PRIMARY] = "QXL_IO_DESTROY_PRIMARY",
|
| 484 |
[QXL_IO_DESTROY_SURFACE_WAIT] = "QXL_IO_DESTROY_SURFACE_WAIT",
|
| 485 |
[QXL_IO_DESTROY_ALL_SURFACES] = "QXL_IO_DESTROY_ALL_SURFACES",
|
| 486 |
[QXL_IO_UPDATE_AREA_ASYNC] = "QXL_IO_UPDATE_AREA_ASYNC",
|
| 487 |
[QXL_IO_MEMSLOT_ADD_ASYNC] = "QXL_IO_MEMSLOT_ADD_ASYNC",
|
| 488 |
[QXL_IO_CREATE_PRIMARY_ASYNC] = "QXL_IO_CREATE_PRIMARY_ASYNC",
|
| 489 |
[QXL_IO_DESTROY_PRIMARY_ASYNC] = "QXL_IO_DESTROY_PRIMARY_ASYNC",
|
| 490 |
[QXL_IO_DESTROY_SURFACE_ASYNC] = "QXL_IO_DESTROY_SURFACE_ASYNC",
|
| 491 |
[QXL_IO_DESTROY_ALL_SURFACES_ASYNC] |
| 492 |
= "QXL_IO_DESTROY_ALL_SURFACES_ASYNC",
|
| 493 |
[QXL_IO_FLUSH_SURFACES_ASYNC] = "QXL_IO_FLUSH_SURFACES_ASYNC",
|
| 494 |
[QXL_IO_FLUSH_RELEASE] = "QXL_IO_FLUSH_RELEASE",
|
| 495 |
}; |
| 496 |
return io_port_to_string[io_port];
|
| 497 |
} |
| 498 |
|
| 499 |
/* called from spice server thread context only */
|
| 500 |
static int interface_get_command(QXLInstance *sin, struct QXLCommandExt *ext) |
| 501 |
{
|
| 502 |
PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); |
| 503 |
SimpleSpiceUpdate *update; |
| 504 |
QXLCommandRing *ring; |
| 505 |
QXLCommand *cmd; |
| 506 |
int notify, ret;
|
| 507 |
|
| 508 |
switch (qxl->mode) {
|
| 509 |
case QXL_MODE_VGA:
|
| 510 |
dprint(qxl, 2, "%s: vga\n", __FUNCTION__); |
| 511 |
ret = false;
|
| 512 |
qemu_mutex_lock(&qxl->ssd.lock); |
| 513 |
if (qxl->ssd.update != NULL) { |
| 514 |
update = qxl->ssd.update; |
| 515 |
qxl->ssd.update = NULL;
|
| 516 |
*ext = update->ext; |
| 517 |
ret = true;
|
| 518 |
} |
| 519 |
qemu_mutex_unlock(&qxl->ssd.lock); |
| 520 |
if (ret) {
|
| 521 |
dprint(qxl, 2, "%s %s\n", __FUNCTION__, qxl_mode_to_string(qxl->mode)); |
| 522 |
qxl_log_command(qxl, "vga", ext);
|
| 523 |
} |
| 524 |
return ret;
|
| 525 |
case QXL_MODE_COMPAT:
|
| 526 |
case QXL_MODE_NATIVE:
|
| 527 |
case QXL_MODE_UNDEFINED:
|
| 528 |
dprint(qxl, 4, "%s: %s\n", __FUNCTION__, qxl_mode_to_string(qxl->mode)); |
| 529 |
ring = &qxl->ram->cmd_ring; |
| 530 |
if (SPICE_RING_IS_EMPTY(ring)) {
|
| 531 |
return false; |
| 532 |
} |
| 533 |
dprint(qxl, 2, "%s: %s\n", __FUNCTION__, qxl_mode_to_string(qxl->mode)); |
| 534 |
SPICE_RING_CONS_ITEM(ring, cmd); |
| 535 |
ext->cmd = *cmd; |
| 536 |
ext->group_id = MEMSLOT_GROUP_GUEST; |
| 537 |
ext->flags = qxl->cmdflags; |
| 538 |
SPICE_RING_POP(ring, notify); |
| 539 |
qxl_ring_set_dirty(qxl); |
| 540 |
if (notify) {
|
| 541 |
qxl_send_events(qxl, QXL_INTERRUPT_DISPLAY); |
| 542 |
} |
| 543 |
qxl->guest_primary.commands++; |
| 544 |
qxl_track_command(qxl, ext); |
| 545 |
qxl_log_command(qxl, "cmd", ext);
|
| 546 |
return true; |
| 547 |
default:
|
| 548 |
return false; |
| 549 |
} |
| 550 |
} |
| 551 |
|
| 552 |
/* called from spice server thread context only */
|
| 553 |
static int interface_req_cmd_notification(QXLInstance *sin) |
| 554 |
{
|
| 555 |
PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); |
| 556 |
int wait = 1; |
| 557 |
|
| 558 |
switch (qxl->mode) {
|
| 559 |
case QXL_MODE_COMPAT:
|
| 560 |
case QXL_MODE_NATIVE:
|
| 561 |
case QXL_MODE_UNDEFINED:
|
| 562 |
SPICE_RING_CONS_WAIT(&qxl->ram->cmd_ring, wait); |
| 563 |
qxl_ring_set_dirty(qxl); |
| 564 |
break;
|
| 565 |
default:
|
| 566 |
/* nothing */
|
| 567 |
break;
|
| 568 |
} |
| 569 |
return wait;
|
| 570 |
} |
| 571 |
|
| 572 |
/* called from spice server thread context only */
|
| 573 |
static inline void qxl_push_free_res(PCIQXLDevice *d, int flush) |
| 574 |
{
|
| 575 |
QXLReleaseRing *ring = &d->ram->release_ring; |
| 576 |
uint64_t *item; |
| 577 |
int notify;
|
| 578 |
|
| 579 |
#define QXL_FREE_BUNCH_SIZE 32 |
| 580 |
|
| 581 |
if (ring->prod - ring->cons + 1 == ring->num_items) { |
| 582 |
/* ring full -- can't push */
|
| 583 |
return;
|
| 584 |
} |
| 585 |
if (!flush && d->oom_running) {
|
| 586 |
/* collect everything from oom handler before pushing */
|
| 587 |
return;
|
| 588 |
} |
| 589 |
if (!flush && d->num_free_res < QXL_FREE_BUNCH_SIZE) {
|
| 590 |
/* collect a bit more before pushing */
|
| 591 |
return;
|
| 592 |
} |
| 593 |
|
| 594 |
SPICE_RING_PUSH(ring, notify); |
| 595 |
dprint(d, 2, "free: push %d items, notify %s, ring %d/%d [%d,%d]\n", |
| 596 |
d->num_free_res, notify ? "yes" : "no", |
| 597 |
ring->prod - ring->cons, ring->num_items, |
| 598 |
ring->prod, ring->cons); |
| 599 |
if (notify) {
|
| 600 |
qxl_send_events(d, QXL_INTERRUPT_DISPLAY); |
| 601 |
} |
| 602 |
SPICE_RING_PROD_ITEM(ring, item); |
| 603 |
*item = 0;
|
| 604 |
d->num_free_res = 0;
|
| 605 |
d->last_release = NULL;
|
| 606 |
qxl_ring_set_dirty(d); |
| 607 |
} |
| 608 |
|
| 609 |
/* called from spice server thread context only */
|
| 610 |
static void interface_release_resource(QXLInstance *sin, |
| 611 |
struct QXLReleaseInfoExt ext)
|
| 612 |
{
|
| 613 |
PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); |
| 614 |
QXLReleaseRing *ring; |
| 615 |
uint64_t *item, id; |
| 616 |
|
| 617 |
if (ext.group_id == MEMSLOT_GROUP_HOST) {
|
| 618 |
/* host group -> vga mode update request */
|
| 619 |
qemu_spice_destroy_update(&qxl->ssd, (void *)(intptr_t)ext.info->id);
|
| 620 |
return;
|
| 621 |
} |
| 622 |
|
| 623 |
/*
|
| 624 |
* ext->info points into guest-visible memory
|
| 625 |
* pci bar 0, $command.release_info
|
| 626 |
*/
|
| 627 |
ring = &qxl->ram->release_ring; |
| 628 |
SPICE_RING_PROD_ITEM(ring, item); |
| 629 |
if (*item == 0) { |
| 630 |
/* stick head into the ring */
|
| 631 |
id = ext.info->id; |
| 632 |
ext.info->next = 0;
|
| 633 |
qxl_ram_set_dirty(qxl, &ext.info->next); |
| 634 |
*item = id; |
| 635 |
qxl_ring_set_dirty(qxl); |
| 636 |
} else {
|
| 637 |
/* append item to the list */
|
| 638 |
qxl->last_release->next = ext.info->id; |
| 639 |
qxl_ram_set_dirty(qxl, &qxl->last_release->next); |
| 640 |
ext.info->next = 0;
|
| 641 |
qxl_ram_set_dirty(qxl, &ext.info->next); |
| 642 |
} |
| 643 |
qxl->last_release = ext.info; |
| 644 |
qxl->num_free_res++; |
| 645 |
dprint(qxl, 3, "%4d\r", qxl->num_free_res); |
| 646 |
qxl_push_free_res(qxl, 0);
|
| 647 |
} |
| 648 |
|
| 649 |
/* called from spice server thread context only */
|
| 650 |
static int interface_get_cursor_command(QXLInstance *sin, struct QXLCommandExt *ext) |
| 651 |
{
|
| 652 |
PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); |
| 653 |
QXLCursorRing *ring; |
| 654 |
QXLCommand *cmd; |
| 655 |
int notify;
|
| 656 |
|
| 657 |
switch (qxl->mode) {
|
| 658 |
case QXL_MODE_COMPAT:
|
| 659 |
case QXL_MODE_NATIVE:
|
| 660 |
case QXL_MODE_UNDEFINED:
|
| 661 |
ring = &qxl->ram->cursor_ring; |
| 662 |
if (SPICE_RING_IS_EMPTY(ring)) {
|
| 663 |
return false; |
| 664 |
} |
| 665 |
SPICE_RING_CONS_ITEM(ring, cmd); |
| 666 |
ext->cmd = *cmd; |
| 667 |
ext->group_id = MEMSLOT_GROUP_GUEST; |
| 668 |
ext->flags = qxl->cmdflags; |
| 669 |
SPICE_RING_POP(ring, notify); |
| 670 |
qxl_ring_set_dirty(qxl); |
| 671 |
if (notify) {
|
| 672 |
qxl_send_events(qxl, QXL_INTERRUPT_CURSOR); |
| 673 |
} |
| 674 |
qxl->guest_primary.commands++; |
| 675 |
qxl_track_command(qxl, ext); |
| 676 |
qxl_log_command(qxl, "csr", ext);
|
| 677 |
if (qxl->id == 0) { |
| 678 |
qxl_render_cursor(qxl, ext); |
| 679 |
} |
| 680 |
return true; |
| 681 |
default:
|
| 682 |
return false; |
| 683 |
} |
| 684 |
} |
| 685 |
|
| 686 |
/* called from spice server thread context only */
|
| 687 |
static int interface_req_cursor_notification(QXLInstance *sin) |
| 688 |
{
|
| 689 |
PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); |
| 690 |
int wait = 1; |
| 691 |
|
| 692 |
switch (qxl->mode) {
|
| 693 |
case QXL_MODE_COMPAT:
|
| 694 |
case QXL_MODE_NATIVE:
|
| 695 |
case QXL_MODE_UNDEFINED:
|
| 696 |
SPICE_RING_CONS_WAIT(&qxl->ram->cursor_ring, wait); |
| 697 |
qxl_ring_set_dirty(qxl); |
| 698 |
break;
|
| 699 |
default:
|
| 700 |
/* nothing */
|
| 701 |
break;
|
| 702 |
} |
| 703 |
return wait;
|
| 704 |
} |
| 705 |
|
| 706 |
/* called from spice server thread context */
|
| 707 |
static void interface_notify_update(QXLInstance *sin, uint32_t update_id) |
| 708 |
{
|
| 709 |
fprintf(stderr, "%s: abort()\n", __FUNCTION__);
|
| 710 |
abort(); |
| 711 |
} |
| 712 |
|
| 713 |
/* called from spice server thread context only */
|
| 714 |
static int interface_flush_resources(QXLInstance *sin) |
| 715 |
{
|
| 716 |
PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); |
| 717 |
int ret;
|
| 718 |
|
| 719 |
dprint(qxl, 1, "free: guest flush (have %d)\n", qxl->num_free_res); |
| 720 |
ret = qxl->num_free_res; |
| 721 |
if (ret) {
|
| 722 |
qxl_push_free_res(qxl, 1);
|
| 723 |
} |
| 724 |
return ret;
|
| 725 |
} |
| 726 |
|
| 727 |
static void qxl_create_guest_primary_complete(PCIQXLDevice *d); |
| 728 |
|
| 729 |
/* called from spice server thread context only */
|
| 730 |
static void interface_async_complete_io(PCIQXLDevice *qxl, QXLCookie *cookie) |
| 731 |
{
|
| 732 |
uint32_t current_async; |
| 733 |
|
| 734 |
qemu_mutex_lock(&qxl->async_lock); |
| 735 |
current_async = qxl->current_async; |
| 736 |
qxl->current_async = QXL_UNDEFINED_IO; |
| 737 |
qemu_mutex_unlock(&qxl->async_lock); |
| 738 |
|
| 739 |
dprint(qxl, 2, "async_complete: %d (%p) done\n", current_async, cookie); |
| 740 |
if (!cookie) {
|
| 741 |
fprintf(stderr, "qxl: %s: error, cookie is NULL\n", __func__);
|
| 742 |
return;
|
| 743 |
} |
| 744 |
if (cookie && current_async != cookie->io) {
|
| 745 |
fprintf(stderr, |
| 746 |
"qxl: %s: error: current_async = %d != %ld = cookie->io\n",
|
| 747 |
__func__, current_async, cookie->io); |
| 748 |
} |
| 749 |
switch (current_async) {
|
| 750 |
case QXL_IO_MEMSLOT_ADD_ASYNC:
|
| 751 |
case QXL_IO_DESTROY_PRIMARY_ASYNC:
|
| 752 |
case QXL_IO_UPDATE_AREA_ASYNC:
|
| 753 |
case QXL_IO_FLUSH_SURFACES_ASYNC:
|
| 754 |
break;
|
| 755 |
case QXL_IO_CREATE_PRIMARY_ASYNC:
|
| 756 |
qxl_create_guest_primary_complete(qxl); |
| 757 |
break;
|
| 758 |
case QXL_IO_DESTROY_ALL_SURFACES_ASYNC:
|
| 759 |
qxl_spice_destroy_surfaces_complete(qxl); |
| 760 |
break;
|
| 761 |
case QXL_IO_DESTROY_SURFACE_ASYNC:
|
| 762 |
qxl_spice_destroy_surface_wait_complete(qxl, cookie->u.surface_id); |
| 763 |
break;
|
| 764 |
default:
|
| 765 |
fprintf(stderr, "qxl: %s: unexpected current_async %d\n", __func__,
|
| 766 |
current_async); |
| 767 |
} |
| 768 |
qxl_send_events(qxl, QXL_INTERRUPT_IO_CMD); |
| 769 |
} |
| 770 |
|
| 771 |
/* called from spice server thread context only */
|
| 772 |
static void interface_update_area_complete(QXLInstance *sin, |
| 773 |
uint32_t surface_id, |
| 774 |
QXLRect *dirty, uint32_t num_updated_rects) |
| 775 |
{
|
| 776 |
PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); |
| 777 |
int i;
|
| 778 |
int qxl_i;
|
| 779 |
|
| 780 |
qemu_mutex_lock(&qxl->ssd.lock); |
| 781 |
if (surface_id != 0 || !qxl->render_update_cookie_num) { |
| 782 |
qemu_mutex_unlock(&qxl->ssd.lock); |
| 783 |
return;
|
| 784 |
} |
| 785 |
if (qxl->num_dirty_rects + num_updated_rects > QXL_NUM_DIRTY_RECTS) {
|
| 786 |
/*
|
| 787 |
* overflow - treat this as a full update. Not expected to be common.
|
| 788 |
*/
|
| 789 |
dprint(qxl, 1, "%s: overflow of dirty rects\n", __func__); |
| 790 |
qxl->guest_primary.resized = 1;
|
| 791 |
} |
| 792 |
if (qxl->guest_primary.resized) {
|
| 793 |
/*
|
| 794 |
* Don't bother copying or scheduling the bh since we will flip
|
| 795 |
* the whole area anyway on completion of the update_area async call
|
| 796 |
*/
|
| 797 |
qemu_mutex_unlock(&qxl->ssd.lock); |
| 798 |
return;
|
| 799 |
} |
| 800 |
qxl_i = qxl->num_dirty_rects; |
| 801 |
for (i = 0; i < num_updated_rects; i++) { |
| 802 |
qxl->dirty[qxl_i++] = dirty[i]; |
| 803 |
} |
| 804 |
qxl->num_dirty_rects += num_updated_rects; |
| 805 |
dprint(qxl, 1, "%s: scheduling update_area_bh, #dirty %d\n", |
| 806 |
__func__, qxl->num_dirty_rects); |
| 807 |
qemu_bh_schedule(qxl->update_area_bh); |
| 808 |
qemu_mutex_unlock(&qxl->ssd.lock); |
| 809 |
} |
| 810 |
|
| 811 |
/* called from spice server thread context only */
|
| 812 |
static void interface_async_complete(QXLInstance *sin, uint64_t cookie_token) |
| 813 |
{
|
| 814 |
PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); |
| 815 |
QXLCookie *cookie = (QXLCookie *)cookie_token; |
| 816 |
|
| 817 |
switch (cookie->type) {
|
| 818 |
case QXL_COOKIE_TYPE_IO:
|
| 819 |
interface_async_complete_io(qxl, cookie); |
| 820 |
g_free(cookie); |
| 821 |
break;
|
| 822 |
case QXL_COOKIE_TYPE_RENDER_UPDATE_AREA:
|
| 823 |
qxl_render_update_area_done(qxl, cookie); |
| 824 |
break;
|
| 825 |
default:
|
| 826 |
fprintf(stderr, "qxl: %s: unexpected cookie type %d\n",
|
| 827 |
__func__, cookie->type); |
| 828 |
g_free(cookie); |
| 829 |
} |
| 830 |
} |
| 831 |
|
| 832 |
static const QXLInterface qxl_interface = { |
| 833 |
.base.type = SPICE_INTERFACE_QXL, |
| 834 |
.base.description = "qxl gpu",
|
| 835 |
.base.major_version = SPICE_INTERFACE_QXL_MAJOR, |
| 836 |
.base.minor_version = SPICE_INTERFACE_QXL_MINOR, |
| 837 |
|
| 838 |
.attache_worker = interface_attach_worker, |
| 839 |
.set_compression_level = interface_set_compression_level, |
| 840 |
.set_mm_time = interface_set_mm_time, |
| 841 |
.get_init_info = interface_get_init_info, |
| 842 |
|
| 843 |
/* the callbacks below are called from spice server thread context */
|
| 844 |
.get_command = interface_get_command, |
| 845 |
.req_cmd_notification = interface_req_cmd_notification, |
| 846 |
.release_resource = interface_release_resource, |
| 847 |
.get_cursor_command = interface_get_cursor_command, |
| 848 |
.req_cursor_notification = interface_req_cursor_notification, |
| 849 |
.notify_update = interface_notify_update, |
| 850 |
.flush_resources = interface_flush_resources, |
| 851 |
.async_complete = interface_async_complete, |
| 852 |
.update_area_complete = interface_update_area_complete, |
| 853 |
}; |
| 854 |
|
| 855 |
static void qxl_enter_vga_mode(PCIQXLDevice *d) |
| 856 |
{
|
| 857 |
if (d->mode == QXL_MODE_VGA) {
|
| 858 |
return;
|
| 859 |
} |
| 860 |
dprint(d, 1, "%s\n", __FUNCTION__); |
| 861 |
qemu_spice_create_host_primary(&d->ssd); |
| 862 |
d->mode = QXL_MODE_VGA; |
| 863 |
memset(&d->ssd.dirty, 0, sizeof(d->ssd.dirty)); |
| 864 |
} |
| 865 |
|
| 866 |
static void qxl_exit_vga_mode(PCIQXLDevice *d) |
| 867 |
{
|
| 868 |
if (d->mode != QXL_MODE_VGA) {
|
| 869 |
return;
|
| 870 |
} |
| 871 |
dprint(d, 1, "%s\n", __FUNCTION__); |
| 872 |
qxl_destroy_primary(d, QXL_SYNC); |
| 873 |
} |
| 874 |
|
| 875 |
static void qxl_update_irq(PCIQXLDevice *d) |
| 876 |
{
|
| 877 |
uint32_t pending = le32_to_cpu(d->ram->int_pending); |
| 878 |
uint32_t mask = le32_to_cpu(d->ram->int_mask); |
| 879 |
int level = !!(pending & mask);
|
| 880 |
qemu_set_irq(d->pci.irq[0], level);
|
| 881 |
qxl_ring_set_dirty(d); |
| 882 |
} |
| 883 |
|
| 884 |
static void qxl_check_state(PCIQXLDevice *d) |
| 885 |
{
|
| 886 |
QXLRam *ram = d->ram; |
| 887 |
|
| 888 |
assert(!d->ssd.running || SPICE_RING_IS_EMPTY(&ram->cmd_ring)); |
| 889 |
assert(!d->ssd.running || SPICE_RING_IS_EMPTY(&ram->cursor_ring)); |
| 890 |
} |
| 891 |
|
| 892 |
static void qxl_reset_state(PCIQXLDevice *d) |
| 893 |
{
|
| 894 |
QXLRom *rom = d->rom; |
| 895 |
|
| 896 |
qxl_check_state(d); |
| 897 |
d->shadow_rom.update_id = cpu_to_le32(0);
|
| 898 |
*rom = d->shadow_rom; |
| 899 |
qxl_rom_set_dirty(d); |
| 900 |
init_qxl_ram(d); |
| 901 |
d->num_free_res = 0;
|
| 902 |
d->last_release = NULL;
|
| 903 |
memset(&d->ssd.dirty, 0, sizeof(d->ssd.dirty)); |
| 904 |
} |
| 905 |
|
| 906 |
static void qxl_soft_reset(PCIQXLDevice *d) |
| 907 |
{
|
| 908 |
dprint(d, 1, "%s:\n", __FUNCTION__); |
| 909 |
qxl_check_state(d); |
| 910 |
|
| 911 |
if (d->id == 0) { |
| 912 |
qxl_enter_vga_mode(d); |
| 913 |
} else {
|
| 914 |
d->mode = QXL_MODE_UNDEFINED; |
| 915 |
} |
| 916 |
} |
| 917 |
|
| 918 |
static void qxl_hard_reset(PCIQXLDevice *d, int loadvm) |
| 919 |
{
|
| 920 |
dprint(d, 1, "%s: start%s\n", __FUNCTION__, |
| 921 |
loadvm ? " (loadvm)" : ""); |
| 922 |
|
| 923 |
qxl_spice_reset_cursor(d); |
| 924 |
qxl_spice_reset_image_cache(d); |
| 925 |
qxl_reset_surfaces(d); |
| 926 |
qxl_reset_memslots(d); |
| 927 |
|
| 928 |
/* pre loadvm reset must not touch QXLRam. This lives in
|
| 929 |
* device memory, is migrated together with RAM and thus
|
| 930 |
* already loaded at this point */
|
| 931 |
if (!loadvm) {
|
| 932 |
qxl_reset_state(d); |
| 933 |
} |
| 934 |
qemu_spice_create_host_memslot(&d->ssd); |
| 935 |
qxl_soft_reset(d); |
| 936 |
|
| 937 |
dprint(d, 1, "%s: done\n", __FUNCTION__); |
| 938 |
} |
| 939 |
|
| 940 |
static void qxl_reset_handler(DeviceState *dev) |
| 941 |
{
|
| 942 |
PCIQXLDevice *d = DO_UPCAST(PCIQXLDevice, pci.qdev, dev); |
| 943 |
qxl_hard_reset(d, 0);
|
| 944 |
} |
| 945 |
|
| 946 |
static void qxl_vga_ioport_write(void *opaque, uint32_t addr, uint32_t val) |
| 947 |
{
|
| 948 |
VGACommonState *vga = opaque; |
| 949 |
PCIQXLDevice *qxl = container_of(vga, PCIQXLDevice, vga); |
| 950 |
|
| 951 |
if (qxl->mode != QXL_MODE_VGA) {
|
| 952 |
dprint(qxl, 1, "%s\n", __FUNCTION__); |
| 953 |
qxl_destroy_primary(qxl, QXL_SYNC); |
| 954 |
qxl_soft_reset(qxl); |
| 955 |
} |
| 956 |
vga_ioport_write(opaque, addr, val); |
| 957 |
} |
| 958 |
|
| 959 |
static const MemoryRegionPortio qxl_vga_portio_list[] = { |
| 960 |
{ 0x04, 2, 1, .read = vga_ioport_read,
|
| 961 |
.write = qxl_vga_ioport_write }, /* 3b4 */
|
| 962 |
{ 0x0a, 1, 1, .read = vga_ioport_read,
|
| 963 |
.write = qxl_vga_ioport_write }, /* 3ba */
|
| 964 |
{ 0x10, 16, 1, .read = vga_ioport_read,
|
| 965 |
.write = qxl_vga_ioport_write }, /* 3c0 */
|
| 966 |
{ 0x24, 2, 1, .read = vga_ioport_read,
|
| 967 |
.write = qxl_vga_ioport_write }, /* 3d4 */
|
| 968 |
{ 0x2a, 1, 1, .read = vga_ioport_read,
|
| 969 |
.write = qxl_vga_ioport_write }, /* 3da */
|
| 970 |
PORTIO_END_OF_LIST(), |
| 971 |
}; |
| 972 |
|
| 973 |
static void qxl_add_memslot(PCIQXLDevice *d, uint32_t slot_id, uint64_t delta, |
| 974 |
qxl_async_io async) |
| 975 |
{
|
| 976 |
static const int regions[] = { |
| 977 |
QXL_RAM_RANGE_INDEX, |
| 978 |
QXL_VRAM_RANGE_INDEX, |
| 979 |
QXL_VRAM64_RANGE_INDEX, |
| 980 |
}; |
| 981 |
uint64_t guest_start; |
| 982 |
uint64_t guest_end; |
| 983 |
int pci_region;
|
| 984 |
pcibus_t pci_start; |
| 985 |
pcibus_t pci_end; |
| 986 |
intptr_t virt_start; |
| 987 |
QXLDevMemSlot memslot; |
| 988 |
int i;
|
| 989 |
|
| 990 |
guest_start = le64_to_cpu(d->guest_slots[slot_id].slot.mem_start); |
| 991 |
guest_end = le64_to_cpu(d->guest_slots[slot_id].slot.mem_end); |
| 992 |
|
| 993 |
dprint(d, 1, "%s: slot %d: guest phys 0x%" PRIx64 " - 0x%" PRIx64 "\n", |
| 994 |
__FUNCTION__, slot_id, |
| 995 |
guest_start, guest_end); |
| 996 |
|
| 997 |
PANIC_ON(slot_id >= NUM_MEMSLOTS); |
| 998 |
PANIC_ON(guest_start > guest_end); |
| 999 |
|
| 1000 |
for (i = 0; i < ARRAY_SIZE(regions); i++) { |
| 1001 |
pci_region = regions[i]; |
| 1002 |
pci_start = d->pci.io_regions[pci_region].addr; |
| 1003 |
pci_end = pci_start + d->pci.io_regions[pci_region].size; |
| 1004 |
/* mapped? */
|
| 1005 |
if (pci_start == -1) { |
| 1006 |
continue;
|
| 1007 |
} |
| 1008 |
/* start address in range ? */
|
| 1009 |
if (guest_start < pci_start || guest_start > pci_end) {
|
| 1010 |
continue;
|
| 1011 |
} |
| 1012 |
/* end address in range ? */
|
| 1013 |
if (guest_end > pci_end) {
|
| 1014 |
continue;
|
| 1015 |
} |
| 1016 |
/* passed */
|
| 1017 |
break;
|
| 1018 |
} |
| 1019 |
PANIC_ON(i == ARRAY_SIZE(regions)); /* finished loop without match */
|
| 1020 |
|
| 1021 |
switch (pci_region) {
|
| 1022 |
case QXL_RAM_RANGE_INDEX:
|
| 1023 |
virt_start = (intptr_t)memory_region_get_ram_ptr(&d->vga.vram); |
| 1024 |
break;
|
| 1025 |
case QXL_VRAM_RANGE_INDEX:
|
| 1026 |
case 4 /* vram 64bit */: |
| 1027 |
virt_start = (intptr_t)memory_region_get_ram_ptr(&d->vram_bar); |
| 1028 |
break;
|
| 1029 |
default:
|
| 1030 |
/* should not happen */
|
| 1031 |
abort(); |
| 1032 |
} |
| 1033 |
|
| 1034 |
memslot.slot_id = slot_id; |
| 1035 |
memslot.slot_group_id = MEMSLOT_GROUP_GUEST; /* guest group */
|
| 1036 |
memslot.virt_start = virt_start + (guest_start - pci_start); |
| 1037 |
memslot.virt_end = virt_start + (guest_end - pci_start); |
| 1038 |
memslot.addr_delta = memslot.virt_start - delta; |
| 1039 |
memslot.generation = d->rom->slot_generation = 0;
|
| 1040 |
qxl_rom_set_dirty(d); |
| 1041 |
|
| 1042 |
dprint(d, 1, "%s: slot %d: host virt 0x%lx - 0x%lx\n", |
| 1043 |
__FUNCTION__, memslot.slot_id, |
| 1044 |
memslot.virt_start, memslot.virt_end); |
| 1045 |
|
| 1046 |
qemu_spice_add_memslot(&d->ssd, &memslot, async); |
| 1047 |
d->guest_slots[slot_id].ptr = (void*)memslot.virt_start;
|
| 1048 |
d->guest_slots[slot_id].size = memslot.virt_end - memslot.virt_start; |
| 1049 |
d->guest_slots[slot_id].delta = delta; |
| 1050 |
d->guest_slots[slot_id].active = 1;
|
| 1051 |
} |
| 1052 |
|
| 1053 |
static void qxl_del_memslot(PCIQXLDevice *d, uint32_t slot_id) |
| 1054 |
{
|
| 1055 |
dprint(d, 1, "%s: slot %d\n", __FUNCTION__, slot_id); |
| 1056 |
qemu_spice_del_memslot(&d->ssd, MEMSLOT_GROUP_HOST, slot_id); |
| 1057 |
d->guest_slots[slot_id].active = 0;
|
| 1058 |
} |
| 1059 |
|
| 1060 |
static void qxl_reset_memslots(PCIQXLDevice *d) |
| 1061 |
{
|
| 1062 |
dprint(d, 1, "%s:\n", __FUNCTION__); |
| 1063 |
qxl_spice_reset_memslots(d); |
| 1064 |
memset(&d->guest_slots, 0, sizeof(d->guest_slots)); |
| 1065 |
} |
| 1066 |
|
| 1067 |
static void qxl_reset_surfaces(PCIQXLDevice *d) |
| 1068 |
{
|
| 1069 |
dprint(d, 1, "%s:\n", __FUNCTION__); |
| 1070 |
d->mode = QXL_MODE_UNDEFINED; |
| 1071 |
qxl_spice_destroy_surfaces(d, QXL_SYNC); |
| 1072 |
} |
| 1073 |
|
| 1074 |
/* can be also called from spice server thread context */
|
| 1075 |
void *qxl_phys2virt(PCIQXLDevice *qxl, QXLPHYSICAL pqxl, int group_id) |
| 1076 |
{
|
| 1077 |
uint64_t phys = le64_to_cpu(pqxl); |
| 1078 |
uint32_t slot = (phys >> (64 - 8)) & 0xff; |
| 1079 |
uint64_t offset = phys & 0xffffffffffff;
|
| 1080 |
|
| 1081 |
switch (group_id) {
|
| 1082 |
case MEMSLOT_GROUP_HOST:
|
| 1083 |
return (void *)(intptr_t)offset; |
| 1084 |
case MEMSLOT_GROUP_GUEST:
|
| 1085 |
PANIC_ON(slot >= NUM_MEMSLOTS); |
| 1086 |
PANIC_ON(!qxl->guest_slots[slot].active); |
| 1087 |
PANIC_ON(offset < qxl->guest_slots[slot].delta); |
| 1088 |
offset -= qxl->guest_slots[slot].delta; |
| 1089 |
PANIC_ON(offset > qxl->guest_slots[slot].size) |
| 1090 |
return qxl->guest_slots[slot].ptr + offset;
|
| 1091 |
default:
|
| 1092 |
PANIC_ON(1);
|
| 1093 |
} |
| 1094 |
} |
| 1095 |
|
| 1096 |
static void qxl_create_guest_primary_complete(PCIQXLDevice *qxl) |
| 1097 |
{
|
| 1098 |
/* for local rendering */
|
| 1099 |
qxl_render_resize(qxl); |
| 1100 |
} |
| 1101 |
|
| 1102 |
static void qxl_create_guest_primary(PCIQXLDevice *qxl, int loadvm, |
| 1103 |
qxl_async_io async) |
| 1104 |
{
|
| 1105 |
QXLDevSurfaceCreate surface; |
| 1106 |
QXLSurfaceCreate *sc = &qxl->guest_primary.surface; |
| 1107 |
|
| 1108 |
assert(qxl->mode != QXL_MODE_NATIVE); |
| 1109 |
qxl_exit_vga_mode(qxl); |
| 1110 |
|
| 1111 |
dprint(qxl, 1, "%s: %dx%d\n", __FUNCTION__, |
| 1112 |
le32_to_cpu(sc->width), le32_to_cpu(sc->height)); |
| 1113 |
|
| 1114 |
surface.format = le32_to_cpu(sc->format); |
| 1115 |
surface.height = le32_to_cpu(sc->height); |
| 1116 |
surface.mem = le64_to_cpu(sc->mem); |
| 1117 |
surface.position = le32_to_cpu(sc->position); |
| 1118 |
surface.stride = le32_to_cpu(sc->stride); |
| 1119 |
surface.width = le32_to_cpu(sc->width); |
| 1120 |
surface.type = le32_to_cpu(sc->type); |
| 1121 |
surface.flags = le32_to_cpu(sc->flags); |
| 1122 |
|
| 1123 |
surface.mouse_mode = true;
|
| 1124 |
surface.group_id = MEMSLOT_GROUP_GUEST; |
| 1125 |
if (loadvm) {
|
| 1126 |
surface.flags |= QXL_SURF_FLAG_KEEP_DATA; |
| 1127 |
} |
| 1128 |
|
| 1129 |
qxl->mode = QXL_MODE_NATIVE; |
| 1130 |
qxl->cmdflags = 0;
|
| 1131 |
qemu_spice_create_primary_surface(&qxl->ssd, 0, &surface, async);
|
| 1132 |
|
| 1133 |
if (async == QXL_SYNC) {
|
| 1134 |
qxl_create_guest_primary_complete(qxl); |
| 1135 |
} |
| 1136 |
} |
| 1137 |
|
| 1138 |
/* return 1 if surface destoy was initiated (in QXL_ASYNC case) or
|
| 1139 |
* done (in QXL_SYNC case), 0 otherwise. */
|
| 1140 |
static int qxl_destroy_primary(PCIQXLDevice *d, qxl_async_io async) |
| 1141 |
{
|
| 1142 |
if (d->mode == QXL_MODE_UNDEFINED) {
|
| 1143 |
return 0; |
| 1144 |
} |
| 1145 |
dprint(d, 1, "%s\n", __FUNCTION__); |
| 1146 |
d->mode = QXL_MODE_UNDEFINED; |
| 1147 |
qemu_spice_destroy_primary_surface(&d->ssd, 0, async);
|
| 1148 |
qxl_spice_reset_cursor(d); |
| 1149 |
return 1; |
| 1150 |
} |
| 1151 |
|
| 1152 |
static void qxl_set_mode(PCIQXLDevice *d, int modenr, int loadvm) |
| 1153 |
{
|
| 1154 |
pcibus_t start = d->pci.io_regions[QXL_RAM_RANGE_INDEX].addr; |
| 1155 |
pcibus_t end = d->pci.io_regions[QXL_RAM_RANGE_INDEX].size + start; |
| 1156 |
QXLMode *mode = d->modes->modes + modenr; |
| 1157 |
uint64_t devmem = d->pci.io_regions[QXL_RAM_RANGE_INDEX].addr; |
| 1158 |
QXLMemSlot slot = {
|
| 1159 |
.mem_start = start, |
| 1160 |
.mem_end = end |
| 1161 |
}; |
| 1162 |
QXLSurfaceCreate surface = {
|
| 1163 |
.width = mode->x_res, |
| 1164 |
.height = mode->y_res, |
| 1165 |
.stride = -mode->x_res * 4,
|
| 1166 |
.format = SPICE_SURFACE_FMT_32_xRGB, |
| 1167 |
.flags = loadvm ? QXL_SURF_FLAG_KEEP_DATA : 0,
|
| 1168 |
.mouse_mode = true,
|
| 1169 |
.mem = devmem + d->shadow_rom.draw_area_offset, |
| 1170 |
}; |
| 1171 |
|
| 1172 |
dprint(d, 1, "%s: mode %d [ %d x %d @ %d bpp devmem 0x%" PRIx64 " ]\n", |
| 1173 |
__func__, modenr, mode->x_res, mode->y_res, mode->bits, devmem); |
| 1174 |
if (!loadvm) {
|
| 1175 |
qxl_hard_reset(d, 0);
|
| 1176 |
} |
| 1177 |
|
| 1178 |
d->guest_slots[0].slot = slot;
|
| 1179 |
qxl_add_memslot(d, 0, devmem, QXL_SYNC);
|
| 1180 |
|
| 1181 |
d->guest_primary.surface = surface; |
| 1182 |
qxl_create_guest_primary(d, 0, QXL_SYNC);
|
| 1183 |
|
| 1184 |
d->mode = QXL_MODE_COMPAT; |
| 1185 |
d->cmdflags = QXL_COMMAND_FLAG_COMPAT; |
| 1186 |
#ifdef QXL_COMMAND_FLAG_COMPAT_16BPP /* new in spice 0.6.1 */ |
| 1187 |
if (mode->bits == 16) { |
| 1188 |
d->cmdflags |= QXL_COMMAND_FLAG_COMPAT_16BPP; |
| 1189 |
} |
| 1190 |
#endif
|
| 1191 |
d->shadow_rom.mode = cpu_to_le32(modenr); |
| 1192 |
d->rom->mode = cpu_to_le32(modenr); |
| 1193 |
qxl_rom_set_dirty(d); |
| 1194 |
} |
| 1195 |
|
| 1196 |
static void ioport_write(void *opaque, target_phys_addr_t addr, |
| 1197 |
uint64_t val, unsigned size)
|
| 1198 |
{
|
| 1199 |
PCIQXLDevice *d = opaque; |
| 1200 |
uint32_t io_port = addr; |
| 1201 |
qxl_async_io async = QXL_SYNC; |
| 1202 |
uint32_t orig_io_port = io_port; |
| 1203 |
|
| 1204 |
switch (io_port) {
|
| 1205 |
case QXL_IO_RESET:
|
| 1206 |
case QXL_IO_SET_MODE:
|
| 1207 |
case QXL_IO_MEMSLOT_ADD:
|
| 1208 |
case QXL_IO_MEMSLOT_DEL:
|
| 1209 |
case QXL_IO_CREATE_PRIMARY:
|
| 1210 |
case QXL_IO_UPDATE_IRQ:
|
| 1211 |
case QXL_IO_LOG:
|
| 1212 |
case QXL_IO_MEMSLOT_ADD_ASYNC:
|
| 1213 |
case QXL_IO_CREATE_PRIMARY_ASYNC:
|
| 1214 |
break;
|
| 1215 |
default:
|
| 1216 |
if (d->mode != QXL_MODE_VGA) {
|
| 1217 |
break;
|
| 1218 |
} |
| 1219 |
dprint(d, 1, "%s: unexpected port 0x%x (%s) in vga mode\n", |
| 1220 |
__func__, io_port, io_port_to_string(io_port)); |
| 1221 |
/* be nice to buggy guest drivers */
|
| 1222 |
if (io_port >= QXL_IO_UPDATE_AREA_ASYNC &&
|
| 1223 |
io_port <= QXL_IO_DESTROY_ALL_SURFACES_ASYNC) {
|
| 1224 |
qxl_send_events(d, QXL_INTERRUPT_IO_CMD); |
| 1225 |
} |
| 1226 |
return;
|
| 1227 |
} |
| 1228 |
|
| 1229 |
/* we change the io_port to avoid ifdeffery in the main switch */
|
| 1230 |
orig_io_port = io_port; |
| 1231 |
switch (io_port) {
|
| 1232 |
case QXL_IO_UPDATE_AREA_ASYNC:
|
| 1233 |
io_port = QXL_IO_UPDATE_AREA; |
| 1234 |
goto async_common;
|
| 1235 |
case QXL_IO_MEMSLOT_ADD_ASYNC:
|
| 1236 |
io_port = QXL_IO_MEMSLOT_ADD; |
| 1237 |
goto async_common;
|
| 1238 |
case QXL_IO_CREATE_PRIMARY_ASYNC:
|
| 1239 |
io_port = QXL_IO_CREATE_PRIMARY; |
| 1240 |
goto async_common;
|
| 1241 |
case QXL_IO_DESTROY_PRIMARY_ASYNC:
|
| 1242 |
io_port = QXL_IO_DESTROY_PRIMARY; |
| 1243 |
goto async_common;
|
| 1244 |
case QXL_IO_DESTROY_SURFACE_ASYNC:
|
| 1245 |
io_port = QXL_IO_DESTROY_SURFACE_WAIT; |
| 1246 |
goto async_common;
|
| 1247 |
case QXL_IO_DESTROY_ALL_SURFACES_ASYNC:
|
| 1248 |
io_port = QXL_IO_DESTROY_ALL_SURFACES; |
| 1249 |
goto async_common;
|
| 1250 |
case QXL_IO_FLUSH_SURFACES_ASYNC:
|
| 1251 |
async_common:
|
| 1252 |
async = QXL_ASYNC; |
| 1253 |
qemu_mutex_lock(&d->async_lock); |
| 1254 |
if (d->current_async != QXL_UNDEFINED_IO) {
|
| 1255 |
qxl_guest_bug(d, "%d async started before last (%d) complete",
|
| 1256 |
io_port, d->current_async); |
| 1257 |
qemu_mutex_unlock(&d->async_lock); |
| 1258 |
return;
|
| 1259 |
} |
| 1260 |
d->current_async = orig_io_port; |
| 1261 |
qemu_mutex_unlock(&d->async_lock); |
| 1262 |
dprint(d, 2, "start async %d (%"PRId64")\n", io_port, val); |
| 1263 |
break;
|
| 1264 |
default:
|
| 1265 |
break;
|
| 1266 |
} |
| 1267 |
|
| 1268 |
switch (io_port) {
|
| 1269 |
case QXL_IO_UPDATE_AREA:
|
| 1270 |
{
|
| 1271 |
QXLCookie *cookie = NULL;
|
| 1272 |
QXLRect update = d->ram->update_area; |
| 1273 |
|
| 1274 |
if (async == QXL_ASYNC) {
|
| 1275 |
cookie = qxl_cookie_new(QXL_COOKIE_TYPE_IO, |
| 1276 |
QXL_IO_UPDATE_AREA_ASYNC); |
| 1277 |
cookie->u.area = update; |
| 1278 |
} |
| 1279 |
qxl_spice_update_area(d, d->ram->update_surface, |
| 1280 |
cookie ? &cookie->u.area : &update, |
| 1281 |
NULL, 0, 0, async, cookie); |
| 1282 |
break;
|
| 1283 |
} |
| 1284 |
case QXL_IO_NOTIFY_CMD:
|
| 1285 |
qemu_spice_wakeup(&d->ssd); |
| 1286 |
break;
|
| 1287 |
case QXL_IO_NOTIFY_CURSOR:
|
| 1288 |
qemu_spice_wakeup(&d->ssd); |
| 1289 |
break;
|
| 1290 |
case QXL_IO_UPDATE_IRQ:
|
| 1291 |
qxl_update_irq(d); |
| 1292 |
break;
|
| 1293 |
case QXL_IO_NOTIFY_OOM:
|
| 1294 |
if (!SPICE_RING_IS_EMPTY(&d->ram->release_ring)) {
|
| 1295 |
break;
|
| 1296 |
} |
| 1297 |
d->oom_running = 1;
|
| 1298 |
qxl_spice_oom(d); |
| 1299 |
d->oom_running = 0;
|
| 1300 |
break;
|
| 1301 |
case QXL_IO_SET_MODE:
|
| 1302 |
dprint(d, 1, "QXL_SET_MODE %d\n", (int)val); |
| 1303 |
qxl_set_mode(d, val, 0);
|
| 1304 |
break;
|
| 1305 |
case QXL_IO_LOG:
|
| 1306 |
if (d->guestdebug) {
|
| 1307 |
fprintf(stderr, "qxl/guest-%d: %" PRId64 ": %s", d->id, |
| 1308 |
qemu_get_clock_ns(vm_clock), d->ram->log_buf); |
| 1309 |
} |
| 1310 |
break;
|
| 1311 |
case QXL_IO_RESET:
|
| 1312 |
dprint(d, 1, "QXL_IO_RESET\n"); |
| 1313 |
qxl_hard_reset(d, 0);
|
| 1314 |
break;
|
| 1315 |
case QXL_IO_MEMSLOT_ADD:
|
| 1316 |
if (val >= NUM_MEMSLOTS) {
|
| 1317 |
qxl_guest_bug(d, "QXL_IO_MEMSLOT_ADD: val out of range");
|
| 1318 |
break;
|
| 1319 |
} |
| 1320 |
if (d->guest_slots[val].active) {
|
| 1321 |
qxl_guest_bug(d, "QXL_IO_MEMSLOT_ADD: memory slot already active");
|
| 1322 |
break;
|
| 1323 |
} |
| 1324 |
d->guest_slots[val].slot = d->ram->mem_slot; |
| 1325 |
qxl_add_memslot(d, val, 0, async);
|
| 1326 |
break;
|
| 1327 |
case QXL_IO_MEMSLOT_DEL:
|
| 1328 |
if (val >= NUM_MEMSLOTS) {
|
| 1329 |
qxl_guest_bug(d, "QXL_IO_MEMSLOT_DEL: val out of range");
|
| 1330 |
break;
|
| 1331 |
} |
| 1332 |
qxl_del_memslot(d, val); |
| 1333 |
break;
|
| 1334 |
case QXL_IO_CREATE_PRIMARY:
|
| 1335 |
if (val != 0) { |
| 1336 |
qxl_guest_bug(d, "QXL_IO_CREATE_PRIMARY (async=%d): val != 0",
|
| 1337 |
async); |
| 1338 |
goto cancel_async;
|
| 1339 |
} |
| 1340 |
dprint(d, 1, "QXL_IO_CREATE_PRIMARY async=%d\n", async); |
| 1341 |
d->guest_primary.surface = d->ram->create_surface; |
| 1342 |
qxl_create_guest_primary(d, 0, async);
|
| 1343 |
break;
|
| 1344 |
case QXL_IO_DESTROY_PRIMARY:
|
| 1345 |
if (val != 0) { |
| 1346 |
qxl_guest_bug(d, "QXL_IO_DESTROY_PRIMARY (async=%d): val != 0",
|
| 1347 |
async); |
| 1348 |
goto cancel_async;
|
| 1349 |
} |
| 1350 |
dprint(d, 1, "QXL_IO_DESTROY_PRIMARY (async=%d) (%s)\n", async, |
| 1351 |
qxl_mode_to_string(d->mode)); |
| 1352 |
if (!qxl_destroy_primary(d, async)) {
|
| 1353 |
dprint(d, 1, "QXL_IO_DESTROY_PRIMARY_ASYNC in %s, ignored\n", |
| 1354 |
qxl_mode_to_string(d->mode)); |
| 1355 |
goto cancel_async;
|
| 1356 |
} |
| 1357 |
break;
|
| 1358 |
case QXL_IO_DESTROY_SURFACE_WAIT:
|
| 1359 |
if (val >= NUM_SURFACES) {
|
| 1360 |
qxl_guest_bug(d, "QXL_IO_DESTROY_SURFACE (async=%d):"
|
| 1361 |
"%d >= NUM_SURFACES", async, val);
|
| 1362 |
goto cancel_async;
|
| 1363 |
} |
| 1364 |
qxl_spice_destroy_surface_wait(d, val, async); |
| 1365 |
break;
|
| 1366 |
case QXL_IO_FLUSH_RELEASE: {
|
| 1367 |
QXLReleaseRing *ring = &d->ram->release_ring; |
| 1368 |
if (ring->prod - ring->cons + 1 == ring->num_items) { |
| 1369 |
fprintf(stderr, |
| 1370 |
"ERROR: no flush, full release ring [p%d,%dc]\n",
|
| 1371 |
ring->prod, ring->cons); |
| 1372 |
} |
| 1373 |
qxl_push_free_res(d, 1 /* flush */); |
| 1374 |
dprint(d, 1, "QXL_IO_FLUSH_RELEASE exit (%s, s#=%d, res#=%d,%p)\n", |
| 1375 |
qxl_mode_to_string(d->mode), d->guest_surfaces.count, |
| 1376 |
d->num_free_res, d->last_release); |
| 1377 |
break;
|
| 1378 |
} |
| 1379 |
case QXL_IO_FLUSH_SURFACES_ASYNC:
|
| 1380 |
dprint(d, 1, "QXL_IO_FLUSH_SURFACES_ASYNC" |
| 1381 |
" (%"PRId64") (%s, s#=%d, res#=%d)\n", |
| 1382 |
val, qxl_mode_to_string(d->mode), d->guest_surfaces.count, |
| 1383 |
d->num_free_res); |
| 1384 |
qxl_spice_flush_surfaces_async(d); |
| 1385 |
break;
|
| 1386 |
case QXL_IO_DESTROY_ALL_SURFACES:
|
| 1387 |
d->mode = QXL_MODE_UNDEFINED; |
| 1388 |
qxl_spice_destroy_surfaces(d, async); |
| 1389 |
break;
|
| 1390 |
default:
|
| 1391 |
fprintf(stderr, "%s: ioport=0x%x, abort()\n", __FUNCTION__, io_port);
|
| 1392 |
abort(); |
| 1393 |
} |
| 1394 |
return;
|
| 1395 |
cancel_async:
|
| 1396 |
if (async) {
|
| 1397 |
qxl_send_events(d, QXL_INTERRUPT_IO_CMD); |
| 1398 |
qemu_mutex_lock(&d->async_lock); |
| 1399 |
d->current_async = QXL_UNDEFINED_IO; |
| 1400 |
qemu_mutex_unlock(&d->async_lock); |
| 1401 |
} |
| 1402 |
} |
| 1403 |
|
| 1404 |
static uint64_t ioport_read(void *opaque, target_phys_addr_t addr, |
| 1405 |
unsigned size)
|
| 1406 |
{
|
| 1407 |
PCIQXLDevice *d = opaque; |
| 1408 |
|
| 1409 |
dprint(d, 1, "%s: unexpected\n", __FUNCTION__); |
| 1410 |
return 0xff; |
| 1411 |
} |
| 1412 |
|
| 1413 |
static const MemoryRegionOps qxl_io_ops = { |
| 1414 |
.read = ioport_read, |
| 1415 |
.write = ioport_write, |
| 1416 |
.valid = {
|
| 1417 |
.min_access_size = 1,
|
| 1418 |
.max_access_size = 1,
|
| 1419 |
}, |
| 1420 |
}; |
| 1421 |
|
| 1422 |
static void pipe_read(void *opaque) |
| 1423 |
{
|
| 1424 |
PCIQXLDevice *d = opaque; |
| 1425 |
char dummy;
|
| 1426 |
int len;
|
| 1427 |
|
| 1428 |
do {
|
| 1429 |
len = read(d->pipe[0], &dummy, sizeof(dummy)); |
| 1430 |
} while (len == sizeof(dummy)); |
| 1431 |
qxl_update_irq(d); |
| 1432 |
} |
| 1433 |
|
| 1434 |
static void qxl_send_events(PCIQXLDevice *d, uint32_t events) |
| 1435 |
{
|
| 1436 |
uint32_t old_pending; |
| 1437 |
uint32_t le_events = cpu_to_le32(events); |
| 1438 |
|
| 1439 |
assert(d->ssd.running); |
| 1440 |
old_pending = __sync_fetch_and_or(&d->ram->int_pending, le_events); |
| 1441 |
if ((old_pending & le_events) == le_events) {
|
| 1442 |
return;
|
| 1443 |
} |
| 1444 |
if (qemu_thread_is_self(&d->main)) {
|
| 1445 |
qxl_update_irq(d); |
| 1446 |
} else {
|
| 1447 |
if (write(d->pipe[1], d, 1) != 1) { |
| 1448 |
dprint(d, 1, "%s: write to pipe failed\n", __FUNCTION__); |
| 1449 |
} |
| 1450 |
} |
| 1451 |
} |
| 1452 |
|
| 1453 |
static void init_pipe_signaling(PCIQXLDevice *d) |
| 1454 |
{
|
| 1455 |
if (pipe(d->pipe) < 0) { |
| 1456 |
dprint(d, 1, "%s: pipe creation failed\n", __FUNCTION__); |
| 1457 |
return;
|
| 1458 |
} |
| 1459 |
fcntl(d->pipe[0], F_SETFL, O_NONBLOCK);
|
| 1460 |
fcntl(d->pipe[1], F_SETFL, O_NONBLOCK);
|
| 1461 |
fcntl(d->pipe[0], F_SETOWN, getpid());
|
| 1462 |
|
| 1463 |
qemu_thread_get_self(&d->main); |
| 1464 |
qemu_set_fd_handler(d->pipe[0], pipe_read, NULL, d); |
| 1465 |
} |
| 1466 |
|
| 1467 |
/* graphics console */
|
| 1468 |
|
| 1469 |
static void qxl_hw_update(void *opaque) |
| 1470 |
{
|
| 1471 |
PCIQXLDevice *qxl = opaque; |
| 1472 |
VGACommonState *vga = &qxl->vga; |
| 1473 |
|
| 1474 |
switch (qxl->mode) {
|
| 1475 |
case QXL_MODE_VGA:
|
| 1476 |
vga->update(vga); |
| 1477 |
break;
|
| 1478 |
case QXL_MODE_COMPAT:
|
| 1479 |
case QXL_MODE_NATIVE:
|
| 1480 |
qxl_render_update(qxl); |
| 1481 |
break;
|
| 1482 |
default:
|
| 1483 |
break;
|
| 1484 |
} |
| 1485 |
} |
| 1486 |
|
| 1487 |
static void qxl_hw_invalidate(void *opaque) |
| 1488 |
{
|
| 1489 |
PCIQXLDevice *qxl = opaque; |
| 1490 |
VGACommonState *vga = &qxl->vga; |
| 1491 |
|
| 1492 |
vga->invalidate(vga); |
| 1493 |
} |
| 1494 |
|
| 1495 |
static void qxl_hw_screen_dump(void *opaque, const char *filename, bool cswitch) |
| 1496 |
{
|
| 1497 |
PCIQXLDevice *qxl = opaque; |
| 1498 |
VGACommonState *vga = &qxl->vga; |
| 1499 |
|
| 1500 |
switch (qxl->mode) {
|
| 1501 |
case QXL_MODE_COMPAT:
|
| 1502 |
case QXL_MODE_NATIVE:
|
| 1503 |
qxl_render_update(qxl); |
| 1504 |
ppm_save(filename, qxl->ssd.ds->surface); |
| 1505 |
break;
|
| 1506 |
case QXL_MODE_VGA:
|
| 1507 |
vga->screen_dump(vga, filename, cswitch); |
| 1508 |
break;
|
| 1509 |
default:
|
| 1510 |
break;
|
| 1511 |
} |
| 1512 |
} |
| 1513 |
|
| 1514 |
static void qxl_hw_text_update(void *opaque, console_ch_t *chardata) |
| 1515 |
{
|
| 1516 |
PCIQXLDevice *qxl = opaque; |
| 1517 |
VGACommonState *vga = &qxl->vga; |
| 1518 |
|
| 1519 |
if (qxl->mode == QXL_MODE_VGA) {
|
| 1520 |
vga->text_update(vga, chardata); |
| 1521 |
return;
|
| 1522 |
} |
| 1523 |
} |
| 1524 |
|
| 1525 |
static void qxl_dirty_surfaces(PCIQXLDevice *qxl) |
| 1526 |
{
|
| 1527 |
intptr_t vram_start; |
| 1528 |
int i;
|
| 1529 |
|
| 1530 |
if (qxl->mode != QXL_MODE_NATIVE && qxl->mode != QXL_MODE_COMPAT) {
|
| 1531 |
return;
|
| 1532 |
} |
| 1533 |
|
| 1534 |
/* dirty the primary surface */
|
| 1535 |
qxl_set_dirty(&qxl->vga.vram, qxl->shadow_rom.draw_area_offset, |
| 1536 |
qxl->shadow_rom.surface0_area_size); |
| 1537 |
|
| 1538 |
vram_start = (intptr_t)memory_region_get_ram_ptr(&qxl->vram_bar); |
| 1539 |
|
| 1540 |
/* dirty the off-screen surfaces */
|
| 1541 |
for (i = 0; i < NUM_SURFACES; i++) { |
| 1542 |
QXLSurfaceCmd *cmd; |
| 1543 |
intptr_t surface_offset; |
| 1544 |
int surface_size;
|
| 1545 |
|
| 1546 |
if (qxl->guest_surfaces.cmds[i] == 0) { |
| 1547 |
continue;
|
| 1548 |
} |
| 1549 |
|
| 1550 |
cmd = qxl_phys2virt(qxl, qxl->guest_surfaces.cmds[i], |
| 1551 |
MEMSLOT_GROUP_GUEST); |
| 1552 |
assert(cmd->type == QXL_SURFACE_CMD_CREATE); |
| 1553 |
surface_offset = (intptr_t)qxl_phys2virt(qxl, |
| 1554 |
cmd->u.surface_create.data, |
| 1555 |
MEMSLOT_GROUP_GUEST); |
| 1556 |
surface_offset -= vram_start; |
| 1557 |
surface_size = cmd->u.surface_create.height * |
| 1558 |
abs(cmd->u.surface_create.stride); |
| 1559 |
dprint(qxl, 3, "%s: dirty surface %d, offset %d, size %d\n", __func__, |
| 1560 |
i, (int)surface_offset, surface_size);
|
| 1561 |
qxl_set_dirty(&qxl->vram_bar, surface_offset, surface_size); |
| 1562 |
} |
| 1563 |
} |
| 1564 |
|
| 1565 |
static void qxl_vm_change_state_handler(void *opaque, int running, |
| 1566 |
RunState state) |
| 1567 |
{
|
| 1568 |
PCIQXLDevice *qxl = opaque; |
| 1569 |
qemu_spice_vm_change_state_handler(&qxl->ssd, running, state); |
| 1570 |
|
| 1571 |
if (running) {
|
| 1572 |
/*
|
| 1573 |
* if qxl_send_events was called from spice server context before
|
| 1574 |
* migration ended, qxl_update_irq for these events might not have been
|
| 1575 |
* called
|
| 1576 |
*/
|
| 1577 |
qxl_update_irq(qxl); |
| 1578 |
} else {
|
| 1579 |
/* make sure surfaces are saved before migration */
|
| 1580 |
qxl_dirty_surfaces(qxl); |
| 1581 |
} |
| 1582 |
} |
| 1583 |
|
| 1584 |
/* display change listener */
|
| 1585 |
|
| 1586 |
static void display_update(struct DisplayState *ds, int x, int y, int w, int h) |
| 1587 |
{
|
| 1588 |
if (qxl0->mode == QXL_MODE_VGA) {
|
| 1589 |
qemu_spice_display_update(&qxl0->ssd, x, y, w, h); |
| 1590 |
} |
| 1591 |
} |
| 1592 |
|
| 1593 |
static void display_resize(struct DisplayState *ds) |
| 1594 |
{
|
| 1595 |
if (qxl0->mode == QXL_MODE_VGA) {
|
| 1596 |
qemu_spice_display_resize(&qxl0->ssd); |
| 1597 |
} |
| 1598 |
} |
| 1599 |
|
| 1600 |
static void display_refresh(struct DisplayState *ds) |
| 1601 |
{
|
| 1602 |
if (qxl0->mode == QXL_MODE_VGA) {
|
| 1603 |
qemu_spice_display_refresh(&qxl0->ssd); |
| 1604 |
} else {
|
| 1605 |
qemu_mutex_lock(&qxl0->ssd.lock); |
| 1606 |
qemu_spice_cursor_refresh_unlocked(&qxl0->ssd); |
| 1607 |
qemu_mutex_unlock(&qxl0->ssd.lock); |
| 1608 |
} |
| 1609 |
} |
| 1610 |
|
| 1611 |
static DisplayChangeListener display_listener = {
|
| 1612 |
.dpy_update = display_update, |
| 1613 |
.dpy_resize = display_resize, |
| 1614 |
.dpy_refresh = display_refresh, |
| 1615 |
}; |
| 1616 |
|
| 1617 |
static void qxl_init_ramsize(PCIQXLDevice *qxl, uint32_t ram_min_mb) |
| 1618 |
{
|
| 1619 |
/* vga ram (bar 0) */
|
| 1620 |
if (qxl->ram_size_mb != -1) { |
| 1621 |
qxl->vga.vram_size = qxl->ram_size_mb * 1024 * 1024; |
| 1622 |
} |
| 1623 |
if (qxl->vga.vram_size < ram_min_mb * 1024 * 1024) { |
| 1624 |
qxl->vga.vram_size = ram_min_mb * 1024 * 1024; |
| 1625 |
} |
| 1626 |
|
| 1627 |
/* vram32 (surfaces, 32bit, bar 1) */
|
| 1628 |
if (qxl->vram32_size_mb != -1) { |
| 1629 |
qxl->vram32_size = qxl->vram32_size_mb * 1024 * 1024; |
| 1630 |
} |
| 1631 |
if (qxl->vram32_size < 4096) { |
| 1632 |
qxl->vram32_size = 4096;
|
| 1633 |
} |
| 1634 |
|
| 1635 |
/* vram (surfaces, 64bit, bar 4+5) */
|
| 1636 |
if (qxl->vram_size_mb != -1) { |
| 1637 |
qxl->vram_size = qxl->vram_size_mb * 1024 * 1024; |
| 1638 |
} |
| 1639 |
if (qxl->vram_size < qxl->vram32_size) {
|
| 1640 |
qxl->vram_size = qxl->vram32_size; |
| 1641 |
} |
| 1642 |
|
| 1643 |
if (qxl->revision == 1) { |
| 1644 |
qxl->vram32_size = 4096;
|
| 1645 |
qxl->vram_size = 4096;
|
| 1646 |
} |
| 1647 |
qxl->vga.vram_size = msb_mask(qxl->vga.vram_size * 2 - 1); |
| 1648 |
qxl->vram32_size = msb_mask(qxl->vram32_size * 2 - 1); |
| 1649 |
qxl->vram_size = msb_mask(qxl->vram_size * 2 - 1); |
| 1650 |
} |
| 1651 |
|
| 1652 |
static int qxl_init_common(PCIQXLDevice *qxl) |
| 1653 |
{
|
| 1654 |
uint8_t* config = qxl->pci.config; |
| 1655 |
uint32_t pci_device_rev; |
| 1656 |
uint32_t io_size; |
| 1657 |
|
| 1658 |
qxl->mode = QXL_MODE_UNDEFINED; |
| 1659 |
qxl->generation = 1;
|
| 1660 |
qxl->num_memslots = NUM_MEMSLOTS; |
| 1661 |
qxl->num_surfaces = NUM_SURFACES; |
| 1662 |
qemu_mutex_init(&qxl->track_lock); |
| 1663 |
qemu_mutex_init(&qxl->async_lock); |
| 1664 |
qxl->current_async = QXL_UNDEFINED_IO; |
| 1665 |
|
| 1666 |
switch (qxl->revision) {
|
| 1667 |
case 1: /* spice 0.4 -- qxl-1 */ |
| 1668 |
pci_device_rev = QXL_REVISION_STABLE_V04; |
| 1669 |
break;
|
| 1670 |
case 2: /* spice 0.6 -- qxl-2 */ |
| 1671 |
pci_device_rev = QXL_REVISION_STABLE_V06; |
| 1672 |
break;
|
| 1673 |
case 3: /* qxl-3 */ |
| 1674 |
default:
|
| 1675 |
pci_device_rev = QXL_DEFAULT_REVISION; |
| 1676 |
break;
|
| 1677 |
} |
| 1678 |
|
| 1679 |
pci_set_byte(&config[PCI_REVISION_ID], pci_device_rev); |
| 1680 |
pci_set_byte(&config[PCI_INTERRUPT_PIN], 1);
|
| 1681 |
|
| 1682 |
qxl->rom_size = qxl_rom_size(); |
| 1683 |
memory_region_init_ram(&qxl->rom_bar, "qxl.vrom", qxl->rom_size);
|
| 1684 |
vmstate_register_ram(&qxl->rom_bar, &qxl->pci.qdev); |
| 1685 |
init_qxl_rom(qxl); |
| 1686 |
init_qxl_ram(qxl); |
| 1687 |
|
| 1688 |
memory_region_init_ram(&qxl->vram_bar, "qxl.vram", qxl->vram_size);
|
| 1689 |
vmstate_register_ram(&qxl->vram_bar, &qxl->pci.qdev); |
| 1690 |
memory_region_init_alias(&qxl->vram32_bar, "qxl.vram32", &qxl->vram_bar,
|
| 1691 |
0, qxl->vram32_size);
|
| 1692 |
|
| 1693 |
io_size = msb_mask(QXL_IO_RANGE_SIZE * 2 - 1); |
| 1694 |
if (qxl->revision == 1) { |
| 1695 |
io_size = 8;
|
| 1696 |
} |
| 1697 |
|
| 1698 |
memory_region_init_io(&qxl->io_bar, &qxl_io_ops, qxl, |
| 1699 |
"qxl-ioports", io_size);
|
| 1700 |
if (qxl->id == 0) { |
| 1701 |
vga_dirty_log_start(&qxl->vga); |
| 1702 |
} |
| 1703 |
|
| 1704 |
|
| 1705 |
pci_register_bar(&qxl->pci, QXL_IO_RANGE_INDEX, |
| 1706 |
PCI_BASE_ADDRESS_SPACE_IO, &qxl->io_bar); |
| 1707 |
|
| 1708 |
pci_register_bar(&qxl->pci, QXL_ROM_RANGE_INDEX, |
| 1709 |
PCI_BASE_ADDRESS_SPACE_MEMORY, &qxl->rom_bar); |
| 1710 |
|
| 1711 |
pci_register_bar(&qxl->pci, QXL_RAM_RANGE_INDEX, |
| 1712 |
PCI_BASE_ADDRESS_SPACE_MEMORY, &qxl->vga.vram); |
| 1713 |
|
| 1714 |
pci_register_bar(&qxl->pci, QXL_VRAM_RANGE_INDEX, |
| 1715 |
PCI_BASE_ADDRESS_SPACE_MEMORY, &qxl->vram32_bar); |
| 1716 |
|
| 1717 |
if (qxl->vram32_size < qxl->vram_size) {
|
| 1718 |
/*
|
| 1719 |
* Make the 64bit vram bar show up only in case it is
|
| 1720 |
* configured to be larger than the 32bit vram bar.
|
| 1721 |
*/
|
| 1722 |
pci_register_bar(&qxl->pci, QXL_VRAM64_RANGE_INDEX, |
| 1723 |
PCI_BASE_ADDRESS_SPACE_MEMORY | |
| 1724 |
PCI_BASE_ADDRESS_MEM_TYPE_64 | |
| 1725 |
PCI_BASE_ADDRESS_MEM_PREFETCH, |
| 1726 |
&qxl->vram_bar); |
| 1727 |
} |
| 1728 |
|
| 1729 |
/* print pci bar details */
|
| 1730 |
dprint(qxl, 1, "ram/%s: %d MB [region 0]\n", |
| 1731 |
qxl->id == 0 ? "pri" : "sec", |
| 1732 |
qxl->vga.vram_size / (1024*1024)); |
| 1733 |
dprint(qxl, 1, "vram/32: %d MB [region 1]\n", |
| 1734 |
qxl->vram32_size / (1024*1024)); |
| 1735 |
dprint(qxl, 1, "vram/64: %d MB %s\n", |
| 1736 |
qxl->vram_size / (1024*1024), |
| 1737 |
qxl->vram32_size < qxl->vram_size ? "[region 4]" : "[unmapped]"); |
| 1738 |
|
| 1739 |
qxl->ssd.qxl.base.sif = &qxl_interface.base; |
| 1740 |
qxl->ssd.qxl.id = qxl->id; |
| 1741 |
qemu_spice_add_interface(&qxl->ssd.qxl.base); |
| 1742 |
qemu_add_vm_change_state_handler(qxl_vm_change_state_handler, qxl); |
| 1743 |
|
| 1744 |
init_pipe_signaling(qxl); |
| 1745 |
qxl_reset_state(qxl); |
| 1746 |
|
| 1747 |
qxl->update_area_bh = qemu_bh_new(qxl_render_update_area_bh, qxl); |
| 1748 |
|
| 1749 |
return 0; |
| 1750 |
} |
| 1751 |
|
| 1752 |
static int qxl_init_primary(PCIDevice *dev) |
| 1753 |
{
|
| 1754 |
PCIQXLDevice *qxl = DO_UPCAST(PCIQXLDevice, pci, dev); |
| 1755 |
VGACommonState *vga = &qxl->vga; |
| 1756 |
PortioList *qxl_vga_port_list = g_new(PortioList, 1);
|
| 1757 |
|
| 1758 |
qxl->id = 0;
|
| 1759 |
qxl_init_ramsize(qxl, 32);
|
| 1760 |
vga_common_init(vga, qxl->vga.vram_size); |
| 1761 |
vga_init(vga, pci_address_space(dev), pci_address_space_io(dev), false);
|
| 1762 |
portio_list_init(qxl_vga_port_list, qxl_vga_portio_list, vga, "vga");
|
| 1763 |
portio_list_add(qxl_vga_port_list, pci_address_space_io(dev), 0x3b0);
|
| 1764 |
|
| 1765 |
vga->ds = graphic_console_init(qxl_hw_update, qxl_hw_invalidate, |
| 1766 |
qxl_hw_screen_dump, qxl_hw_text_update, qxl); |
| 1767 |
qemu_spice_display_init_common(&qxl->ssd, vga->ds); |
| 1768 |
|
| 1769 |
qxl0 = qxl; |
| 1770 |
register_displaychangelistener(vga->ds, &display_listener); |
| 1771 |
|
| 1772 |
return qxl_init_common(qxl);
|
| 1773 |
} |
| 1774 |
|
| 1775 |
static int qxl_init_secondary(PCIDevice *dev) |
| 1776 |
{
|
| 1777 |
static int device_id = 1; |
| 1778 |
PCIQXLDevice *qxl = DO_UPCAST(PCIQXLDevice, pci, dev); |
| 1779 |
|
| 1780 |
qxl->id = device_id++; |
| 1781 |
qxl_init_ramsize(qxl, 16);
|
| 1782 |
memory_region_init_ram(&qxl->vga.vram, "qxl.vgavram", qxl->vga.vram_size);
|
| 1783 |
vmstate_register_ram(&qxl->vga.vram, &qxl->pci.qdev); |
| 1784 |
qxl->vga.vram_ptr = memory_region_get_ram_ptr(&qxl->vga.vram); |
| 1785 |
|
| 1786 |
return qxl_init_common(qxl);
|
| 1787 |
} |
| 1788 |
|
| 1789 |
static void qxl_pre_save(void *opaque) |
| 1790 |
{
|
| 1791 |
PCIQXLDevice* d = opaque; |
| 1792 |
uint8_t *ram_start = d->vga.vram_ptr; |
| 1793 |
|
| 1794 |
dprint(d, 1, "%s:\n", __FUNCTION__); |
| 1795 |
if (d->last_release == NULL) { |
| 1796 |
d->last_release_offset = 0;
|
| 1797 |
} else {
|
| 1798 |
d->last_release_offset = (uint8_t *)d->last_release - ram_start; |
| 1799 |
} |
| 1800 |
assert(d->last_release_offset < d->vga.vram_size); |
| 1801 |
} |
| 1802 |
|
| 1803 |
static int qxl_pre_load(void *opaque) |
| 1804 |
{
|
| 1805 |
PCIQXLDevice* d = opaque; |
| 1806 |
|
| 1807 |
dprint(d, 1, "%s: start\n", __FUNCTION__); |
| 1808 |
qxl_hard_reset(d, 1);
|
| 1809 |
qxl_exit_vga_mode(d); |
| 1810 |
dprint(d, 1, "%s: done\n", __FUNCTION__); |
| 1811 |
return 0; |
| 1812 |
} |
| 1813 |
|
| 1814 |
static void qxl_create_memslots(PCIQXLDevice *d) |
| 1815 |
{
|
| 1816 |
int i;
|
| 1817 |
|
| 1818 |
for (i = 0; i < NUM_MEMSLOTS; i++) { |
| 1819 |
if (!d->guest_slots[i].active) {
|
| 1820 |
continue;
|
| 1821 |
} |
| 1822 |
dprint(d, 1, "%s: restoring guest slot %d\n", __func__, i); |
| 1823 |
qxl_add_memslot(d, i, 0, QXL_SYNC);
|
| 1824 |
} |
| 1825 |
} |
| 1826 |
|
| 1827 |
static int qxl_post_load(void *opaque, int version) |
| 1828 |
{
|
| 1829 |
PCIQXLDevice* d = opaque; |
| 1830 |
uint8_t *ram_start = d->vga.vram_ptr; |
| 1831 |
QXLCommandExt *cmds; |
| 1832 |
int in, out, newmode;
|
| 1833 |
|
| 1834 |
dprint(d, 1, "%s: start\n", __FUNCTION__); |
| 1835 |
|
| 1836 |
assert(d->last_release_offset < d->vga.vram_size); |
| 1837 |
if (d->last_release_offset == 0) { |
| 1838 |
d->last_release = NULL;
|
| 1839 |
} else {
|
| 1840 |
d->last_release = (QXLReleaseInfo *)(ram_start + d->last_release_offset); |
| 1841 |
} |
| 1842 |
|
| 1843 |
d->modes = (QXLModes*)((uint8_t*)d->rom + d->rom->modes_offset); |
| 1844 |
|
| 1845 |
dprint(d, 1, "%s: restore mode (%s)\n", __FUNCTION__, |
| 1846 |
qxl_mode_to_string(d->mode)); |
| 1847 |
newmode = d->mode; |
| 1848 |
d->mode = QXL_MODE_UNDEFINED; |
| 1849 |
|
| 1850 |
switch (newmode) {
|
| 1851 |
case QXL_MODE_UNDEFINED:
|
| 1852 |
break;
|
| 1853 |
case QXL_MODE_VGA:
|
| 1854 |
qxl_create_memslots(d); |
| 1855 |
qxl_enter_vga_mode(d); |
| 1856 |
break;
|
| 1857 |
case QXL_MODE_NATIVE:
|
| 1858 |
qxl_create_memslots(d); |
| 1859 |
qxl_create_guest_primary(d, 1, QXL_SYNC);
|
| 1860 |
|
| 1861 |
/* replay surface-create and cursor-set commands */
|
| 1862 |
cmds = g_malloc0(sizeof(QXLCommandExt) * (NUM_SURFACES + 1)); |
| 1863 |
for (in = 0, out = 0; in < NUM_SURFACES; in++) { |
| 1864 |
if (d->guest_surfaces.cmds[in] == 0) { |
| 1865 |
continue;
|
| 1866 |
} |
| 1867 |
cmds[out].cmd.data = d->guest_surfaces.cmds[in]; |
| 1868 |
cmds[out].cmd.type = QXL_CMD_SURFACE; |
| 1869 |
cmds[out].group_id = MEMSLOT_GROUP_GUEST; |
| 1870 |
out++; |
| 1871 |
} |
| 1872 |
if (d->guest_cursor) {
|
| 1873 |
cmds[out].cmd.data = d->guest_cursor; |
| 1874 |
cmds[out].cmd.type = QXL_CMD_CURSOR; |
| 1875 |
cmds[out].group_id = MEMSLOT_GROUP_GUEST; |
| 1876 |
out++; |
| 1877 |
} |
| 1878 |
qxl_spice_loadvm_commands(d, cmds, out); |
| 1879 |
g_free(cmds); |
| 1880 |
|
| 1881 |
break;
|
| 1882 |
case QXL_MODE_COMPAT:
|
| 1883 |
/* note: no need to call qxl_create_memslots, qxl_set_mode
|
| 1884 |
* creates the mem slot. */
|
| 1885 |
qxl_set_mode(d, d->shadow_rom.mode, 1);
|
| 1886 |
break;
|
| 1887 |
} |
| 1888 |
dprint(d, 1, "%s: done\n", __FUNCTION__); |
| 1889 |
|
| 1890 |
return 0; |
| 1891 |
} |
| 1892 |
|
| 1893 |
#define QXL_SAVE_VERSION 21 |
| 1894 |
|
| 1895 |
static VMStateDescription qxl_memslot = {
|
| 1896 |
.name = "qxl-memslot",
|
| 1897 |
.version_id = QXL_SAVE_VERSION, |
| 1898 |
.minimum_version_id = QXL_SAVE_VERSION, |
| 1899 |
.fields = (VMStateField[]) {
|
| 1900 |
VMSTATE_UINT64(slot.mem_start, struct guest_slots),
|
| 1901 |
VMSTATE_UINT64(slot.mem_end, struct guest_slots),
|
| 1902 |
VMSTATE_UINT32(active, struct guest_slots),
|
| 1903 |
VMSTATE_END_OF_LIST() |
| 1904 |
} |
| 1905 |
}; |
| 1906 |
|
| 1907 |
static VMStateDescription qxl_surface = {
|
| 1908 |
.name = "qxl-surface",
|
| 1909 |
.version_id = QXL_SAVE_VERSION, |
| 1910 |
.minimum_version_id = QXL_SAVE_VERSION, |
| 1911 |
.fields = (VMStateField[]) {
|
| 1912 |
VMSTATE_UINT32(width, QXLSurfaceCreate), |
| 1913 |
VMSTATE_UINT32(height, QXLSurfaceCreate), |
| 1914 |
VMSTATE_INT32(stride, QXLSurfaceCreate), |
| 1915 |
VMSTATE_UINT32(format, QXLSurfaceCreate), |
| 1916 |
VMSTATE_UINT32(position, QXLSurfaceCreate), |
| 1917 |
VMSTATE_UINT32(mouse_mode, QXLSurfaceCreate), |
| 1918 |
VMSTATE_UINT32(flags, QXLSurfaceCreate), |
| 1919 |
VMSTATE_UINT32(type, QXLSurfaceCreate), |
| 1920 |
VMSTATE_UINT64(mem, QXLSurfaceCreate), |
| 1921 |
VMSTATE_END_OF_LIST() |
| 1922 |
} |
| 1923 |
}; |
| 1924 |
|
| 1925 |
static VMStateDescription qxl_vmstate = {
|
| 1926 |
.name = "qxl",
|
| 1927 |
.version_id = QXL_SAVE_VERSION, |
| 1928 |
.minimum_version_id = QXL_SAVE_VERSION, |
| 1929 |
.pre_save = qxl_pre_save, |
| 1930 |
.pre_load = qxl_pre_load, |
| 1931 |
.post_load = qxl_post_load, |
| 1932 |
.fields = (VMStateField []) {
|
| 1933 |
VMSTATE_PCI_DEVICE(pci, PCIQXLDevice), |
| 1934 |
VMSTATE_STRUCT(vga, PCIQXLDevice, 0, vmstate_vga_common, VGACommonState),
|
| 1935 |
VMSTATE_UINT32(shadow_rom.mode, PCIQXLDevice), |
| 1936 |
VMSTATE_UINT32(num_free_res, PCIQXLDevice), |
| 1937 |
VMSTATE_UINT32(last_release_offset, PCIQXLDevice), |
| 1938 |
VMSTATE_UINT32(mode, PCIQXLDevice), |
| 1939 |
VMSTATE_UINT32(ssd.unique, PCIQXLDevice), |
| 1940 |
VMSTATE_INT32_EQUAL(num_memslots, PCIQXLDevice), |
| 1941 |
VMSTATE_STRUCT_ARRAY(guest_slots, PCIQXLDevice, NUM_MEMSLOTS, 0,
|
| 1942 |
qxl_memslot, struct guest_slots),
|
| 1943 |
VMSTATE_STRUCT(guest_primary.surface, PCIQXLDevice, 0,
|
| 1944 |
qxl_surface, QXLSurfaceCreate), |
| 1945 |
VMSTATE_INT32_EQUAL(num_surfaces, PCIQXLDevice), |
| 1946 |
VMSTATE_ARRAY(guest_surfaces.cmds, PCIQXLDevice, NUM_SURFACES, 0,
|
| 1947 |
vmstate_info_uint64, uint64_t), |
| 1948 |
VMSTATE_UINT64(guest_cursor, PCIQXLDevice), |
| 1949 |
VMSTATE_END_OF_LIST() |
| 1950 |
}, |
| 1951 |
}; |
| 1952 |
|
| 1953 |
static Property qxl_properties[] = {
|
| 1954 |
DEFINE_PROP_UINT32("ram_size", PCIQXLDevice, vga.vram_size,
|
| 1955 |
64 * 1024 * 1024), |
| 1956 |
DEFINE_PROP_UINT32("vram_size", PCIQXLDevice, vram32_size,
|
| 1957 |
64 * 1024 * 1024), |
| 1958 |
DEFINE_PROP_UINT32("revision", PCIQXLDevice, revision,
|
| 1959 |
QXL_DEFAULT_REVISION), |
| 1960 |
DEFINE_PROP_UINT32("debug", PCIQXLDevice, debug, 0), |
| 1961 |
DEFINE_PROP_UINT32("guestdebug", PCIQXLDevice, guestdebug, 0), |
| 1962 |
DEFINE_PROP_UINT32("cmdlog", PCIQXLDevice, cmdlog, 0), |
| 1963 |
DEFINE_PROP_UINT32("ram_size_mb", PCIQXLDevice, ram_size_mb, -1), |
| 1964 |
DEFINE_PROP_UINT32("vram_size_mb", PCIQXLDevice, vram32_size_mb, 0), |
| 1965 |
DEFINE_PROP_UINT32("vram64_size_mb", PCIQXLDevice, vram_size_mb, 0), |
| 1966 |
DEFINE_PROP_END_OF_LIST(), |
| 1967 |
}; |
| 1968 |
|
| 1969 |
static void qxl_primary_class_init(ObjectClass *klass, void *data) |
| 1970 |
{
|
| 1971 |
DeviceClass *dc = DEVICE_CLASS(klass); |
| 1972 |
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
| 1973 |
|
| 1974 |
k->no_hotplug = 1;
|
| 1975 |
k->init = qxl_init_primary; |
| 1976 |
k->romfile = "vgabios-qxl.bin";
|
| 1977 |
k->vendor_id = REDHAT_PCI_VENDOR_ID; |
| 1978 |
k->device_id = QXL_DEVICE_ID_STABLE; |
| 1979 |
k->class_id = PCI_CLASS_DISPLAY_VGA; |
| 1980 |
dc->desc = "Spice QXL GPU (primary, vga compatible)";
|
| 1981 |
dc->reset = qxl_reset_handler; |
| 1982 |
dc->vmsd = &qxl_vmstate; |
| 1983 |
dc->props = qxl_properties; |
| 1984 |
} |
| 1985 |
|
| 1986 |
static TypeInfo qxl_primary_info = {
|
| 1987 |
.name = "qxl-vga",
|
| 1988 |
.parent = TYPE_PCI_DEVICE, |
| 1989 |
.instance_size = sizeof(PCIQXLDevice),
|
| 1990 |
.class_init = qxl_primary_class_init, |
| 1991 |
}; |
| 1992 |
|
| 1993 |
static void qxl_secondary_class_init(ObjectClass *klass, void *data) |
| 1994 |
{
|
| 1995 |
DeviceClass *dc = DEVICE_CLASS(klass); |
| 1996 |
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
| 1997 |
|
| 1998 |
k->init = qxl_init_secondary; |
| 1999 |
k->vendor_id = REDHAT_PCI_VENDOR_ID; |
| 2000 |
k->device_id = QXL_DEVICE_ID_STABLE; |
| 2001 |
k->class_id = PCI_CLASS_DISPLAY_OTHER; |
| 2002 |
dc->desc = "Spice QXL GPU (secondary)";
|
| 2003 |
dc->reset = qxl_reset_handler; |
| 2004 |
dc->vmsd = &qxl_vmstate; |
| 2005 |
dc->props = qxl_properties; |
| 2006 |
} |
| 2007 |
|
| 2008 |
static TypeInfo qxl_secondary_info = {
|
| 2009 |
.name = "qxl",
|
| 2010 |
.parent = TYPE_PCI_DEVICE, |
| 2011 |
.instance_size = sizeof(PCIQXLDevice),
|
| 2012 |
.class_init = qxl_secondary_class_init, |
| 2013 |
}; |
| 2014 |
|
| 2015 |
static void qxl_register_types(void) |
| 2016 |
{
|
| 2017 |
type_register_static(&qxl_primary_info); |
| 2018 |
type_register_static(&qxl_secondary_info); |
| 2019 |
} |
| 2020 |
|
| 2021 |
type_init(qxl_register_types) |