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/*
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 * QEMU PC System Emulator
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 *
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 * Copyright (c) 2003-2004 Fabrice Bellard
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 *
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 * Permission is hereby granted, free of charge, to any person obtaining a copy
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 * of this software and associated documentation files (the "Software"), to deal
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 * in the Software without restriction, including without limitation the rights
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 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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 * copies of the Software, and to permit persons to whom the Software is
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 * furnished to do so, subject to the following conditions:
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 *
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 * The above copyright notice and this permission notice shall be included in
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 * all copies or substantial portions of the Software.
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 *
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 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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 * THE SOFTWARE.
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 */
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#include "hw.h"
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#include "pc.h"
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#include "fdc.h"
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#include "pci.h"
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#include "block.h"
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#include "sysemu.h"
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#include "audio/audio.h"
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#include "net.h"
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#include "smbus.h"
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#include "boards.h"
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#include "console.h"
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#include "fw_cfg.h"
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#include "virtio-blk.h"
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#include "virtio-balloon.h"
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#include "virtio-console.h"
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#include "hpet_emul.h"
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/* output Bochs bios info messages */
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//#define DEBUG_BIOS
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#define BIOS_FILENAME "bios.bin"
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#define VGABIOS_FILENAME "vgabios.bin"
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#define VGABIOS_CIRRUS_FILENAME "vgabios-cirrus.bin"
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#define PC_MAX_BIOS_SIZE (4 * 1024 * 1024)
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/* Leave a chunk of memory at the top of RAM for the BIOS ACPI tables.  */
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#define ACPI_DATA_SIZE       0x10000
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#define BIOS_CFG_IOPORT 0x510
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#define MAX_IDE_BUS 2
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static fdctrl_t *floppy_controller;
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static RTCState *rtc_state;
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static PITState *pit;
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static IOAPICState *ioapic;
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static PCIDevice *i440fx_state;
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static void ioport80_write(void *opaque, uint32_t addr, uint32_t data)
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{
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}
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/* MSDOS compatibility mode FPU exception support */
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static qemu_irq ferr_irq;
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/* XXX: add IGNNE support */
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void cpu_set_ferr(CPUX86State *s)
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{
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    qemu_irq_raise(ferr_irq);
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}
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static void ioportF0_write(void *opaque, uint32_t addr, uint32_t data)
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{
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    qemu_irq_lower(ferr_irq);
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}
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/* TSC handling */
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uint64_t cpu_get_tsc(CPUX86State *env)
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{
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    /* Note: when using kqemu, it is more logical to return the host TSC
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       because kqemu does not trap the RDTSC instruction for
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       performance reasons */
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#ifdef USE_KQEMU
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    if (env->kqemu_enabled) {
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        return cpu_get_real_ticks();
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    } else
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#endif
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    {
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        return cpu_get_ticks();
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    }
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}
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/* SMM support */
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void cpu_smm_update(CPUState *env)
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{
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    if (i440fx_state && env == first_cpu)
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        i440fx_set_smm(i440fx_state, (env->hflags >> HF_SMM_SHIFT) & 1);
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}
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/* IRQ handling */
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int cpu_get_pic_interrupt(CPUState *env)
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{
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    int intno;
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    intno = apic_get_interrupt(env);
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    if (intno >= 0) {
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        /* set irq request if a PIC irq is still pending */
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        /* XXX: improve that */
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        pic_update_irq(isa_pic);
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        return intno;
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    }
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    /* read the irq from the PIC */
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    if (!apic_accept_pic_intr(env))
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        return -1;
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    intno = pic_read_irq(isa_pic);
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    return intno;
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}
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static void pic_irq_request(void *opaque, int irq, int level)
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{
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    CPUState *env = first_cpu;
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    if (env->apic_state) {
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        while (env) {
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            if (apic_accept_pic_intr(env))
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                apic_deliver_pic_intr(env, level);
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            env = env->next_cpu;
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        }
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    } else {
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        if (level)
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            cpu_interrupt(env, CPU_INTERRUPT_HARD);
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        else
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            cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
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    }
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}
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/* PC cmos mappings */
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#define REG_EQUIPMENT_BYTE          0x14
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static int cmos_get_fd_drive_type(int fd0)
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{
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    int val;
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    switch (fd0) {
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    case 0:
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        /* 1.44 Mb 3"5 drive */
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        val = 4;
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        break;
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    case 1:
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        /* 2.88 Mb 3"5 drive */
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        val = 5;
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        break;
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    case 2:
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        /* 1.2 Mb 5"5 drive */
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        val = 2;
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        break;
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    default:
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        val = 0;
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        break;
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    }
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    return val;
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}
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static void cmos_init_hd(int type_ofs, int info_ofs, BlockDriverState *hd)
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{
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    RTCState *s = rtc_state;
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    int cylinders, heads, sectors;
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    bdrv_get_geometry_hint(hd, &cylinders, &heads, &sectors);
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    rtc_set_memory(s, type_ofs, 47);
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    rtc_set_memory(s, info_ofs, cylinders);
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    rtc_set_memory(s, info_ofs + 1, cylinders >> 8);
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    rtc_set_memory(s, info_ofs + 2, heads);
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    rtc_set_memory(s, info_ofs + 3, 0xff);
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    rtc_set_memory(s, info_ofs + 4, 0xff);
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    rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3));
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    rtc_set_memory(s, info_ofs + 6, cylinders);
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    rtc_set_memory(s, info_ofs + 7, cylinders >> 8);
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    rtc_set_memory(s, info_ofs + 8, sectors);
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}
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/* convert boot_device letter to something recognizable by the bios */
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static int boot_device2nibble(char boot_device)
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{
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    switch(boot_device) {
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    case 'a':
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    case 'b':
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        return 0x01; /* floppy boot */
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    case 'c':
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        return 0x02; /* hard drive boot */
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    case 'd':
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        return 0x03; /* CD-ROM boot */
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    case 'n':
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        return 0x04; /* Network boot */
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    }
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    return 0;
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}
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/* copy/pasted from cmos_init, should be made a general function
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 and used there as well */
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static int pc_boot_set(void *opaque, const char *boot_device)
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{
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#define PC_MAX_BOOT_DEVICES 3
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    RTCState *s = (RTCState *)opaque;
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    int nbds, bds[3] = { 0, };
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    int i;
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    nbds = strlen(boot_device);
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    if (nbds > PC_MAX_BOOT_DEVICES) {
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        term_printf("Too many boot devices for PC\n");
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        return(1);
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    }
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    for (i = 0; i < nbds; i++) {
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        bds[i] = boot_device2nibble(boot_device[i]);
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        if (bds[i] == 0) {
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            term_printf("Invalid boot device for PC: '%c'\n",
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                    boot_device[i]);
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            return(1);
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        }
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    }
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    rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]);
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    rtc_set_memory(s, 0x38, (bds[2] << 4));
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    return(0);
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}
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/* hd_table must contain 4 block drivers */
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static void cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size,
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                      const char *boot_device, BlockDriverState **hd_table)
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{
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    RTCState *s = rtc_state;
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    int nbds, bds[3] = { 0, };
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    int val;
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    int fd0, fd1, nb;
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    int i;
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    /* various important CMOS locations needed by PC/Bochs bios */
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    /* memory size */
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    val = 640; /* base memory in K */
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    rtc_set_memory(s, 0x15, val);
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    rtc_set_memory(s, 0x16, val >> 8);
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    val = (ram_size / 1024) - 1024;
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    if (val > 65535)
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        val = 65535;
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    rtc_set_memory(s, 0x17, val);
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    rtc_set_memory(s, 0x18, val >> 8);
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    rtc_set_memory(s, 0x30, val);
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    rtc_set_memory(s, 0x31, val >> 8);
254 80cabfad bellard
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    if (above_4g_mem_size) {
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        rtc_set_memory(s, 0x5b, (unsigned int)above_4g_mem_size >> 16);
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        rtc_set_memory(s, 0x5c, (unsigned int)above_4g_mem_size >> 24);
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        rtc_set_memory(s, 0x5d, (uint64_t)above_4g_mem_size >> 32);
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    }
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    if (ram_size > (16 * 1024 * 1024))
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        val = (ram_size / 65536) - ((16 * 1024 * 1024) / 65536);
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    else
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        val = 0;
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    if (val > 65535)
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        val = 65535;
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    rtc_set_memory(s, 0x34, val);
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    rtc_set_memory(s, 0x35, val >> 8);
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    /* set the number of CPU */
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    rtc_set_memory(s, 0x5f, smp_cpus - 1);
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    /* set boot devices, and disable floppy signature check if requested */
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#define PC_MAX_BOOT_DEVICES 3
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    nbds = strlen(boot_device);
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    if (nbds > PC_MAX_BOOT_DEVICES) {
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        fprintf(stderr, "Too many boot devices for PC\n");
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        exit(1);
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    }
280 28c5af54 j_mayer
    for (i = 0; i < nbds; i++) {
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        bds[i] = boot_device2nibble(boot_device[i]);
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        if (bds[i] == 0) {
283 28c5af54 j_mayer
            fprintf(stderr, "Invalid boot device for PC: '%c'\n",
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                    boot_device[i]);
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            exit(1);
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        }
287 28c5af54 j_mayer
    }
288 28c5af54 j_mayer
    rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]);
289 28c5af54 j_mayer
    rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ?  0x0 : 0x1));
290 80cabfad bellard
291 b41a2cd1 bellard
    /* floppy type */
292 b41a2cd1 bellard
293 baca51fa bellard
    fd0 = fdctrl_get_drive_type(floppy_controller, 0);
294 baca51fa bellard
    fd1 = fdctrl_get_drive_type(floppy_controller, 1);
295 80cabfad bellard
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    val = (cmos_get_fd_drive_type(fd0) << 4) | cmos_get_fd_drive_type(fd1);
297 b0a21b53 bellard
    rtc_set_memory(s, 0x10, val);
298 3b46e624 ths
299 b0a21b53 bellard
    val = 0;
300 b41a2cd1 bellard
    nb = 0;
301 80cabfad bellard
    if (fd0 < 3)
302 80cabfad bellard
        nb++;
303 80cabfad bellard
    if (fd1 < 3)
304 80cabfad bellard
        nb++;
305 80cabfad bellard
    switch (nb) {
306 80cabfad bellard
    case 0:
307 80cabfad bellard
        break;
308 80cabfad bellard
    case 1:
309 b0a21b53 bellard
        val |= 0x01; /* 1 drive, ready for boot */
310 80cabfad bellard
        break;
311 80cabfad bellard
    case 2:
312 b0a21b53 bellard
        val |= 0x41; /* 2 drives, ready for boot */
313 80cabfad bellard
        break;
314 80cabfad bellard
    }
315 b0a21b53 bellard
    val |= 0x02; /* FPU is there */
316 b0a21b53 bellard
    val |= 0x04; /* PS/2 mouse installed */
317 b0a21b53 bellard
    rtc_set_memory(s, REG_EQUIPMENT_BYTE, val);
318 b0a21b53 bellard
319 ba6c2377 bellard
    /* hard drives */
320 ba6c2377 bellard
321 ba6c2377 bellard
    rtc_set_memory(s, 0x12, (hd_table[0] ? 0xf0 : 0) | (hd_table[1] ? 0x0f : 0));
322 ba6c2377 bellard
    if (hd_table[0])
323 ba6c2377 bellard
        cmos_init_hd(0x19, 0x1b, hd_table[0]);
324 5fafdf24 ths
    if (hd_table[1])
325 ba6c2377 bellard
        cmos_init_hd(0x1a, 0x24, hd_table[1]);
326 ba6c2377 bellard
327 ba6c2377 bellard
    val = 0;
328 40b6ecc6 bellard
    for (i = 0; i < 4; i++) {
329 ba6c2377 bellard
        if (hd_table[i]) {
330 46d4767d bellard
            int cylinders, heads, sectors, translation;
331 46d4767d bellard
            /* NOTE: bdrv_get_geometry_hint() returns the physical
332 46d4767d bellard
                geometry.  It is always such that: 1 <= sects <= 63, 1
333 46d4767d bellard
                <= heads <= 16, 1 <= cylinders <= 16383. The BIOS
334 46d4767d bellard
                geometry can be different if a translation is done. */
335 46d4767d bellard
            translation = bdrv_get_translation_hint(hd_table[i]);
336 46d4767d bellard
            if (translation == BIOS_ATA_TRANSLATION_AUTO) {
337 46d4767d bellard
                bdrv_get_geometry_hint(hd_table[i], &cylinders, &heads, &sectors);
338 46d4767d bellard
                if (cylinders <= 1024 && heads <= 16 && sectors <= 63) {
339 46d4767d bellard
                    /* No translation. */
340 46d4767d bellard
                    translation = 0;
341 46d4767d bellard
                } else {
342 46d4767d bellard
                    /* LBA translation. */
343 46d4767d bellard
                    translation = 1;
344 46d4767d bellard
                }
345 40b6ecc6 bellard
            } else {
346 46d4767d bellard
                translation--;
347 ba6c2377 bellard
            }
348 ba6c2377 bellard
            val |= translation << (i * 2);
349 ba6c2377 bellard
        }
350 40b6ecc6 bellard
    }
351 ba6c2377 bellard
    rtc_set_memory(s, 0x39, val);
352 80cabfad bellard
}
353 80cabfad bellard
354 59b8ad81 bellard
void ioport_set_a20(int enable)
355 59b8ad81 bellard
{
356 59b8ad81 bellard
    /* XXX: send to all CPUs ? */
357 59b8ad81 bellard
    cpu_x86_set_a20(first_cpu, enable);
358 59b8ad81 bellard
}
359 59b8ad81 bellard
360 59b8ad81 bellard
int ioport_get_a20(void)
361 59b8ad81 bellard
{
362 59b8ad81 bellard
    return ((first_cpu->a20_mask >> 20) & 1);
363 59b8ad81 bellard
}
364 59b8ad81 bellard
365 e1a23744 bellard
static void ioport92_write(void *opaque, uint32_t addr, uint32_t val)
366 e1a23744 bellard
{
367 59b8ad81 bellard
    ioport_set_a20((val >> 1) & 1);
368 e1a23744 bellard
    /* XXX: bit 0 is fast reset */
369 e1a23744 bellard
}
370 e1a23744 bellard
371 e1a23744 bellard
static uint32_t ioport92_read(void *opaque, uint32_t addr)
372 e1a23744 bellard
{
373 59b8ad81 bellard
    return ioport_get_a20() << 1;
374 e1a23744 bellard
}
375 e1a23744 bellard
376 80cabfad bellard
/***********************************************************/
377 80cabfad bellard
/* Bochs BIOS debug ports */
378 80cabfad bellard
379 9596ebb7 pbrook
static void bochs_bios_write(void *opaque, uint32_t addr, uint32_t val)
380 80cabfad bellard
{
381 a2f659ee bellard
    static const char shutdown_str[8] = "Shutdown";
382 a2f659ee bellard
    static int shutdown_index = 0;
383 3b46e624 ths
384 80cabfad bellard
    switch(addr) {
385 80cabfad bellard
        /* Bochs BIOS messages */
386 80cabfad bellard
    case 0x400:
387 80cabfad bellard
    case 0x401:
388 80cabfad bellard
        fprintf(stderr, "BIOS panic at rombios.c, line %d\n", val);
389 80cabfad bellard
        exit(1);
390 80cabfad bellard
    case 0x402:
391 80cabfad bellard
    case 0x403:
392 80cabfad bellard
#ifdef DEBUG_BIOS
393 80cabfad bellard
        fprintf(stderr, "%c", val);
394 80cabfad bellard
#endif
395 80cabfad bellard
        break;
396 a2f659ee bellard
    case 0x8900:
397 a2f659ee bellard
        /* same as Bochs power off */
398 a2f659ee bellard
        if (val == shutdown_str[shutdown_index]) {
399 a2f659ee bellard
            shutdown_index++;
400 a2f659ee bellard
            if (shutdown_index == 8) {
401 a2f659ee bellard
                shutdown_index = 0;
402 a2f659ee bellard
                qemu_system_shutdown_request();
403 a2f659ee bellard
            }
404 a2f659ee bellard
        } else {
405 a2f659ee bellard
            shutdown_index = 0;
406 a2f659ee bellard
        }
407 a2f659ee bellard
        break;
408 80cabfad bellard
409 80cabfad bellard
        /* LGPL'ed VGA BIOS messages */
410 80cabfad bellard
    case 0x501:
411 80cabfad bellard
    case 0x502:
412 80cabfad bellard
        fprintf(stderr, "VGA BIOS panic, line %d\n", val);
413 80cabfad bellard
        exit(1);
414 80cabfad bellard
    case 0x500:
415 80cabfad bellard
    case 0x503:
416 80cabfad bellard
#ifdef DEBUG_BIOS
417 80cabfad bellard
        fprintf(stderr, "%c", val);
418 80cabfad bellard
#endif
419 80cabfad bellard
        break;
420 80cabfad bellard
    }
421 80cabfad bellard
}
422 80cabfad bellard
423 9596ebb7 pbrook
static void bochs_bios_init(void)
424 80cabfad bellard
{
425 3cce6243 blueswir1
    void *fw_cfg;
426 3cce6243 blueswir1
427 b41a2cd1 bellard
    register_ioport_write(0x400, 1, 2, bochs_bios_write, NULL);
428 b41a2cd1 bellard
    register_ioport_write(0x401, 1, 2, bochs_bios_write, NULL);
429 b41a2cd1 bellard
    register_ioport_write(0x402, 1, 1, bochs_bios_write, NULL);
430 b41a2cd1 bellard
    register_ioport_write(0x403, 1, 1, bochs_bios_write, NULL);
431 a2f659ee bellard
    register_ioport_write(0x8900, 1, 1, bochs_bios_write, NULL);
432 b41a2cd1 bellard
433 b41a2cd1 bellard
    register_ioport_write(0x501, 1, 2, bochs_bios_write, NULL);
434 b41a2cd1 bellard
    register_ioport_write(0x502, 1, 2, bochs_bios_write, NULL);
435 b41a2cd1 bellard
    register_ioport_write(0x500, 1, 1, bochs_bios_write, NULL);
436 b41a2cd1 bellard
    register_ioport_write(0x503, 1, 1, bochs_bios_write, NULL);
437 3cce6243 blueswir1
438 3cce6243 blueswir1
    fw_cfg = fw_cfg_init(BIOS_CFG_IOPORT, BIOS_CFG_IOPORT + 1, 0, 0);
439 3cce6243 blueswir1
    fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
440 905fdcb5 blueswir1
    fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
441 80cabfad bellard
}
442 80cabfad bellard
443 642a4f96 ths
/* Generate an initial boot sector which sets state and jump to
444 642a4f96 ths
   a specified vector */
445 4fc9af53 aliguori
static void generate_bootsect(uint8_t *option_rom,
446 4fc9af53 aliguori
                              uint32_t gpr[8], uint16_t segs[6], uint16_t ip)
447 642a4f96 ths
{
448 4fc9af53 aliguori
    uint8_t rom[512], *p, *reloc;
449 4fc9af53 aliguori
    uint8_t sum;
450 642a4f96 ths
    int i;
451 642a4f96 ths
452 4fc9af53 aliguori
    memset(rom, 0, sizeof(rom));
453 4fc9af53 aliguori
454 4fc9af53 aliguori
    p = rom;
455 4fc9af53 aliguori
    /* Make sure we have an option rom signature */
456 4fc9af53 aliguori
    *p++ = 0x55;
457 4fc9af53 aliguori
    *p++ = 0xaa;
458 642a4f96 ths
459 4fc9af53 aliguori
    /* ROM size in sectors*/
460 4fc9af53 aliguori
    *p++ = 1;
461 642a4f96 ths
462 4fc9af53 aliguori
    /* Hook int19 */
463 642a4f96 ths
464 4fc9af53 aliguori
    *p++ = 0x50;                /* push ax */
465 4fc9af53 aliguori
    *p++ = 0x1e;                /* push ds */
466 4fc9af53 aliguori
    *p++ = 0x31; *p++ = 0xc0;        /* xor ax, ax */
467 4fc9af53 aliguori
    *p++ = 0x8e; *p++ = 0xd8;        /* mov ax, ds */
468 642a4f96 ths
469 4fc9af53 aliguori
    *p++ = 0xc7; *p++ = 0x06;   /* movvw _start,0x64 */
470 4fc9af53 aliguori
    *p++ = 0x64; *p++ = 0x00;
471 4fc9af53 aliguori
    reloc = p;
472 4fc9af53 aliguori
    *p++ = 0x00; *p++ = 0x00;
473 4fc9af53 aliguori
474 4fc9af53 aliguori
    *p++ = 0x8c; *p++ = 0x0e;   /* mov cs,0x66 */
475 4fc9af53 aliguori
    *p++ = 0x66; *p++ = 0x00;
476 4fc9af53 aliguori
477 4fc9af53 aliguori
    *p++ = 0x1f;                /* pop ds */
478 4fc9af53 aliguori
    *p++ = 0x58;                /* pop ax */
479 4fc9af53 aliguori
    *p++ = 0xcb;                /* lret */
480 4fc9af53 aliguori
    
481 642a4f96 ths
    /* Actual code */
482 4fc9af53 aliguori
    *reloc = (p - rom);
483 4fc9af53 aliguori
484 642a4f96 ths
    *p++ = 0xfa;                /* CLI */
485 642a4f96 ths
    *p++ = 0xfc;                /* CLD */
486 642a4f96 ths
487 642a4f96 ths
    for (i = 0; i < 6; i++) {
488 642a4f96 ths
        if (i == 1)                /* Skip CS */
489 642a4f96 ths
            continue;
490 642a4f96 ths
491 642a4f96 ths
        *p++ = 0xb8;                /* MOV AX,imm16 */
492 642a4f96 ths
        *p++ = segs[i];
493 642a4f96 ths
        *p++ = segs[i] >> 8;
494 642a4f96 ths
        *p++ = 0x8e;                /* MOV <seg>,AX */
495 642a4f96 ths
        *p++ = 0xc0 + (i << 3);
496 642a4f96 ths
    }
497 642a4f96 ths
498 642a4f96 ths
    for (i = 0; i < 8; i++) {
499 642a4f96 ths
        *p++ = 0x66;                /* 32-bit operand size */
500 642a4f96 ths
        *p++ = 0xb8 + i;        /* MOV <reg>,imm32 */
501 642a4f96 ths
        *p++ = gpr[i];
502 642a4f96 ths
        *p++ = gpr[i] >> 8;
503 642a4f96 ths
        *p++ = gpr[i] >> 16;
504 642a4f96 ths
        *p++ = gpr[i] >> 24;
505 642a4f96 ths
    }
506 642a4f96 ths
507 642a4f96 ths
    *p++ = 0xea;                /* JMP FAR */
508 642a4f96 ths
    *p++ = ip;                        /* IP */
509 642a4f96 ths
    *p++ = ip >> 8;
510 642a4f96 ths
    *p++ = segs[1];                /* CS */
511 642a4f96 ths
    *p++ = segs[1] >> 8;
512 642a4f96 ths
513 4fc9af53 aliguori
    /* sign rom */
514 4fc9af53 aliguori
    sum = 0;
515 4fc9af53 aliguori
    for (i = 0; i < (sizeof(rom) - 1); i++)
516 4fc9af53 aliguori
        sum += rom[i];
517 4fc9af53 aliguori
    rom[sizeof(rom) - 1] = -sum;
518 4fc9af53 aliguori
519 4fc9af53 aliguori
    memcpy(option_rom, rom, sizeof(rom));
520 642a4f96 ths
}
521 80cabfad bellard
522 642a4f96 ths
static long get_file_size(FILE *f)
523 642a4f96 ths
{
524 642a4f96 ths
    long where, size;
525 642a4f96 ths
526 642a4f96 ths
    /* XXX: on Unix systems, using fstat() probably makes more sense */
527 642a4f96 ths
528 642a4f96 ths
    where = ftell(f);
529 642a4f96 ths
    fseek(f, 0, SEEK_END);
530 642a4f96 ths
    size = ftell(f);
531 642a4f96 ths
    fseek(f, where, SEEK_SET);
532 642a4f96 ths
533 642a4f96 ths
    return size;
534 642a4f96 ths
}
535 642a4f96 ths
536 4fc9af53 aliguori
static void load_linux(uint8_t *option_rom,
537 4fc9af53 aliguori
                       const char *kernel_filename,
538 642a4f96 ths
                       const char *initrd_filename,
539 642a4f96 ths
                       const char *kernel_cmdline)
540 642a4f96 ths
{
541 642a4f96 ths
    uint16_t protocol;
542 642a4f96 ths
    uint32_t gpr[8];
543 642a4f96 ths
    uint16_t seg[6];
544 642a4f96 ths
    uint16_t real_seg;
545 642a4f96 ths
    int setup_size, kernel_size, initrd_size, cmdline_size;
546 642a4f96 ths
    uint32_t initrd_max;
547 642a4f96 ths
    uint8_t header[1024];
548 a37af289 blueswir1
    target_phys_addr_t real_addr, prot_addr, cmdline_addr, initrd_addr;
549 642a4f96 ths
    FILE *f, *fi;
550 642a4f96 ths
551 642a4f96 ths
    /* Align to 16 bytes as a paranoia measure */
552 642a4f96 ths
    cmdline_size = (strlen(kernel_cmdline)+16) & ~15;
553 642a4f96 ths
554 642a4f96 ths
    /* load the kernel header */
555 642a4f96 ths
    f = fopen(kernel_filename, "rb");
556 642a4f96 ths
    if (!f || !(kernel_size = get_file_size(f)) ||
557 642a4f96 ths
        fread(header, 1, 1024, f) != 1024) {
558 642a4f96 ths
        fprintf(stderr, "qemu: could not load kernel '%s'\n",
559 642a4f96 ths
                kernel_filename);
560 642a4f96 ths
        exit(1);
561 642a4f96 ths
    }
562 642a4f96 ths
563 642a4f96 ths
    /* kernel protocol version */
564 bc4edd79 bellard
#if 0
565 642a4f96 ths
    fprintf(stderr, "header magic: %#x\n", ldl_p(header+0x202));
566 bc4edd79 bellard
#endif
567 642a4f96 ths
    if (ldl_p(header+0x202) == 0x53726448)
568 642a4f96 ths
        protocol = lduw_p(header+0x206);
569 642a4f96 ths
    else
570 642a4f96 ths
        protocol = 0;
571 642a4f96 ths
572 642a4f96 ths
    if (protocol < 0x200 || !(header[0x211] & 0x01)) {
573 642a4f96 ths
        /* Low kernel */
574 a37af289 blueswir1
        real_addr    = 0x90000;
575 a37af289 blueswir1
        cmdline_addr = 0x9a000 - cmdline_size;
576 a37af289 blueswir1
        prot_addr    = 0x10000;
577 642a4f96 ths
    } else if (protocol < 0x202) {
578 642a4f96 ths
        /* High but ancient kernel */
579 a37af289 blueswir1
        real_addr    = 0x90000;
580 a37af289 blueswir1
        cmdline_addr = 0x9a000 - cmdline_size;
581 a37af289 blueswir1
        prot_addr    = 0x100000;
582 642a4f96 ths
    } else {
583 642a4f96 ths
        /* High and recent kernel */
584 a37af289 blueswir1
        real_addr    = 0x10000;
585 a37af289 blueswir1
        cmdline_addr = 0x20000;
586 a37af289 blueswir1
        prot_addr    = 0x100000;
587 642a4f96 ths
    }
588 642a4f96 ths
589 bc4edd79 bellard
#if 0
590 642a4f96 ths
    fprintf(stderr,
591 526ccb7a balrog
            "qemu: real_addr     = 0x" TARGET_FMT_plx "\n"
592 526ccb7a balrog
            "qemu: cmdline_addr  = 0x" TARGET_FMT_plx "\n"
593 526ccb7a balrog
            "qemu: prot_addr     = 0x" TARGET_FMT_plx "\n",
594 a37af289 blueswir1
            real_addr,
595 a37af289 blueswir1
            cmdline_addr,
596 a37af289 blueswir1
            prot_addr);
597 bc4edd79 bellard
#endif
598 642a4f96 ths
599 642a4f96 ths
    /* highest address for loading the initrd */
600 642a4f96 ths
    if (protocol >= 0x203)
601 642a4f96 ths
        initrd_max = ldl_p(header+0x22c);
602 642a4f96 ths
    else
603 642a4f96 ths
        initrd_max = 0x37ffffff;
604 642a4f96 ths
605 642a4f96 ths
    if (initrd_max >= ram_size-ACPI_DATA_SIZE)
606 642a4f96 ths
        initrd_max = ram_size-ACPI_DATA_SIZE-1;
607 642a4f96 ths
608 642a4f96 ths
    /* kernel command line */
609 a37af289 blueswir1
    pstrcpy_targphys(cmdline_addr, 4096, kernel_cmdline);
610 642a4f96 ths
611 642a4f96 ths
    if (protocol >= 0x202) {
612 a37af289 blueswir1
        stl_p(header+0x228, cmdline_addr);
613 642a4f96 ths
    } else {
614 642a4f96 ths
        stw_p(header+0x20, 0xA33F);
615 642a4f96 ths
        stw_p(header+0x22, cmdline_addr-real_addr);
616 642a4f96 ths
    }
617 642a4f96 ths
618 642a4f96 ths
    /* loader type */
619 642a4f96 ths
    /* High nybble = B reserved for Qemu; low nybble is revision number.
620 642a4f96 ths
       If this code is substantially changed, you may want to consider
621 642a4f96 ths
       incrementing the revision. */
622 642a4f96 ths
    if (protocol >= 0x200)
623 642a4f96 ths
        header[0x210] = 0xB0;
624 642a4f96 ths
625 642a4f96 ths
    /* heap */
626 642a4f96 ths
    if (protocol >= 0x201) {
627 642a4f96 ths
        header[0x211] |= 0x80;        /* CAN_USE_HEAP */
628 642a4f96 ths
        stw_p(header+0x224, cmdline_addr-real_addr-0x200);
629 642a4f96 ths
    }
630 642a4f96 ths
631 642a4f96 ths
    /* load initrd */
632 642a4f96 ths
    if (initrd_filename) {
633 642a4f96 ths
        if (protocol < 0x200) {
634 642a4f96 ths
            fprintf(stderr, "qemu: linux kernel too old to load a ram disk\n");
635 642a4f96 ths
            exit(1);
636 642a4f96 ths
        }
637 642a4f96 ths
638 642a4f96 ths
        fi = fopen(initrd_filename, "rb");
639 642a4f96 ths
        if (!fi) {
640 642a4f96 ths
            fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
641 642a4f96 ths
                    initrd_filename);
642 642a4f96 ths
            exit(1);
643 642a4f96 ths
        }
644 642a4f96 ths
645 642a4f96 ths
        initrd_size = get_file_size(fi);
646 a37af289 blueswir1
        initrd_addr = (initrd_max-initrd_size) & ~4095;
647 642a4f96 ths
648 526ccb7a balrog
        fprintf(stderr, "qemu: loading initrd (%#x bytes) at 0x" TARGET_FMT_plx
649 526ccb7a balrog
                "\n", initrd_size, initrd_addr);
650 642a4f96 ths
651 a37af289 blueswir1
        if (!fread_targphys_ok(initrd_addr, initrd_size, fi)) {
652 642a4f96 ths
            fprintf(stderr, "qemu: read error on initial ram disk '%s'\n",
653 642a4f96 ths
                    initrd_filename);
654 642a4f96 ths
            exit(1);
655 642a4f96 ths
        }
656 642a4f96 ths
        fclose(fi);
657 642a4f96 ths
658 a37af289 blueswir1
        stl_p(header+0x218, initrd_addr);
659 642a4f96 ths
        stl_p(header+0x21c, initrd_size);
660 642a4f96 ths
    }
661 642a4f96 ths
662 642a4f96 ths
    /* store the finalized header and load the rest of the kernel */
663 a37af289 blueswir1
    cpu_physical_memory_write(real_addr, header, 1024);
664 642a4f96 ths
665 642a4f96 ths
    setup_size = header[0x1f1];
666 642a4f96 ths
    if (setup_size == 0)
667 642a4f96 ths
        setup_size = 4;
668 642a4f96 ths
669 642a4f96 ths
    setup_size = (setup_size+1)*512;
670 642a4f96 ths
    kernel_size -= setup_size;        /* Size of protected-mode code */
671 642a4f96 ths
672 a37af289 blueswir1
    if (!fread_targphys_ok(real_addr+1024, setup_size-1024, f) ||
673 a37af289 blueswir1
        !fread_targphys_ok(prot_addr, kernel_size, f)) {
674 642a4f96 ths
        fprintf(stderr, "qemu: read error on kernel '%s'\n",
675 642a4f96 ths
                kernel_filename);
676 642a4f96 ths
        exit(1);
677 642a4f96 ths
    }
678 642a4f96 ths
    fclose(f);
679 642a4f96 ths
680 642a4f96 ths
    /* generate bootsector to set up the initial register state */
681 a37af289 blueswir1
    real_seg = real_addr >> 4;
682 642a4f96 ths
    seg[0] = seg[2] = seg[3] = seg[4] = seg[4] = real_seg;
683 642a4f96 ths
    seg[1] = real_seg+0x20;        /* CS */
684 642a4f96 ths
    memset(gpr, 0, sizeof gpr);
685 642a4f96 ths
    gpr[4] = cmdline_addr-real_addr-16;        /* SP (-16 is paranoia) */
686 642a4f96 ths
687 4fc9af53 aliguori
    generate_bootsect(option_rom, gpr, seg, 0);
688 642a4f96 ths
}
689 642a4f96 ths
690 59b8ad81 bellard
static void main_cpu_reset(void *opaque)
691 59b8ad81 bellard
{
692 59b8ad81 bellard
    CPUState *env = opaque;
693 59b8ad81 bellard
    cpu_reset(env);
694 59b8ad81 bellard
}
695 59b8ad81 bellard
696 b41a2cd1 bellard
static const int ide_iobase[2] = { 0x1f0, 0x170 };
697 b41a2cd1 bellard
static const int ide_iobase2[2] = { 0x3f6, 0x376 };
698 b41a2cd1 bellard
static const int ide_irq[2] = { 14, 15 };
699 b41a2cd1 bellard
700 b41a2cd1 bellard
#define NE2000_NB_MAX 6
701 b41a2cd1 bellard
702 8d11df9e bellard
static int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 0x280, 0x380 };
703 b41a2cd1 bellard
static int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
704 b41a2cd1 bellard
705 8d11df9e bellard
static int serial_io[MAX_SERIAL_PORTS] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8 };
706 8d11df9e bellard
static int serial_irq[MAX_SERIAL_PORTS] = { 4, 3, 4, 3 };
707 8d11df9e bellard
708 6508fe59 bellard
static int parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc };
709 6508fe59 bellard
static int parallel_irq[MAX_PARALLEL_PORTS] = { 7, 7, 7 };
710 6508fe59 bellard
711 6a36d84e bellard
#ifdef HAS_AUDIO
712 d537cf6c pbrook
static void audio_init (PCIBus *pci_bus, qemu_irq *pic)
713 6a36d84e bellard
{
714 6a36d84e bellard
    struct soundhw *c;
715 6a36d84e bellard
    int audio_enabled = 0;
716 6a36d84e bellard
717 6a36d84e bellard
    for (c = soundhw; !audio_enabled && c->name; ++c) {
718 6a36d84e bellard
        audio_enabled = c->enabled;
719 6a36d84e bellard
    }
720 6a36d84e bellard
721 6a36d84e bellard
    if (audio_enabled) {
722 6a36d84e bellard
        AudioState *s;
723 6a36d84e bellard
724 6a36d84e bellard
        s = AUD_init ();
725 6a36d84e bellard
        if (s) {
726 6a36d84e bellard
            for (c = soundhw; c->name; ++c) {
727 6a36d84e bellard
                if (c->enabled) {
728 6a36d84e bellard
                    if (c->isa) {
729 d537cf6c pbrook
                        c->init.init_isa (s, pic);
730 6a36d84e bellard
                    }
731 6a36d84e bellard
                    else {
732 6a36d84e bellard
                        if (pci_bus) {
733 6a36d84e bellard
                            c->init.init_pci (pci_bus, s);
734 6a36d84e bellard
                        }
735 6a36d84e bellard
                    }
736 6a36d84e bellard
                }
737 6a36d84e bellard
            }
738 6a36d84e bellard
        }
739 6a36d84e bellard
    }
740 6a36d84e bellard
}
741 6a36d84e bellard
#endif
742 6a36d84e bellard
743 d537cf6c pbrook
static void pc_init_ne2k_isa(NICInfo *nd, qemu_irq *pic)
744 a41b2ff2 pbrook
{
745 a41b2ff2 pbrook
    static int nb_ne2k = 0;
746 a41b2ff2 pbrook
747 a41b2ff2 pbrook
    if (nb_ne2k == NE2000_NB_MAX)
748 a41b2ff2 pbrook
        return;
749 d537cf6c pbrook
    isa_ne2000_init(ne2000_io[nb_ne2k], pic[ne2000_irq[nb_ne2k]], nd);
750 a41b2ff2 pbrook
    nb_ne2k++;
751 a41b2ff2 pbrook
}
752 a41b2ff2 pbrook
753 80cabfad bellard
/* PC hardware initialisation */
754 00f82b8a aurel32
static void pc_init1(ram_addr_t ram_size, int vga_ram_size,
755 3023f332 aliguori
                     const char *boot_device,
756 b5ff2d6e bellard
                     const char *kernel_filename, const char *kernel_cmdline,
757 3dbbdc25 bellard
                     const char *initrd_filename,
758 a049de61 bellard
                     int pci_enabled, const char *cpu_model)
759 80cabfad bellard
{
760 80cabfad bellard
    char buf[1024];
761 642a4f96 ths
    int ret, linux_boot, i;
762 970ac5a3 bellard
    ram_addr_t ram_addr, vga_ram_addr, bios_offset, vga_bios_offset;
763 00f82b8a aurel32
    ram_addr_t below_4g_mem_size, above_4g_mem_size = 0;
764 970ac5a3 bellard
    int bios_size, isa_bios_size, vga_bios_size;
765 46e50e9d bellard
    PCIBus *pci_bus;
766 5c3ff3a7 pbrook
    int piix3_devfn = -1;
767 59b8ad81 bellard
    CPUState *env;
768 d537cf6c pbrook
    qemu_irq *cpu_irq;
769 d537cf6c pbrook
    qemu_irq *i8259;
770 e4bcb14c ths
    int index;
771 e4bcb14c ths
    BlockDriverState *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
772 e4bcb14c ths
    BlockDriverState *fd[MAX_FD];
773 d592d303 bellard
774 00f82b8a aurel32
    if (ram_size >= 0xe0000000 ) {
775 00f82b8a aurel32
        above_4g_mem_size = ram_size - 0xe0000000;
776 00f82b8a aurel32
        below_4g_mem_size = 0xe0000000;
777 00f82b8a aurel32
    } else {
778 00f82b8a aurel32
        below_4g_mem_size = ram_size;
779 00f82b8a aurel32
    }
780 00f82b8a aurel32
781 80cabfad bellard
    linux_boot = (kernel_filename != NULL);
782 80cabfad bellard
783 59b8ad81 bellard
    /* init CPUs */
784 a049de61 bellard
    if (cpu_model == NULL) {
785 a049de61 bellard
#ifdef TARGET_X86_64
786 a049de61 bellard
        cpu_model = "qemu64";
787 a049de61 bellard
#else
788 a049de61 bellard
        cpu_model = "qemu32";
789 a049de61 bellard
#endif
790 a049de61 bellard
    }
791 a049de61 bellard
    
792 59b8ad81 bellard
    for(i = 0; i < smp_cpus; i++) {
793 aaed909a bellard
        env = cpu_init(cpu_model);
794 aaed909a bellard
        if (!env) {
795 aaed909a bellard
            fprintf(stderr, "Unable to find x86 CPU definition\n");
796 aaed909a bellard
            exit(1);
797 aaed909a bellard
        }
798 59b8ad81 bellard
        if (i != 0)
799 ce5232c5 bellard
            env->halted = 1;
800 59b8ad81 bellard
        if (smp_cpus > 1) {
801 59b8ad81 bellard
            /* XXX: enable it in all cases */
802 59b8ad81 bellard
            env->cpuid_features |= CPUID_APIC;
803 59b8ad81 bellard
        }
804 59b8ad81 bellard
        qemu_register_reset(main_cpu_reset, env);
805 59b8ad81 bellard
        if (pci_enabled) {
806 59b8ad81 bellard
            apic_init(env);
807 59b8ad81 bellard
        }
808 59b8ad81 bellard
    }
809 59b8ad81 bellard
810 26fb5e48 aurel32
    vmport_init();
811 26fb5e48 aurel32
812 80cabfad bellard
    /* allocate RAM */
813 82b36dc3 aliguori
    ram_addr = qemu_ram_alloc(0xa0000);
814 82b36dc3 aliguori
    cpu_register_physical_memory(0, 0xa0000, ram_addr);
815 82b36dc3 aliguori
816 82b36dc3 aliguori
    /* Allocate, even though we won't register, so we don't break the
817 82b36dc3 aliguori
     * phys_ram_base + PA assumption. This range includes vga (0xa0000 - 0xc0000),
818 82b36dc3 aliguori
     * and some bios areas, which will be registered later
819 82b36dc3 aliguori
     */
820 82b36dc3 aliguori
    ram_addr = qemu_ram_alloc(0x100000 - 0xa0000);
821 82b36dc3 aliguori
    ram_addr = qemu_ram_alloc(below_4g_mem_size - 0x100000);
822 82b36dc3 aliguori
    cpu_register_physical_memory(0x100000,
823 82b36dc3 aliguori
                 below_4g_mem_size - 0x100000,
824 82b36dc3 aliguori
                 ram_addr);
825 00f82b8a aurel32
826 00f82b8a aurel32
    /* above 4giga memory allocation */
827 00f82b8a aurel32
    if (above_4g_mem_size > 0) {
828 82b36dc3 aliguori
        ram_addr = qemu_ram_alloc(above_4g_mem_size);
829 82b36dc3 aliguori
        cpu_register_physical_memory(0x100000000ULL,
830 526ccb7a balrog
                                     above_4g_mem_size,
831 82b36dc3 aliguori
                                     ram_addr);
832 00f82b8a aurel32
    }
833 80cabfad bellard
834 82b36dc3 aliguori
835 970ac5a3 bellard
    /* allocate VGA RAM */
836 970ac5a3 bellard
    vga_ram_addr = qemu_ram_alloc(vga_ram_size);
837 7587cf44 bellard
838 970ac5a3 bellard
    /* BIOS load */
839 1192dad8 j_mayer
    if (bios_name == NULL)
840 1192dad8 j_mayer
        bios_name = BIOS_FILENAME;
841 1192dad8 j_mayer
    snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
842 7587cf44 bellard
    bios_size = get_image_size(buf);
843 5fafdf24 ths
    if (bios_size <= 0 ||
844 970ac5a3 bellard
        (bios_size % 65536) != 0) {
845 7587cf44 bellard
        goto bios_error;
846 7587cf44 bellard
    }
847 970ac5a3 bellard
    bios_offset = qemu_ram_alloc(bios_size);
848 7587cf44 bellard
    ret = load_image(buf, phys_ram_base + bios_offset);
849 7587cf44 bellard
    if (ret != bios_size) {
850 7587cf44 bellard
    bios_error:
851 970ac5a3 bellard
        fprintf(stderr, "qemu: could not load PC BIOS '%s'\n", buf);
852 80cabfad bellard
        exit(1);
853 80cabfad bellard
    }
854 7587cf44 bellard
855 c2b3b41a aliguori
    if (cirrus_vga_enabled || std_vga_enabled || vmsvga_enabled) {
856 c2b3b41a aliguori
        /* VGA BIOS load */
857 c2b3b41a aliguori
        if (cirrus_vga_enabled) {
858 c2b3b41a aliguori
            snprintf(buf, sizeof(buf), "%s/%s", bios_dir, VGABIOS_CIRRUS_FILENAME);
859 c2b3b41a aliguori
        } else {
860 c2b3b41a aliguori
            snprintf(buf, sizeof(buf), "%s/%s", bios_dir, VGABIOS_FILENAME);
861 c2b3b41a aliguori
        }
862 c2b3b41a aliguori
        vga_bios_size = get_image_size(buf);
863 c2b3b41a aliguori
        if (vga_bios_size <= 0 || vga_bios_size > 65536)
864 c2b3b41a aliguori
            goto vga_bios_error;
865 c2b3b41a aliguori
        vga_bios_offset = qemu_ram_alloc(65536);
866 c2b3b41a aliguori
867 c2b3b41a aliguori
        ret = load_image(buf, phys_ram_base + vga_bios_offset);
868 c2b3b41a aliguori
        if (ret != vga_bios_size) {
869 c2b3b41a aliguori
vga_bios_error:
870 c2b3b41a aliguori
            fprintf(stderr, "qemu: could not load VGA BIOS '%s'\n", buf);
871 c2b3b41a aliguori
            exit(1);
872 c2b3b41a aliguori
        }
873 970ac5a3 bellard
874 e9ebead2 aliguori
        /* setup basic memory access */
875 e9ebead2 aliguori
        cpu_register_physical_memory(0xc0000, 0x10000,
876 e9ebead2 aliguori
                                     vga_bios_offset | IO_MEM_ROM);
877 e9ebead2 aliguori
    }
878 7587cf44 bellard
879 7587cf44 bellard
    /* map the last 128KB of the BIOS in ISA space */
880 7587cf44 bellard
    isa_bios_size = bios_size;
881 7587cf44 bellard
    if (isa_bios_size > (128 * 1024))
882 7587cf44 bellard
        isa_bios_size = 128 * 1024;
883 5fafdf24 ths
    cpu_register_physical_memory(0x100000 - isa_bios_size,
884 5fafdf24 ths
                                 isa_bios_size,
885 7587cf44 bellard
                                 (bios_offset + bios_size - isa_bios_size) | IO_MEM_ROM);
886 9ae02555 ths
887 970ac5a3 bellard
    {
888 970ac5a3 bellard
        ram_addr_t option_rom_offset;
889 970ac5a3 bellard
        int size, offset;
890 970ac5a3 bellard
891 970ac5a3 bellard
        offset = 0;
892 4fc9af53 aliguori
        if (linux_boot) {
893 4fc9af53 aliguori
            option_rom_offset = qemu_ram_alloc(TARGET_PAGE_SIZE);
894 4fc9af53 aliguori
            load_linux(phys_ram_base + option_rom_offset,
895 4fc9af53 aliguori
                       kernel_filename, initrd_filename, kernel_cmdline);
896 4fc9af53 aliguori
            cpu_register_physical_memory(0xd0000, TARGET_PAGE_SIZE,
897 4fc9af53 aliguori
                                         option_rom_offset | IO_MEM_ROM);
898 4fc9af53 aliguori
            offset = TARGET_PAGE_SIZE;
899 4fc9af53 aliguori
        }
900 4fc9af53 aliguori
901 970ac5a3 bellard
        for (i = 0; i < nb_option_roms; i++) {
902 970ac5a3 bellard
            size = get_image_size(option_rom[i]);
903 970ac5a3 bellard
            if (size < 0) {
904 5fafdf24 ths
                fprintf(stderr, "Could not load option rom '%s'\n",
905 970ac5a3 bellard
                        option_rom[i]);
906 970ac5a3 bellard
                exit(1);
907 970ac5a3 bellard
            }
908 970ac5a3 bellard
            if (size > (0x10000 - offset))
909 970ac5a3 bellard
                goto option_rom_error;
910 970ac5a3 bellard
            option_rom_offset = qemu_ram_alloc(size);
911 970ac5a3 bellard
            ret = load_image(option_rom[i], phys_ram_base + option_rom_offset);
912 970ac5a3 bellard
            if (ret != size) {
913 970ac5a3 bellard
            option_rom_error:
914 970ac5a3 bellard
                fprintf(stderr, "Too many option ROMS\n");
915 970ac5a3 bellard
                exit(1);
916 970ac5a3 bellard
            }
917 970ac5a3 bellard
            size = (size + 4095) & ~4095;
918 970ac5a3 bellard
            cpu_register_physical_memory(0xd0000 + offset,
919 970ac5a3 bellard
                                         size, option_rom_offset | IO_MEM_ROM);
920 970ac5a3 bellard
            offset += size;
921 970ac5a3 bellard
        }
922 9ae02555 ths
    }
923 9ae02555 ths
924 7587cf44 bellard
    /* map all the bios at the top of memory */
925 5fafdf24 ths
    cpu_register_physical_memory((uint32_t)(-bios_size),
926 7587cf44 bellard
                                 bios_size, bios_offset | IO_MEM_ROM);
927 3b46e624 ths
928 80cabfad bellard
    bochs_bios_init();
929 80cabfad bellard
930 a5b38b51 aurel32
    cpu_irq = qemu_allocate_irqs(pic_irq_request, NULL, 1);
931 d537cf6c pbrook
    i8259 = i8259_init(cpu_irq[0]);
932 d537cf6c pbrook
    ferr_irq = i8259[13];
933 d537cf6c pbrook
934 69b91039 bellard
    if (pci_enabled) {
935 d537cf6c pbrook
        pci_bus = i440fx_init(&i440fx_state, i8259);
936 8f1c91d8 ths
        piix3_devfn = piix3_init(pci_bus, -1);
937 46e50e9d bellard
    } else {
938 46e50e9d bellard
        pci_bus = NULL;
939 69b91039 bellard
    }
940 69b91039 bellard
941 80cabfad bellard
    /* init basic PC hardware */
942 b41a2cd1 bellard
    register_ioport_write(0x80, 1, 1, ioport80_write, NULL);
943 80cabfad bellard
944 f929aad6 bellard
    register_ioport_write(0xf0, 1, 1, ioportF0_write, NULL);
945 f929aad6 bellard
946 1f04275e bellard
    if (cirrus_vga_enabled) {
947 1f04275e bellard
        if (pci_enabled) {
948 5fafdf24 ths
            pci_cirrus_vga_init(pci_bus,
949 3023f332 aliguori
                                phys_ram_base + vga_ram_addr,
950 970ac5a3 bellard
                                vga_ram_addr, vga_ram_size);
951 1f04275e bellard
        } else {
952 3023f332 aliguori
            isa_cirrus_vga_init(phys_ram_base + vga_ram_addr,
953 970ac5a3 bellard
                                vga_ram_addr, vga_ram_size);
954 1f04275e bellard
        }
955 d34cab9f ths
    } else if (vmsvga_enabled) {
956 d34cab9f ths
        if (pci_enabled)
957 3023f332 aliguori
            pci_vmsvga_init(pci_bus, phys_ram_base + vga_ram_addr,
958 45e4522e balrog
                            vga_ram_addr, vga_ram_size);
959 d34cab9f ths
        else
960 d34cab9f ths
            fprintf(stderr, "%s: vmware_vga: no PCI bus\n", __FUNCTION__);
961 c2b3b41a aliguori
    } else if (std_vga_enabled) {
962 89b6b508 bellard
        if (pci_enabled) {
963 3023f332 aliguori
            pci_vga_init(pci_bus, phys_ram_base + vga_ram_addr,
964 970ac5a3 bellard
                         vga_ram_addr, vga_ram_size, 0, 0);
965 89b6b508 bellard
        } else {
966 3023f332 aliguori
            isa_vga_init(phys_ram_base + vga_ram_addr,
967 970ac5a3 bellard
                         vga_ram_addr, vga_ram_size);
968 89b6b508 bellard
        }
969 1f04275e bellard
    }
970 80cabfad bellard
971 42fc73a1 aurel32
    rtc_state = rtc_init(0x70, i8259[8], 2000);
972 80cabfad bellard
973 3b4366de blueswir1
    qemu_register_boot_set(pc_boot_set, rtc_state);
974 3b4366de blueswir1
975 e1a23744 bellard
    register_ioport_read(0x92, 1, 1, ioport92_read, NULL);
976 e1a23744 bellard
    register_ioport_write(0x92, 1, 1, ioport92_write, NULL);
977 e1a23744 bellard
978 d592d303 bellard
    if (pci_enabled) {
979 d592d303 bellard
        ioapic = ioapic_init();
980 d592d303 bellard
    }
981 d537cf6c pbrook
    pit = pit_init(0x40, i8259[0]);
982 fd06c375 bellard
    pcspk_init(pit);
983 16b29ae1 aliguori
    if (!no_hpet) {
984 16b29ae1 aliguori
        hpet_init(i8259);
985 16b29ae1 aliguori
    }
986 d592d303 bellard
    if (pci_enabled) {
987 d592d303 bellard
        pic_set_alt_irq_func(isa_pic, ioapic_set_irq, ioapic);
988 d592d303 bellard
    }
989 b41a2cd1 bellard
990 8d11df9e bellard
    for(i = 0; i < MAX_SERIAL_PORTS; i++) {
991 8d11df9e bellard
        if (serial_hds[i]) {
992 b6cd0ea1 aurel32
            serial_init(serial_io[i], i8259[serial_irq[i]], 115200,
993 b6cd0ea1 aurel32
                        serial_hds[i]);
994 8d11df9e bellard
        }
995 8d11df9e bellard
    }
996 b41a2cd1 bellard
997 6508fe59 bellard
    for(i = 0; i < MAX_PARALLEL_PORTS; i++) {
998 6508fe59 bellard
        if (parallel_hds[i]) {
999 d537cf6c pbrook
            parallel_init(parallel_io[i], i8259[parallel_irq[i]],
1000 d537cf6c pbrook
                          parallel_hds[i]);
1001 6508fe59 bellard
        }
1002 6508fe59 bellard
    }
1003 6508fe59 bellard
1004 a41b2ff2 pbrook
    for(i = 0; i < nb_nics; i++) {
1005 cb457d76 aliguori
        NICInfo *nd = &nd_table[i];
1006 cb457d76 aliguori
1007 cb457d76 aliguori
        if (!pci_enabled || (nd->model && strcmp(nd->model, "ne2k_isa") == 0))
1008 d537cf6c pbrook
            pc_init_ne2k_isa(nd, i8259);
1009 cb457d76 aliguori
        else
1010 cb457d76 aliguori
            pci_nic_init(pci_bus, nd, -1, "ne2k_pci");
1011 a41b2ff2 pbrook
    }
1012 b41a2cd1 bellard
1013 5e3cb534 aliguori
    qemu_system_hot_add_init();
1014 5e3cb534 aliguori
1015 e4bcb14c ths
    if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) {
1016 e4bcb14c ths
        fprintf(stderr, "qemu: too many IDE bus\n");
1017 e4bcb14c ths
        exit(1);
1018 e4bcb14c ths
    }
1019 e4bcb14c ths
1020 e4bcb14c ths
    for(i = 0; i < MAX_IDE_BUS * MAX_IDE_DEVS; i++) {
1021 e4bcb14c ths
        index = drive_get_index(IF_IDE, i / MAX_IDE_DEVS, i % MAX_IDE_DEVS);
1022 e4bcb14c ths
        if (index != -1)
1023 e4bcb14c ths
            hd[i] = drives_table[index].bdrv;
1024 e4bcb14c ths
        else
1025 e4bcb14c ths
            hd[i] = NULL;
1026 e4bcb14c ths
    }
1027 e4bcb14c ths
1028 a41b2ff2 pbrook
    if (pci_enabled) {
1029 e4bcb14c ths
        pci_piix3_ide_init(pci_bus, hd, piix3_devfn + 1, i8259);
1030 a41b2ff2 pbrook
    } else {
1031 e4bcb14c ths
        for(i = 0; i < MAX_IDE_BUS; i++) {
1032 d537cf6c pbrook
            isa_ide_init(ide_iobase[i], ide_iobase2[i], i8259[ide_irq[i]],
1033 e4bcb14c ths
                         hd[MAX_IDE_DEVS * i], hd[MAX_IDE_DEVS * i + 1]);
1034 69b91039 bellard
        }
1035 b41a2cd1 bellard
    }
1036 69b91039 bellard
1037 d537cf6c pbrook
    i8042_init(i8259[1], i8259[12], 0x60);
1038 7c29d0c0 bellard
    DMA_init(0);
1039 6a36d84e bellard
#ifdef HAS_AUDIO
1040 d537cf6c pbrook
    audio_init(pci_enabled ? pci_bus : NULL, i8259);
1041 fb065187 bellard
#endif
1042 80cabfad bellard
1043 e4bcb14c ths
    for(i = 0; i < MAX_FD; i++) {
1044 e4bcb14c ths
        index = drive_get_index(IF_FLOPPY, 0, i);
1045 e4bcb14c ths
        if (index != -1)
1046 e4bcb14c ths
            fd[i] = drives_table[index].bdrv;
1047 e4bcb14c ths
        else
1048 e4bcb14c ths
            fd[i] = NULL;
1049 e4bcb14c ths
    }
1050 e4bcb14c ths
    floppy_controller = fdctrl_init(i8259[6], 2, 0, 0x3f0, fd);
1051 b41a2cd1 bellard
1052 00f82b8a aurel32
    cmos_init(below_4g_mem_size, above_4g_mem_size, boot_device, hd);
1053 69b91039 bellard
1054 bb36d470 bellard
    if (pci_enabled && usb_enabled) {
1055 afcc3cdf ths
        usb_uhci_piix3_init(pci_bus, piix3_devfn + 2);
1056 bb36d470 bellard
    }
1057 bb36d470 bellard
1058 6515b203 bellard
    if (pci_enabled && acpi_enabled) {
1059 3fffc223 ths
        uint8_t *eeprom_buf = qemu_mallocz(8 * 256); /* XXX: make this persistent */
1060 0ff596d0 pbrook
        i2c_bus *smbus;
1061 0ff596d0 pbrook
1062 0ff596d0 pbrook
        /* TODO: Populate SPD eeprom data.  */
1063 cf7a2fe2 aurel32
        smbus = piix4_pm_init(pci_bus, piix3_devfn + 3, 0xb100, i8259[9]);
1064 3fffc223 ths
        for (i = 0; i < 8; i++) {
1065 0ff596d0 pbrook
            smbus_eeprom_device_init(smbus, 0x50 + i, eeprom_buf + (i * 256));
1066 3fffc223 ths
        }
1067 6515b203 bellard
    }
1068 3b46e624 ths
1069 a5954d5c bellard
    if (i440fx_state) {
1070 a5954d5c bellard
        i440fx_init_memory_mappings(i440fx_state);
1071 a5954d5c bellard
    }
1072 e4bcb14c ths
1073 7d8406be pbrook
    if (pci_enabled) {
1074 e4bcb14c ths
        int max_bus;
1075 e4bcb14c ths
        int bus, unit;
1076 7d8406be pbrook
        void *scsi;
1077 96d30e48 ths
1078 e4bcb14c ths
        max_bus = drive_get_max_bus(IF_SCSI);
1079 e4bcb14c ths
1080 e4bcb14c ths
        for (bus = 0; bus <= max_bus; bus++) {
1081 e4bcb14c ths
            scsi = lsi_scsi_init(pci_bus, -1);
1082 e4bcb14c ths
            for (unit = 0; unit < LSI_MAX_DEVS; unit++) {
1083 e4bcb14c ths
                index = drive_get_index(IF_SCSI, bus, unit);
1084 e4bcb14c ths
                if (index == -1)
1085 e4bcb14c ths
                    continue;
1086 e4bcb14c ths
                lsi_scsi_attach(scsi, drives_table[index].bdrv, unit);
1087 e4bcb14c ths
            }
1088 e4bcb14c ths
        }
1089 7d8406be pbrook
    }
1090 6e02c38d aliguori
1091 6e02c38d aliguori
    /* Add virtio block devices */
1092 6e02c38d aliguori
    if (pci_enabled) {
1093 6e02c38d aliguori
        int index;
1094 6e02c38d aliguori
        int unit_id = 0;
1095 6e02c38d aliguori
1096 6e02c38d aliguori
        while ((index = drive_get_index(IF_VIRTIO, 0, unit_id)) != -1) {
1097 9b32d5a5 aliguori
            virtio_blk_init(pci_bus, drives_table[index].bdrv);
1098 6e02c38d aliguori
            unit_id++;
1099 6e02c38d aliguori
        }
1100 6e02c38d aliguori
    }
1101 bd322087 aliguori
1102 bd322087 aliguori
    /* Add virtio balloon device */
1103 bd322087 aliguori
    if (pci_enabled)
1104 bd322087 aliguori
        virtio_balloon_init(pci_bus);
1105 a2fa19f9 aliguori
1106 a2fa19f9 aliguori
    /* Add virtio console devices */
1107 a2fa19f9 aliguori
    if (pci_enabled) {
1108 a2fa19f9 aliguori
        for(i = 0; i < MAX_VIRTIO_CONSOLES; i++) {
1109 a2fa19f9 aliguori
            if (virtcon_hds[i])
1110 a2fa19f9 aliguori
                virtio_console_init(pci_bus, virtcon_hds[i]);
1111 a2fa19f9 aliguori
        }
1112 a2fa19f9 aliguori
    }
1113 80cabfad bellard
}
1114 b5ff2d6e bellard
1115 00f82b8a aurel32
static void pc_init_pci(ram_addr_t ram_size, int vga_ram_size,
1116 3023f332 aliguori
                        const char *boot_device,
1117 5fafdf24 ths
                        const char *kernel_filename,
1118 3dbbdc25 bellard
                        const char *kernel_cmdline,
1119 94fc95cd j_mayer
                        const char *initrd_filename,
1120 94fc95cd j_mayer
                        const char *cpu_model)
1121 3dbbdc25 bellard
{
1122 3023f332 aliguori
    pc_init1(ram_size, vga_ram_size, boot_device,
1123 3dbbdc25 bellard
             kernel_filename, kernel_cmdline,
1124 a049de61 bellard
             initrd_filename, 1, cpu_model);
1125 3dbbdc25 bellard
}
1126 3dbbdc25 bellard
1127 00f82b8a aurel32
static void pc_init_isa(ram_addr_t ram_size, int vga_ram_size,
1128 3023f332 aliguori
                        const char *boot_device,
1129 5fafdf24 ths
                        const char *kernel_filename,
1130 3dbbdc25 bellard
                        const char *kernel_cmdline,
1131 94fc95cd j_mayer
                        const char *initrd_filename,
1132 94fc95cd j_mayer
                        const char *cpu_model)
1133 3dbbdc25 bellard
{
1134 3023f332 aliguori
    pc_init1(ram_size, vga_ram_size, boot_device,
1135 3dbbdc25 bellard
             kernel_filename, kernel_cmdline,
1136 a049de61 bellard
             initrd_filename, 0, cpu_model);
1137 3dbbdc25 bellard
}
1138 3dbbdc25 bellard
1139 0bacd130 aliguori
/* set CMOS shutdown status register (index 0xF) as S3_resume(0xFE)
1140 0bacd130 aliguori
   BIOS will read it and start S3 resume at POST Entry */
1141 0bacd130 aliguori
void cmos_set_s3_resume(void)
1142 0bacd130 aliguori
{
1143 0bacd130 aliguori
    if (rtc_state)
1144 0bacd130 aliguori
        rtc_set_memory(rtc_state, 0xF, 0xFE);
1145 0bacd130 aliguori
}
1146 0bacd130 aliguori
1147 b5ff2d6e bellard
QEMUMachine pc_machine = {
1148 a245f2e7 aurel32
    .name = "pc",
1149 a245f2e7 aurel32
    .desc = "Standard PC",
1150 a245f2e7 aurel32
    .init = pc_init_pci,
1151 a245f2e7 aurel32
    .ram_require = VGA_RAM_SIZE + PC_MAX_BIOS_SIZE,
1152 b2097003 aliguori
    .max_cpus = 255,
1153 3dbbdc25 bellard
};
1154 3dbbdc25 bellard
1155 3dbbdc25 bellard
QEMUMachine isapc_machine = {
1156 a245f2e7 aurel32
    .name = "isapc",
1157 a245f2e7 aurel32
    .desc = "ISA-only PC",
1158 a245f2e7 aurel32
    .init = pc_init_isa,
1159 a245f2e7 aurel32
    .ram_require = VGA_RAM_SIZE + PC_MAX_BIOS_SIZE,
1160 b2097003 aliguori
    .max_cpus = 1,
1161 b5ff2d6e bellard
};