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/*
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* QEMU IDE Emulation: PCI Bus support.
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*
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* Copyright (c) 2003 Fabrice Bellard
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* Copyright (c) 2006 Openedhand Ltd.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include <hw/hw.h> |
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#include <hw/pc.h> |
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#include <hw/pci.h> |
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#include <hw/isa.h> |
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#include "block.h" |
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#include "block_int.h" |
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#include "sysemu.h" |
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#include "dma.h" |
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#include <hw/ide/internal.h> |
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/***********************************************************/
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/* PCI IDE definitions */
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/* CMD646 specific */
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#define MRDMODE 0x71 |
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#define MRDMODE_INTR_CH0 0x04 |
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#define MRDMODE_INTR_CH1 0x08 |
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#define MRDMODE_BLK_CH0 0x10 |
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#define MRDMODE_BLK_CH1 0x20 |
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#define UDIDETCR0 0x73 |
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#define UDIDETCR1 0x7B |
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|
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#define IDE_TYPE_PIIX3 0 |
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#define IDE_TYPE_CMD646 1 |
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#define IDE_TYPE_PIIX4 2 |
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typedef struct PCIIDEState { |
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PCIDevice dev; |
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IDEBus *bus[2];
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BMDMAState bmdma[2];
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int type; /* see IDE_TYPE_xxx */ |
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uint32_t secondary; |
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} PCIIDEState; |
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static void cmd646_update_irq(PCIIDEState *d); |
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static void ide_map(PCIDevice *pci_dev, int region_num, |
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uint32_t addr, uint32_t size, int type)
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{ |
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PCIIDEState *d = (PCIIDEState *)pci_dev; |
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IDEBus *bus; |
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if (region_num <= 3) { |
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bus = d->bus[(region_num >> 1)];
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if (region_num & 1) { |
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register_ioport_read(addr + 2, 1, 1, ide_status_read, bus); |
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register_ioport_write(addr + 2, 1, 1, ide_cmd_write, bus); |
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} else {
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register_ioport_write(addr, 8, 1, ide_ioport_write, bus); |
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register_ioport_read(addr, 8, 1, ide_ioport_read, bus); |
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/* data ports */
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register_ioport_write(addr, 2, 2, ide_data_writew, bus); |
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register_ioport_read(addr, 2, 2, ide_data_readw, bus); |
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register_ioport_write(addr, 4, 4, ide_data_writel, bus); |
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register_ioport_read(addr, 4, 4, ide_data_readl, bus); |
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} |
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} |
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} |
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static void bmdma_cmd_writeb(void *opaque, uint32_t addr, uint32_t val) |
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{ |
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BMDMAState *bm = opaque; |
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#ifdef DEBUG_IDE
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printf("%s: 0x%08x\n", __func__, val);
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#endif
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if (!(val & BM_CMD_START)) {
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/* XXX: do it better */
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ide_dma_cancel(bm); |
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bm->cmd = val & 0x09;
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} else {
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if (!(bm->status & BM_STATUS_DMAING)) {
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bm->status |= BM_STATUS_DMAING; |
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/* start dma transfer if possible */
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if (bm->dma_cb)
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bm->dma_cb(bm, 0);
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} |
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bm->cmd = val & 0x09;
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} |
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} |
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static uint32_t bmdma_readb(void *opaque, uint32_t addr) |
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{ |
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BMDMAState *bm = opaque; |
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PCIIDEState *pci_dev; |
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uint32_t val; |
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switch(addr & 3) { |
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case 0: |
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val = bm->cmd; |
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break;
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case 1: |
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pci_dev = bm->pci_dev; |
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if (pci_dev->type == IDE_TYPE_CMD646) {
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val = pci_dev->dev.config[MRDMODE]; |
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} else {
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val = 0xff;
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} |
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break;
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case 2: |
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val = bm->status; |
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break;
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case 3: |
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pci_dev = bm->pci_dev; |
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if (pci_dev->type == IDE_TYPE_CMD646) {
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if (bm == &pci_dev->bmdma[0]) |
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val = pci_dev->dev.config[UDIDETCR0]; |
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else
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val = pci_dev->dev.config[UDIDETCR1]; |
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} else {
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val = 0xff;
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} |
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break;
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default:
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val = 0xff;
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break;
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} |
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#ifdef DEBUG_IDE
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printf("bmdma: readb 0x%02x : 0x%02x\n", addr, val);
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#endif
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return val;
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} |
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static void bmdma_writeb(void *opaque, uint32_t addr, uint32_t val) |
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{ |
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BMDMAState *bm = opaque; |
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PCIIDEState *pci_dev; |
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#ifdef DEBUG_IDE
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printf("bmdma: writeb 0x%02x : 0x%02x\n", addr, val);
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#endif
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switch(addr & 3) { |
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case 1: |
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pci_dev = bm->pci_dev; |
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if (pci_dev->type == IDE_TYPE_CMD646) {
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pci_dev->dev.config[MRDMODE] = |
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(pci_dev->dev.config[MRDMODE] & ~0x30) | (val & 0x30); |
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cmd646_update_irq(pci_dev); |
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} |
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break;
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case 2: |
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bm->status = (val & 0x60) | (bm->status & 1) | (bm->status & ~val & 0x06); |
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break;
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case 3: |
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pci_dev = bm->pci_dev; |
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if (pci_dev->type == IDE_TYPE_CMD646) {
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if (bm == &pci_dev->bmdma[0]) |
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pci_dev->dev.config[UDIDETCR0] = val; |
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else
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pci_dev->dev.config[UDIDETCR1] = val; |
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} |
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break;
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} |
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} |
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static uint32_t bmdma_addr_readb(void *opaque, uint32_t addr) |
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{ |
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BMDMAState *bm = opaque; |
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uint32_t val; |
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val = (bm->addr >> ((addr & 3) * 8)) & 0xff; |
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#ifdef DEBUG_IDE
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printf("%s: 0x%08x\n", __func__, val);
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#endif
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return val;
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} |
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static void bmdma_addr_writeb(void *opaque, uint32_t addr, uint32_t val) |
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{ |
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BMDMAState *bm = opaque; |
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int shift = (addr & 3) * 8; |
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#ifdef DEBUG_IDE
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printf("%s: 0x%08x\n", __func__, val);
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#endif
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bm->addr &= ~(0xFF << shift);
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bm->addr |= ((val & 0xFF) << shift) & ~3; |
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bm->cur_addr = bm->addr; |
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} |
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static uint32_t bmdma_addr_readw(void *opaque, uint32_t addr) |
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{ |
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BMDMAState *bm = opaque; |
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uint32_t val; |
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val = (bm->addr >> ((addr & 3) * 8)) & 0xffff; |
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#ifdef DEBUG_IDE
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printf("%s: 0x%08x\n", __func__, val);
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#endif
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return val;
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} |
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static void bmdma_addr_writew(void *opaque, uint32_t addr, uint32_t val) |
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{ |
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BMDMAState *bm = opaque; |
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int shift = (addr & 3) * 8; |
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#ifdef DEBUG_IDE
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printf("%s: 0x%08x\n", __func__, val);
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#endif
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bm->addr &= ~(0xFFFF << shift);
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bm->addr |= ((val & 0xFFFF) << shift) & ~3; |
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bm->cur_addr = bm->addr; |
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} |
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static uint32_t bmdma_addr_readl(void *opaque, uint32_t addr) |
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{ |
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BMDMAState *bm = opaque; |
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uint32_t val; |
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val = bm->addr; |
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#ifdef DEBUG_IDE
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printf("%s: 0x%08x\n", __func__, val);
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#endif
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return val;
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} |
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static void bmdma_addr_writel(void *opaque, uint32_t addr, uint32_t val) |
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{ |
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BMDMAState *bm = opaque; |
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#ifdef DEBUG_IDE
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printf("%s: 0x%08x\n", __func__, val);
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#endif
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bm->addr = val & ~3;
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bm->cur_addr = bm->addr; |
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} |
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static void bmdma_map(PCIDevice *pci_dev, int region_num, |
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uint32_t addr, uint32_t size, int type)
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{ |
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PCIIDEState *d = (PCIIDEState *)pci_dev; |
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int i;
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for(i = 0;i < 2; i++) { |
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BMDMAState *bm = &d->bmdma[i]; |
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d->bus[i]->bmdma = bm; |
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bm->pci_dev = DO_UPCAST(PCIIDEState, dev, pci_dev); |
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bm->bus = d->bus[i]; |
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qemu_add_vm_change_state_handler(ide_dma_restart_cb, bm); |
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register_ioport_write(addr, 1, 1, bmdma_cmd_writeb, bm); |
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register_ioport_write(addr + 1, 3, 1, bmdma_writeb, bm); |
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register_ioport_read(addr, 4, 1, bmdma_readb, bm); |
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register_ioport_write(addr + 4, 4, 1, bmdma_addr_writeb, bm); |
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register_ioport_read(addr + 4, 4, 1, bmdma_addr_readb, bm); |
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register_ioport_write(addr + 4, 4, 2, bmdma_addr_writew, bm); |
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register_ioport_read(addr + 4, 4, 2, bmdma_addr_readw, bm); |
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register_ioport_write(addr + 4, 4, 4, bmdma_addr_writel, bm); |
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register_ioport_read(addr + 4, 4, 4, bmdma_addr_readl, bm); |
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addr += 8;
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} |
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} |
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static void pci_ide_save(QEMUFile* f, void *opaque) |
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{ |
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PCIIDEState *d = opaque; |
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int i;
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pci_device_save(&d->dev, f); |
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for(i = 0; i < 2; i++) { |
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BMDMAState *bm = &d->bmdma[i]; |
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uint8_t ifidx; |
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qemu_put_8s(f, &bm->cmd); |
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qemu_put_8s(f, &bm->status); |
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qemu_put_be32s(f, &bm->addr); |
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qemu_put_sbe64s(f, &bm->sector_num); |
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qemu_put_be32s(f, &bm->nsector); |
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ifidx = bm->unit + 2*i;
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qemu_put_8s(f, &ifidx); |
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/* XXX: if a transfer is pending, we do not save it yet */
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} |
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/* per IDE interface data */
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for(i = 0; i < 2; i++) { |
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idebus_save(f, d->bus[i]); |
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} |
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/* per IDE drive data */
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for(i = 0; i < 2; i++) { |
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ide_save(f, &d->bus[i]->ifs[0]);
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ide_save(f, &d->bus[i]->ifs[1]);
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} |
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} |
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static int pci_ide_load(QEMUFile* f, void *opaque, int version_id) |
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{ |
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PCIIDEState *d = opaque; |
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int ret, i;
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if (version_id != 2 && version_id != 3) |
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return -EINVAL;
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ret = pci_device_load(&d->dev, f); |
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if (ret < 0) |
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return ret;
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for(i = 0; i < 2; i++) { |
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BMDMAState *bm = &d->bmdma[i]; |
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uint8_t ifidx; |
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qemu_get_8s(f, &bm->cmd); |
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qemu_get_8s(f, &bm->status); |
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qemu_get_be32s(f, &bm->addr); |
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qemu_get_sbe64s(f, &bm->sector_num); |
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qemu_get_be32s(f, &bm->nsector); |
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qemu_get_8s(f, &ifidx); |
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bm->unit = ifidx & 1;
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/* XXX: if a transfer is pending, we do not save it yet */
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} |
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|
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/* per IDE interface data */
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for(i = 0; i < 2; i++) { |
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idebus_load(f, d->bus[i], version_id); |
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} |
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|
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/* per IDE drive data */
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for(i = 0; i < 2; i++) { |
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ide_load(f, &d->bus[i]->ifs[0], version_id);
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ide_load(f, &d->bus[i]->ifs[1], version_id);
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} |
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return 0; |
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} |
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|
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static void pci_ide_create_devs(PCIDevice *dev, DriveInfo **hd_table) |
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{ |
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PCIIDEState *d = DO_UPCAST(PCIIDEState, dev, dev); |
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static const int bus[4] = { 0, 0, 1, 1 }; |
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static const int unit[4] = { 0, 1, 0, 1 }; |
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int i;
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|
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for (i = 0; i < 4; i++) { |
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if (hd_table[i] == NULL) |
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continue;
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ide_create_drive(d->bus[bus[i]], unit[i], hd_table[i]); |
355 |
} |
356 |
} |
357 |
|
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/* XXX: call it also when the MRDMODE is changed from the PCI config
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registers */
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static void cmd646_update_irq(PCIIDEState *d) |
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{ |
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int pci_level;
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pci_level = ((d->dev.config[MRDMODE] & MRDMODE_INTR_CH0) && |
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!(d->dev.config[MRDMODE] & MRDMODE_BLK_CH0)) || |
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((d->dev.config[MRDMODE] & MRDMODE_INTR_CH1) && |
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!(d->dev.config[MRDMODE] & MRDMODE_BLK_CH1)); |
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qemu_set_irq(d->dev.irq[0], pci_level);
|
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} |
369 |
|
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/* the PCI irq level is the logical OR of the two channels */
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static void cmd646_set_irq(void *opaque, int channel, int level) |
372 |
{ |
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PCIIDEState *d = opaque; |
374 |
int irq_mask;
|
375 |
|
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irq_mask = MRDMODE_INTR_CH0 << channel; |
377 |
if (level)
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d->dev.config[MRDMODE] |= irq_mask; |
379 |
else
|
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d->dev.config[MRDMODE] &= ~irq_mask; |
381 |
cmd646_update_irq(d); |
382 |
} |
383 |
|
384 |
static void cmd646_reset(void *opaque) |
385 |
{ |
386 |
PCIIDEState *d = opaque; |
387 |
unsigned int i; |
388 |
|
389 |
for (i = 0; i < 2; i++) |
390 |
ide_dma_cancel(&d->bmdma[i]); |
391 |
} |
392 |
|
393 |
/* CMD646 PCI IDE controller */
|
394 |
static int pci_cmd646_ide_initfn(PCIDevice *dev) |
395 |
{ |
396 |
PCIIDEState *d = DO_UPCAST(PCIIDEState, dev, dev); |
397 |
uint8_t *pci_conf = d->dev.config; |
398 |
qemu_irq *irq; |
399 |
|
400 |
d->type = IDE_TYPE_CMD646; |
401 |
pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_CMD); |
402 |
pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_CMD_646); |
403 |
|
404 |
pci_conf[0x08] = 0x07; // IDE controller revision |
405 |
pci_conf[0x09] = 0x8f; |
406 |
|
407 |
pci_config_set_class(pci_conf, PCI_CLASS_STORAGE_IDE); |
408 |
pci_conf[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
|
409 |
|
410 |
pci_conf[0x51] = 0x04; // enable IDE0 |
411 |
if (d->secondary) {
|
412 |
/* XXX: if not enabled, really disable the seconday IDE controller */
|
413 |
pci_conf[0x51] |= 0x08; /* enable IDE1 */ |
414 |
} |
415 |
|
416 |
pci_register_bar((PCIDevice *)d, 0, 0x8, |
417 |
PCI_ADDRESS_SPACE_IO, ide_map); |
418 |
pci_register_bar((PCIDevice *)d, 1, 0x4, |
419 |
PCI_ADDRESS_SPACE_IO, ide_map); |
420 |
pci_register_bar((PCIDevice *)d, 2, 0x8, |
421 |
PCI_ADDRESS_SPACE_IO, ide_map); |
422 |
pci_register_bar((PCIDevice *)d, 3, 0x4, |
423 |
PCI_ADDRESS_SPACE_IO, ide_map); |
424 |
pci_register_bar((PCIDevice *)d, 4, 0x10, |
425 |
PCI_ADDRESS_SPACE_IO, bmdma_map); |
426 |
|
427 |
pci_conf[0x3d] = 0x01; // interrupt on pin 1 |
428 |
|
429 |
irq = qemu_allocate_irqs(cmd646_set_irq, d, 2);
|
430 |
d->bus[0] = ide_bus_new(&d->dev.qdev);
|
431 |
d->bus[1] = ide_bus_new(&d->dev.qdev);
|
432 |
ide_init2(d->bus[0], NULL, NULL, irq[0]); |
433 |
ide_init2(d->bus[1], NULL, NULL, irq[1]); |
434 |
|
435 |
register_savevm("ide", 0, 3, pci_ide_save, pci_ide_load, d); |
436 |
qemu_register_reset(cmd646_reset, d); |
437 |
cmd646_reset(d); |
438 |
return 0; |
439 |
} |
440 |
|
441 |
void pci_cmd646_ide_init(PCIBus *bus, DriveInfo **hd_table,
|
442 |
int secondary_ide_enabled)
|
443 |
{ |
444 |
PCIDevice *dev; |
445 |
|
446 |
dev = pci_create_noinit(bus, -1, "CMD646 IDE"); |
447 |
qdev_prop_set_uint32(&dev->qdev, "secondary", secondary_ide_enabled);
|
448 |
qdev_init(&dev->qdev); |
449 |
|
450 |
pci_ide_create_devs(dev, hd_table); |
451 |
} |
452 |
|
453 |
static void piix3_reset(void *opaque) |
454 |
{ |
455 |
PCIIDEState *d = opaque; |
456 |
uint8_t *pci_conf = d->dev.config; |
457 |
int i;
|
458 |
|
459 |
for (i = 0; i < 2; i++) |
460 |
ide_dma_cancel(&d->bmdma[i]); |
461 |
|
462 |
pci_conf[0x04] = 0x00; |
463 |
pci_conf[0x05] = 0x00; |
464 |
pci_conf[0x06] = 0x80; /* FBC */ |
465 |
pci_conf[0x07] = 0x02; // PCI_status_devsel_medium |
466 |
pci_conf[0x20] = 0x01; /* BMIBA: 20-23h */ |
467 |
} |
468 |
|
469 |
static int pci_piix_ide_initfn(PCIIDEState *d) |
470 |
{ |
471 |
uint8_t *pci_conf = d->dev.config; |
472 |
|
473 |
pci_conf[0x09] = 0x80; // legacy ATA mode |
474 |
pci_config_set_class(pci_conf, PCI_CLASS_STORAGE_IDE); |
475 |
pci_conf[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
|
476 |
|
477 |
qemu_register_reset(piix3_reset, d); |
478 |
piix3_reset(d); |
479 |
|
480 |
pci_register_bar((PCIDevice *)d, 4, 0x10, |
481 |
PCI_ADDRESS_SPACE_IO, bmdma_map); |
482 |
|
483 |
register_savevm("ide", 0, 3, pci_ide_save, pci_ide_load, d); |
484 |
|
485 |
d->bus[0] = ide_bus_new(&d->dev.qdev);
|
486 |
d->bus[1] = ide_bus_new(&d->dev.qdev);
|
487 |
ide_init_ioport(d->bus[0], 0x1f0, 0x3f6); |
488 |
ide_init_ioport(d->bus[1], 0x170, 0x376); |
489 |
|
490 |
ide_init2(d->bus[0], NULL, NULL, isa_reserve_irq(14)); |
491 |
ide_init2(d->bus[1], NULL, NULL, isa_reserve_irq(15)); |
492 |
return 0; |
493 |
} |
494 |
|
495 |
static int pci_piix3_ide_initfn(PCIDevice *dev) |
496 |
{ |
497 |
PCIIDEState *d = DO_UPCAST(PCIIDEState, dev, dev); |
498 |
|
499 |
d->type = IDE_TYPE_PIIX3; |
500 |
pci_config_set_vendor_id(d->dev.config, PCI_VENDOR_ID_INTEL); |
501 |
pci_config_set_device_id(d->dev.config, PCI_DEVICE_ID_INTEL_82371SB_1); |
502 |
return pci_piix_ide_initfn(d);
|
503 |
} |
504 |
|
505 |
static int pci_piix4_ide_initfn(PCIDevice *dev) |
506 |
{ |
507 |
PCIIDEState *d = DO_UPCAST(PCIIDEState, dev, dev); |
508 |
|
509 |
d->type = IDE_TYPE_PIIX4; |
510 |
pci_config_set_vendor_id(d->dev.config, PCI_VENDOR_ID_INTEL); |
511 |
pci_config_set_device_id(d->dev.config, PCI_DEVICE_ID_INTEL_82371AB); |
512 |
return pci_piix_ide_initfn(d);
|
513 |
} |
514 |
|
515 |
/* hd_table must contain 4 block drivers */
|
516 |
/* NOTE: for the PIIX3, the IRQs and IOports are hardcoded */
|
517 |
void pci_piix3_ide_init(PCIBus *bus, DriveInfo **hd_table, int devfn) |
518 |
{ |
519 |
PCIDevice *dev; |
520 |
|
521 |
dev = pci_create_simple(bus, devfn, "PIIX3 IDE");
|
522 |
pci_ide_create_devs(dev, hd_table); |
523 |
} |
524 |
|
525 |
/* hd_table must contain 4 block drivers */
|
526 |
/* NOTE: for the PIIX4, the IRQs and IOports are hardcoded */
|
527 |
void pci_piix4_ide_init(PCIBus *bus, DriveInfo **hd_table, int devfn) |
528 |
{ |
529 |
PCIDevice *dev; |
530 |
|
531 |
dev = pci_create_simple(bus, devfn, "PIIX4 IDE");
|
532 |
pci_ide_create_devs(dev, hd_table); |
533 |
} |
534 |
|
535 |
static PCIDeviceInfo piix_ide_info[] = {
|
536 |
{ |
537 |
.qdev.name = "PIIX3 IDE",
|
538 |
.qdev.size = sizeof(PCIIDEState),
|
539 |
.init = pci_piix3_ide_initfn, |
540 |
},{ |
541 |
.qdev.name = "PIIX4 IDE",
|
542 |
.qdev.size = sizeof(PCIIDEState),
|
543 |
.init = pci_piix4_ide_initfn, |
544 |
},{ |
545 |
.qdev.name = "CMD646 IDE",
|
546 |
.qdev.size = sizeof(PCIIDEState),
|
547 |
.init = pci_cmd646_ide_initfn, |
548 |
.qdev.props = (Property[]) { |
549 |
DEFINE_PROP_UINT32("secondary", PCIIDEState, secondary, 0), |
550 |
DEFINE_PROP_END_OF_LIST(), |
551 |
}, |
552 |
},{ |
553 |
/* end of list */
|
554 |
} |
555 |
}; |
556 |
|
557 |
static void piix_ide_register(void) |
558 |
{ |
559 |
pci_qdev_register_many(piix_ide_info); |
560 |
} |
561 |
device_init(piix_ide_register); |