Revision 6f4cbd39 hw/pci.h

b/hw/pci.h
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#define PCI_MIN_GNT		0x3e	/* 8 bits */
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#define PCI_MAX_LAT		0x3f	/* 8 bits */
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/* Capability lists */
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#define PCI_CAP_LIST_ID		0	/* Capability ID */
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#define PCI_CAP_LIST_NEXT	1	/* Next capability in the list */
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#define PCI_REVISION            0x08    /* obsolete, use PCI_REVISION_ID */
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#define PCI_SUBVENDOR_ID        0x2c    /* obsolete, use PCI_SUBSYSTEM_VENDOR_ID */
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#define PCI_SUBDEVICE_ID        0x2e    /* obsolete, use PCI_SUBSYSTEM_ID */
......
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/* Bits in the PCI Status Register (PCI 2.3 spec) */
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#define PCI_STATUS_RESERVED1	0x007
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#define PCI_STATUS_INT_STATUS	0x008
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#define PCI_STATUS_CAPABILITIES	0x010
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#define PCI_STATUS_CAP_LIST	0x010
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#define PCI_STATUS_66MHZ	0x020
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#define PCI_STATUS_RESERVED2	0x040
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#define PCI_STATUS_FAST_BACK	0x080
......
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    /* Used to implement R/W bytes */
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    uint8_t wmask[PCI_CONFIG_SPACE_SIZE];
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    /* Used to allocate config space for capabilities. */
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    uint8_t used[PCI_CONFIG_SPACE_SIZE];
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    /* the following fields are read only */
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    PCIBus *bus;
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    int devfn;
......
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                            uint32_t size, int type,
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                            PCIMapIORegionFunc *map_func);
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int pci_add_capability(PCIDevice *pci_dev, uint8_t cap_id, uint8_t cap_size);
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void pci_del_capability(PCIDevice *pci_dev, uint8_t cap_id, uint8_t cap_size);
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void pci_reserve_capability(PCIDevice *pci_dev, uint8_t offset, uint8_t size);
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uint8_t pci_find_capability(PCIDevice *pci_dev, uint8_t cap_id);
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uint32_t pci_default_read_config(PCIDevice *d,
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                                 uint32_t address, int len);
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void pci_default_write_config(PCIDevice *d,

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