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/*
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* QEMU PCI bus manager
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*
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* Copyright (c) 2004 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "hw.h" |
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#include "pci.h" |
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#include "monitor.h" |
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#include "net.h" |
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#include "sysemu.h" |
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//#define DEBUG_PCI
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|
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struct PCIBus {
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BusState qbus; |
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int bus_num;
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int devfn_min;
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pci_set_irq_fn set_irq; |
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pci_map_irq_fn map_irq; |
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uint32_t config_reg; /* XXX: suppress */
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/* low level pic */
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SetIRQFunc *low_set_irq; |
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qemu_irq *irq_opaque; |
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PCIDevice *devices[256];
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PCIDevice *parent_dev; |
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PCIBus *next; |
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/* The bus IRQ state is the logical OR of the connected devices.
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Keep a count of the number of devices with raised IRQs. */
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int nirq;
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int irq_count[];
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}; |
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static void pci_update_mappings(PCIDevice *d); |
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static void pci_set_irq(void *opaque, int irq_num, int level); |
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|
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target_phys_addr_t pci_mem_base; |
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static uint16_t pci_default_sub_vendor_id = PCI_SUBVENDOR_ID_REDHAT_QUMRANET;
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static uint16_t pci_default_sub_device_id = PCI_SUBDEVICE_ID_QEMU;
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static PCIBus *first_bus;
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|
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static void pcibus_save(QEMUFile *f, void *opaque) |
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{ |
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PCIBus *bus = (PCIBus *)opaque; |
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int i;
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|
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qemu_put_be32(f, bus->nirq); |
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for (i = 0; i < bus->nirq; i++) |
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qemu_put_be32(f, bus->irq_count[i]); |
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} |
68 |
|
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static int pcibus_load(QEMUFile *f, void *opaque, int version_id) |
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{ |
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PCIBus *bus = (PCIBus *)opaque; |
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int i, nirq;
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|
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if (version_id != 1) |
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return -EINVAL;
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|
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nirq = qemu_get_be32(f); |
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if (bus->nirq != nirq) {
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fprintf(stderr, "pcibus_load: nirq mismatch: src=%d dst=%d\n",
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nirq, bus->nirq); |
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return -EINVAL;
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} |
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|
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for (i = 0; i < nirq; i++) |
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bus->irq_count[i] = qemu_get_be32(f); |
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|
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return 0; |
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} |
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static void pci_bus_reset(void *opaque) |
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{ |
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PCIBus *bus = (PCIBus *)opaque; |
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int i;
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|
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for (i = 0; i < bus->nirq; i++) { |
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bus->irq_count[i] = 0;
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} |
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for (i = 0; i < 256; i++) { |
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if (bus->devices[i])
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memset(bus->devices[i]->irq_state, 0,
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sizeof(bus->devices[i]->irq_state));
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} |
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} |
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|
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PCIBus *pci_register_bus(DeviceState *parent, const char *name, |
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pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, |
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qemu_irq *pic, int devfn_min, int nirq) |
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{ |
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PCIBus *bus; |
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static int nbus = 0; |
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|
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bus = FROM_QBUS(PCIBus, qbus_create(BUS_TYPE_PCI, |
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sizeof(PCIBus) + (nirq * sizeof(int)), |
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parent, name)); |
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bus->set_irq = set_irq; |
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bus->map_irq = map_irq; |
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bus->irq_opaque = pic; |
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bus->devfn_min = devfn_min; |
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bus->nirq = nirq; |
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bus->next = first_bus; |
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first_bus = bus; |
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register_savevm("PCIBUS", nbus++, 1, pcibus_save, pcibus_load, bus); |
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qemu_register_reset(pci_bus_reset, 0, bus);
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return bus;
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} |
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static PCIBus *pci_register_secondary_bus(PCIDevice *dev, pci_map_irq_fn map_irq)
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{ |
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PCIBus *bus; |
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bus = qemu_mallocz(sizeof(PCIBus));
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bus->map_irq = map_irq; |
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bus->parent_dev = dev; |
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bus->next = dev->bus->next; |
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dev->bus->next = bus; |
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return bus;
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} |
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int pci_bus_num(PCIBus *s)
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{ |
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return s->bus_num;
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} |
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void pci_device_save(PCIDevice *s, QEMUFile *f)
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{ |
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int i;
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qemu_put_be32(f, 2); /* PCI device version */ |
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qemu_put_buffer(f, s->config, 256);
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for (i = 0; i < 4; i++) |
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qemu_put_be32(f, s->irq_state[i]); |
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} |
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int pci_device_load(PCIDevice *s, QEMUFile *f)
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{ |
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uint32_t version_id; |
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int i;
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version_id = qemu_get_be32(f); |
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if (version_id > 2) |
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return -EINVAL;
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qemu_get_buffer(f, s->config, 256);
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pci_update_mappings(s); |
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if (version_id >= 2) |
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for (i = 0; i < 4; i ++) |
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s->irq_state[i] = qemu_get_be32(f); |
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return 0; |
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} |
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static int pci_set_default_subsystem_id(PCIDevice *pci_dev) |
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{ |
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uint16_t *id; |
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id = (void*)(&pci_dev->config[PCI_SUBVENDOR_ID]);
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id[0] = cpu_to_le16(pci_default_sub_vendor_id);
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id[1] = cpu_to_le16(pci_default_sub_device_id);
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return 0; |
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} |
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/*
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* Parse [[<domain>:]<bus>:]<slot>, return -1 on error
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*/
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static int pci_parse_devaddr(const char *addr, int *domp, int *busp, unsigned *slotp) |
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{ |
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const char *p; |
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char *e;
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unsigned long val; |
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unsigned long dom = 0, bus = 0; |
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unsigned slot = 0; |
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p = addr; |
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val = strtoul(p, &e, 16);
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if (e == p)
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return -1; |
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if (*e == ':') { |
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bus = val; |
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p = e + 1;
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val = strtoul(p, &e, 16);
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if (e == p)
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return -1; |
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if (*e == ':') { |
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dom = bus; |
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bus = val; |
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p = e + 1;
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val = strtoul(p, &e, 16);
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if (e == p)
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return -1; |
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} |
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} |
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if (dom > 0xffff || bus > 0xff || val > 0x1f) |
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return -1; |
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slot = val; |
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if (*e)
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return -1; |
218 |
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/* Note: QEMU doesn't implement domains other than 0 */
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if (dom != 0 || pci_find_bus(bus) == NULL) |
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return -1; |
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*domp = dom; |
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*busp = bus; |
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*slotp = slot; |
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return 0; |
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} |
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int pci_read_devaddr(const char *addr, int *domp, int *busp, unsigned *slotp) |
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{ |
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char devaddr[32]; |
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if (!get_param_value(devaddr, sizeof(devaddr), "pci_addr", addr)) |
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return -1; |
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return pci_parse_devaddr(devaddr, domp, busp, slotp);
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} |
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static PCIBus *pci_get_bus_devfn(int *devfnp, const char *devaddr) |
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{ |
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int dom, bus;
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unsigned slot;
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if (!devaddr) {
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*devfnp = -1;
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return pci_find_bus(0); |
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} |
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if (pci_parse_devaddr(devaddr, &dom, &bus, &slot) < 0) { |
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return NULL; |
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} |
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*devfnp = slot << 3;
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return pci_find_bus(bus);
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} |
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static void pci_init_wmask(PCIDevice *dev) |
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{ |
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int i;
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dev->wmask[PCI_CACHE_LINE_SIZE] = 0xff;
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dev->wmask[PCI_INTERRUPT_LINE] = 0xff;
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dev->wmask[PCI_COMMAND] = PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
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| PCI_COMMAND_MASTER; |
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for (i = PCI_CONFIG_HEADER_SIZE; i < PCI_CONFIG_SPACE_SIZE; ++i)
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dev->wmask[i] = 0xff;
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} |
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/* -1 for devfn means auto assign */
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static PCIDevice *do_pci_register_device(PCIDevice *pci_dev, PCIBus *bus,
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const char *name, int devfn, |
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PCIConfigReadFunc *config_read, |
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PCIConfigWriteFunc *config_write) |
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{ |
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if (devfn < 0) { |
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for(devfn = bus->devfn_min ; devfn < 256; devfn += 8) { |
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if (!bus->devices[devfn])
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goto found;
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} |
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return NULL; |
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found: ;
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} else if (bus->devices[devfn]) { |
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return NULL; |
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} |
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pci_dev->bus = bus; |
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pci_dev->devfn = devfn; |
286 |
pstrcpy(pci_dev->name, sizeof(pci_dev->name), name);
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memset(pci_dev->irq_state, 0, sizeof(pci_dev->irq_state)); |
288 |
pci_set_default_subsystem_id(pci_dev); |
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pci_init_wmask(pci_dev); |
290 |
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if (!config_read)
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config_read = pci_default_read_config; |
293 |
if (!config_write)
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config_write = pci_default_write_config; |
295 |
pci_dev->config_read = config_read; |
296 |
pci_dev->config_write = config_write; |
297 |
bus->devices[devfn] = pci_dev; |
298 |
pci_dev->irq = qemu_allocate_irqs(pci_set_irq, pci_dev, 4);
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return pci_dev;
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} |
301 |
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PCIDevice *pci_register_device(PCIBus *bus, const char *name, |
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int instance_size, int devfn, |
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PCIConfigReadFunc *config_read, |
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PCIConfigWriteFunc *config_write) |
306 |
{ |
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PCIDevice *pci_dev; |
308 |
|
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pci_dev = qemu_mallocz(instance_size); |
310 |
pci_dev = do_pci_register_device(pci_dev, bus, name, devfn, |
311 |
config_read, config_write); |
312 |
return pci_dev;
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} |
314 |
static target_phys_addr_t pci_to_cpu_addr(target_phys_addr_t addr)
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{ |
316 |
return addr + pci_mem_base;
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317 |
} |
318 |
|
319 |
static void pci_unregister_io_regions(PCIDevice *pci_dev) |
320 |
{ |
321 |
PCIIORegion *r; |
322 |
int i;
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323 |
|
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for(i = 0; i < PCI_NUM_REGIONS; i++) { |
325 |
r = &pci_dev->io_regions[i]; |
326 |
if (!r->size || r->addr == -1) |
327 |
continue;
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if (r->type == PCI_ADDRESS_SPACE_IO) {
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isa_unassign_ioport(r->addr, r->size); |
330 |
} else {
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cpu_register_physical_memory(pci_to_cpu_addr(r->addr), |
332 |
r->size, |
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IO_MEM_UNASSIGNED); |
334 |
} |
335 |
} |
336 |
} |
337 |
|
338 |
int pci_unregister_device(PCIDevice *pci_dev)
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339 |
{ |
340 |
int ret = 0; |
341 |
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342 |
if (pci_dev->unregister)
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343 |
ret = pci_dev->unregister(pci_dev); |
344 |
if (ret)
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345 |
return ret;
|
346 |
|
347 |
pci_unregister_io_regions(pci_dev); |
348 |
|
349 |
qemu_free_irqs(pci_dev->irq); |
350 |
pci_dev->bus->devices[pci_dev->devfn] = NULL;
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351 |
qdev_free(&pci_dev->qdev); |
352 |
return 0; |
353 |
} |
354 |
|
355 |
void pci_register_bar(PCIDevice *pci_dev, int region_num, |
356 |
uint32_t size, int type,
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357 |
PCIMapIORegionFunc *map_func) |
358 |
{ |
359 |
PCIIORegion *r; |
360 |
uint32_t addr; |
361 |
uint32_t wmask; |
362 |
|
363 |
if ((unsigned int)region_num >= PCI_NUM_REGIONS) |
364 |
return;
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365 |
|
366 |
if (size & (size-1)) { |
367 |
fprintf(stderr, "ERROR: PCI region size must be pow2 "
|
368 |
"type=0x%x, size=0x%x\n", type, size);
|
369 |
exit(1);
|
370 |
} |
371 |
|
372 |
r = &pci_dev->io_regions[region_num]; |
373 |
r->addr = -1;
|
374 |
r->size = size; |
375 |
r->type = type; |
376 |
r->map_func = map_func; |
377 |
|
378 |
wmask = ~(size - 1);
|
379 |
if (region_num == PCI_ROM_SLOT) {
|
380 |
addr = 0x30;
|
381 |
/* ROM enable bit is writeable */
|
382 |
wmask |= 1;
|
383 |
} else {
|
384 |
addr = 0x10 + region_num * 4; |
385 |
} |
386 |
*(uint32_t *)(pci_dev->config + addr) = cpu_to_le32(type); |
387 |
*(uint32_t *)(pci_dev->wmask + addr) = cpu_to_le32(wmask); |
388 |
} |
389 |
|
390 |
static void pci_update_mappings(PCIDevice *d) |
391 |
{ |
392 |
PCIIORegion *r; |
393 |
int cmd, i;
|
394 |
uint32_t last_addr, new_addr, config_ofs; |
395 |
|
396 |
cmd = le16_to_cpu(*(uint16_t *)(d->config + PCI_COMMAND)); |
397 |
for(i = 0; i < PCI_NUM_REGIONS; i++) { |
398 |
r = &d->io_regions[i]; |
399 |
if (i == PCI_ROM_SLOT) {
|
400 |
config_ofs = 0x30;
|
401 |
} else {
|
402 |
config_ofs = 0x10 + i * 4; |
403 |
} |
404 |
if (r->size != 0) { |
405 |
if (r->type & PCI_ADDRESS_SPACE_IO) {
|
406 |
if (cmd & PCI_COMMAND_IO) {
|
407 |
new_addr = le32_to_cpu(*(uint32_t *)(d->config + |
408 |
config_ofs)); |
409 |
new_addr = new_addr & ~(r->size - 1);
|
410 |
last_addr = new_addr + r->size - 1;
|
411 |
/* NOTE: we have only 64K ioports on PC */
|
412 |
if (last_addr <= new_addr || new_addr == 0 || |
413 |
last_addr >= 0x10000) {
|
414 |
new_addr = -1;
|
415 |
} |
416 |
} else {
|
417 |
new_addr = -1;
|
418 |
} |
419 |
} else {
|
420 |
if (cmd & PCI_COMMAND_MEMORY) {
|
421 |
new_addr = le32_to_cpu(*(uint32_t *)(d->config + |
422 |
config_ofs)); |
423 |
/* the ROM slot has a specific enable bit */
|
424 |
if (i == PCI_ROM_SLOT && !(new_addr & 1)) |
425 |
goto no_mem_map;
|
426 |
new_addr = new_addr & ~(r->size - 1);
|
427 |
last_addr = new_addr + r->size - 1;
|
428 |
/* NOTE: we do not support wrapping */
|
429 |
/* XXX: as we cannot support really dynamic
|
430 |
mappings, we handle specific values as invalid
|
431 |
mappings. */
|
432 |
if (last_addr <= new_addr || new_addr == 0 || |
433 |
last_addr == -1) {
|
434 |
new_addr = -1;
|
435 |
} |
436 |
} else {
|
437 |
no_mem_map:
|
438 |
new_addr = -1;
|
439 |
} |
440 |
} |
441 |
/* now do the real mapping */
|
442 |
if (new_addr != r->addr) {
|
443 |
if (r->addr != -1) { |
444 |
if (r->type & PCI_ADDRESS_SPACE_IO) {
|
445 |
int class;
|
446 |
/* NOTE: specific hack for IDE in PC case:
|
447 |
only one byte must be mapped. */
|
448 |
class = d->config[0x0a] | (d->config[0x0b] << 8); |
449 |
if (class == 0x0101 && r->size == 4) { |
450 |
isa_unassign_ioport(r->addr + 2, 1); |
451 |
} else {
|
452 |
isa_unassign_ioport(r->addr, r->size); |
453 |
} |
454 |
} else {
|
455 |
cpu_register_physical_memory(pci_to_cpu_addr(r->addr), |
456 |
r->size, |
457 |
IO_MEM_UNASSIGNED); |
458 |
qemu_unregister_coalesced_mmio(r->addr, r->size); |
459 |
} |
460 |
} |
461 |
r->addr = new_addr; |
462 |
if (r->addr != -1) { |
463 |
r->map_func(d, i, r->addr, r->size, r->type); |
464 |
} |
465 |
} |
466 |
} |
467 |
} |
468 |
} |
469 |
|
470 |
uint32_t pci_default_read_config(PCIDevice *d, |
471 |
uint32_t address, int len)
|
472 |
{ |
473 |
uint32_t val; |
474 |
|
475 |
switch(len) {
|
476 |
default:
|
477 |
case 4: |
478 |
if (address <= 0xfc) { |
479 |
val = le32_to_cpu(*(uint32_t *)(d->config + address)); |
480 |
break;
|
481 |
} |
482 |
/* fall through */
|
483 |
case 2: |
484 |
if (address <= 0xfe) { |
485 |
val = le16_to_cpu(*(uint16_t *)(d->config + address)); |
486 |
break;
|
487 |
} |
488 |
/* fall through */
|
489 |
case 1: |
490 |
val = d->config[address]; |
491 |
break;
|
492 |
} |
493 |
return val;
|
494 |
} |
495 |
|
496 |
void pci_default_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int l) |
497 |
{ |
498 |
uint8_t orig[PCI_CONFIG_SPACE_SIZE]; |
499 |
int i;
|
500 |
|
501 |
/* not efficient, but simple */
|
502 |
memcpy(orig, d->config, PCI_CONFIG_SPACE_SIZE); |
503 |
for(i = 0; i < l && addr < PCI_CONFIG_SPACE_SIZE; val >>= 8, ++i, ++addr) { |
504 |
uint8_t wmask = d->wmask[addr]; |
505 |
d->config[addr] = (d->config[addr] & ~wmask) | (val & wmask); |
506 |
} |
507 |
if (memcmp(orig + PCI_BASE_ADDRESS_0, d->config + PCI_BASE_ADDRESS_0, 24) |
508 |
|| ((orig[PCI_COMMAND] ^ d->config[PCI_COMMAND]) |
509 |
& (PCI_COMMAND_MEMORY | PCI_COMMAND_IO))) |
510 |
pci_update_mappings(d); |
511 |
} |
512 |
|
513 |
void pci_data_write(void *opaque, uint32_t addr, uint32_t val, int len) |
514 |
{ |
515 |
PCIBus *s = opaque; |
516 |
PCIDevice *pci_dev; |
517 |
int config_addr, bus_num;
|
518 |
|
519 |
#if defined(DEBUG_PCI) && 0 |
520 |
printf("pci_data_write: addr=%08x val=%08x len=%d\n",
|
521 |
addr, val, len); |
522 |
#endif
|
523 |
bus_num = (addr >> 16) & 0xff; |
524 |
while (s && s->bus_num != bus_num)
|
525 |
s = s->next; |
526 |
if (!s)
|
527 |
return;
|
528 |
pci_dev = s->devices[(addr >> 8) & 0xff]; |
529 |
if (!pci_dev)
|
530 |
return;
|
531 |
config_addr = addr & 0xff;
|
532 |
#if defined(DEBUG_PCI)
|
533 |
printf("pci_config_write: %s: addr=%02x val=%08x len=%d\n",
|
534 |
pci_dev->name, config_addr, val, len); |
535 |
#endif
|
536 |
pci_dev->config_write(pci_dev, config_addr, val, len); |
537 |
} |
538 |
|
539 |
uint32_t pci_data_read(void *opaque, uint32_t addr, int len) |
540 |
{ |
541 |
PCIBus *s = opaque; |
542 |
PCIDevice *pci_dev; |
543 |
int config_addr, bus_num;
|
544 |
uint32_t val; |
545 |
|
546 |
bus_num = (addr >> 16) & 0xff; |
547 |
while (s && s->bus_num != bus_num)
|
548 |
s= s->next; |
549 |
if (!s)
|
550 |
goto fail;
|
551 |
pci_dev = s->devices[(addr >> 8) & 0xff]; |
552 |
if (!pci_dev) {
|
553 |
fail:
|
554 |
switch(len) {
|
555 |
case 1: |
556 |
val = 0xff;
|
557 |
break;
|
558 |
case 2: |
559 |
val = 0xffff;
|
560 |
break;
|
561 |
default:
|
562 |
case 4: |
563 |
val = 0xffffffff;
|
564 |
break;
|
565 |
} |
566 |
goto the_end;
|
567 |
} |
568 |
config_addr = addr & 0xff;
|
569 |
val = pci_dev->config_read(pci_dev, config_addr, len); |
570 |
#if defined(DEBUG_PCI)
|
571 |
printf("pci_config_read: %s: addr=%02x val=%08x len=%d\n",
|
572 |
pci_dev->name, config_addr, val, len); |
573 |
#endif
|
574 |
the_end:
|
575 |
#if defined(DEBUG_PCI) && 0 |
576 |
printf("pci_data_read: addr=%08x val=%08x len=%d\n",
|
577 |
addr, val, len); |
578 |
#endif
|
579 |
return val;
|
580 |
} |
581 |
|
582 |
/***********************************************************/
|
583 |
/* generic PCI irq support */
|
584 |
|
585 |
/* 0 <= irq_num <= 3. level must be 0 or 1 */
|
586 |
static void pci_set_irq(void *opaque, int irq_num, int level) |
587 |
{ |
588 |
PCIDevice *pci_dev = (PCIDevice *)opaque; |
589 |
PCIBus *bus; |
590 |
int change;
|
591 |
|
592 |
change = level - pci_dev->irq_state[irq_num]; |
593 |
if (!change)
|
594 |
return;
|
595 |
|
596 |
pci_dev->irq_state[irq_num] = level; |
597 |
for (;;) {
|
598 |
bus = pci_dev->bus; |
599 |
irq_num = bus->map_irq(pci_dev, irq_num); |
600 |
if (bus->set_irq)
|
601 |
break;
|
602 |
pci_dev = bus->parent_dev; |
603 |
} |
604 |
bus->irq_count[irq_num] += change; |
605 |
bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0);
|
606 |
} |
607 |
|
608 |
/***********************************************************/
|
609 |
/* monitor info on PCI */
|
610 |
|
611 |
typedef struct { |
612 |
uint16_t class; |
613 |
const char *desc; |
614 |
} pci_class_desc; |
615 |
|
616 |
static const pci_class_desc pci_class_descriptions[] = |
617 |
{ |
618 |
{ 0x0100, "SCSI controller"}, |
619 |
{ 0x0101, "IDE controller"}, |
620 |
{ 0x0102, "Floppy controller"}, |
621 |
{ 0x0103, "IPI controller"}, |
622 |
{ 0x0104, "RAID controller"}, |
623 |
{ 0x0106, "SATA controller"}, |
624 |
{ 0x0107, "SAS controller"}, |
625 |
{ 0x0180, "Storage controller"}, |
626 |
{ 0x0200, "Ethernet controller"}, |
627 |
{ 0x0201, "Token Ring controller"}, |
628 |
{ 0x0202, "FDDI controller"}, |
629 |
{ 0x0203, "ATM controller"}, |
630 |
{ 0x0280, "Network controller"}, |
631 |
{ 0x0300, "VGA controller"}, |
632 |
{ 0x0301, "XGA controller"}, |
633 |
{ 0x0302, "3D controller"}, |
634 |
{ 0x0380, "Display controller"}, |
635 |
{ 0x0400, "Video controller"}, |
636 |
{ 0x0401, "Audio controller"}, |
637 |
{ 0x0402, "Phone"}, |
638 |
{ 0x0480, "Multimedia controller"}, |
639 |
{ 0x0500, "RAM controller"}, |
640 |
{ 0x0501, "Flash controller"}, |
641 |
{ 0x0580, "Memory controller"}, |
642 |
{ 0x0600, "Host bridge"}, |
643 |
{ 0x0601, "ISA bridge"}, |
644 |
{ 0x0602, "EISA bridge"}, |
645 |
{ 0x0603, "MC bridge"}, |
646 |
{ 0x0604, "PCI bridge"}, |
647 |
{ 0x0605, "PCMCIA bridge"}, |
648 |
{ 0x0606, "NUBUS bridge"}, |
649 |
{ 0x0607, "CARDBUS bridge"}, |
650 |
{ 0x0608, "RACEWAY bridge"}, |
651 |
{ 0x0680, "Bridge"}, |
652 |
{ 0x0c03, "USB controller"}, |
653 |
{ 0, NULL} |
654 |
}; |
655 |
|
656 |
static void pci_info_device(PCIDevice *d) |
657 |
{ |
658 |
Monitor *mon = cur_mon; |
659 |
int i, class;
|
660 |
PCIIORegion *r; |
661 |
const pci_class_desc *desc;
|
662 |
|
663 |
monitor_printf(mon, " Bus %2d, device %3d, function %d:\n",
|
664 |
d->bus->bus_num, d->devfn >> 3, d->devfn & 7); |
665 |
class = le16_to_cpu(*((uint16_t *)(d->config + PCI_CLASS_DEVICE))); |
666 |
monitor_printf(mon, " ");
|
667 |
desc = pci_class_descriptions; |
668 |
while (desc->desc && class != desc->class)
|
669 |
desc++; |
670 |
if (desc->desc) {
|
671 |
monitor_printf(mon, "%s", desc->desc);
|
672 |
} else {
|
673 |
monitor_printf(mon, "Class %04x", class);
|
674 |
} |
675 |
monitor_printf(mon, ": PCI device %04x:%04x\n",
|
676 |
le16_to_cpu(*((uint16_t *)(d->config + PCI_VENDOR_ID))), |
677 |
le16_to_cpu(*((uint16_t *)(d->config + PCI_DEVICE_ID)))); |
678 |
|
679 |
if (d->config[PCI_INTERRUPT_PIN] != 0) { |
680 |
monitor_printf(mon, " IRQ %d.\n",
|
681 |
d->config[PCI_INTERRUPT_LINE]); |
682 |
} |
683 |
if (class == 0x0604) { |
684 |
monitor_printf(mon, " BUS %d.\n", d->config[0x19]); |
685 |
} |
686 |
for(i = 0;i < PCI_NUM_REGIONS; i++) { |
687 |
r = &d->io_regions[i]; |
688 |
if (r->size != 0) { |
689 |
monitor_printf(mon, " BAR%d: ", i);
|
690 |
if (r->type & PCI_ADDRESS_SPACE_IO) {
|
691 |
monitor_printf(mon, "I/O at 0x%04x [0x%04x].\n",
|
692 |
r->addr, r->addr + r->size - 1);
|
693 |
} else {
|
694 |
monitor_printf(mon, "32 bit memory at 0x%08x [0x%08x].\n",
|
695 |
r->addr, r->addr + r->size - 1);
|
696 |
} |
697 |
} |
698 |
} |
699 |
if (class == 0x0604 && d->config[0x19] != 0) { |
700 |
pci_for_each_device(d->config[0x19], pci_info_device);
|
701 |
} |
702 |
} |
703 |
|
704 |
void pci_for_each_device(int bus_num, void (*fn)(PCIDevice *d)) |
705 |
{ |
706 |
PCIBus *bus = first_bus; |
707 |
PCIDevice *d; |
708 |
int devfn;
|
709 |
|
710 |
while (bus && bus->bus_num != bus_num)
|
711 |
bus = bus->next; |
712 |
if (bus) {
|
713 |
for(devfn = 0; devfn < 256; devfn++) { |
714 |
d = bus->devices[devfn]; |
715 |
if (d)
|
716 |
fn(d); |
717 |
} |
718 |
} |
719 |
} |
720 |
|
721 |
void pci_info(Monitor *mon)
|
722 |
{ |
723 |
pci_for_each_device(0, pci_info_device);
|
724 |
} |
725 |
|
726 |
PCIDevice *pci_create(const char *name, const char *devaddr) |
727 |
{ |
728 |
PCIBus *bus; |
729 |
int devfn;
|
730 |
DeviceState *dev; |
731 |
|
732 |
bus = pci_get_bus_devfn(&devfn, devaddr); |
733 |
if (!bus) {
|
734 |
fprintf(stderr, "Invalid PCI device address %s for device %s\n",
|
735 |
devaddr, name); |
736 |
exit(1);
|
737 |
} |
738 |
|
739 |
dev = qdev_create(&bus->qbus, name); |
740 |
qdev_set_prop_int(dev, "devfn", devfn);
|
741 |
return (PCIDevice *)dev;
|
742 |
} |
743 |
|
744 |
static const char * const pci_nic_models[] = { |
745 |
"ne2k_pci",
|
746 |
"i82551",
|
747 |
"i82557b",
|
748 |
"i82559er",
|
749 |
"rtl8139",
|
750 |
"e1000",
|
751 |
"pcnet",
|
752 |
"virtio",
|
753 |
NULL
|
754 |
}; |
755 |
|
756 |
static const char * const pci_nic_names[] = { |
757 |
"ne2k_pci",
|
758 |
"i82551",
|
759 |
"i82557b",
|
760 |
"i82559er",
|
761 |
"rtl8139",
|
762 |
"e1000",
|
763 |
"pcnet",
|
764 |
"virtio-net-pci",
|
765 |
NULL
|
766 |
}; |
767 |
|
768 |
/* Initialize a PCI NIC. */
|
769 |
PCIDevice *pci_nic_init(NICInfo *nd, const char *default_model, |
770 |
const char *default_devaddr) |
771 |
{ |
772 |
const char *devaddr = nd->devaddr ? nd->devaddr : default_devaddr; |
773 |
PCIDevice *pci_dev; |
774 |
DeviceState *dev; |
775 |
int i;
|
776 |
|
777 |
qemu_check_nic_model_list(nd, pci_nic_models, default_model); |
778 |
|
779 |
for (i = 0; pci_nic_models[i]; i++) { |
780 |
if (strcmp(nd->model, pci_nic_models[i]) == 0) { |
781 |
pci_dev = pci_create(pci_nic_names[i], devaddr); |
782 |
dev = &pci_dev->qdev; |
783 |
qdev_set_netdev(dev, nd); |
784 |
qdev_init(dev); |
785 |
nd->private = dev; |
786 |
return pci_dev;
|
787 |
} |
788 |
} |
789 |
|
790 |
return NULL; |
791 |
} |
792 |
|
793 |
typedef struct { |
794 |
PCIDevice dev; |
795 |
PCIBus *bus; |
796 |
} PCIBridge; |
797 |
|
798 |
static void pci_bridge_write_config(PCIDevice *d, |
799 |
uint32_t address, uint32_t val, int len)
|
800 |
{ |
801 |
PCIBridge *s = (PCIBridge *)d; |
802 |
|
803 |
pci_default_write_config(d, address, val, len); |
804 |
s->bus->bus_num = d->config[PCI_SECONDARY_BUS]; |
805 |
} |
806 |
|
807 |
PCIBus *pci_find_bus(int bus_num)
|
808 |
{ |
809 |
PCIBus *bus = first_bus; |
810 |
|
811 |
while (bus && bus->bus_num != bus_num)
|
812 |
bus = bus->next; |
813 |
|
814 |
return bus;
|
815 |
} |
816 |
|
817 |
PCIDevice *pci_find_device(int bus_num, int slot, int function) |
818 |
{ |
819 |
PCIBus *bus = pci_find_bus(bus_num); |
820 |
|
821 |
if (!bus)
|
822 |
return NULL; |
823 |
|
824 |
return bus->devices[PCI_DEVFN(slot, function)];
|
825 |
} |
826 |
|
827 |
PCIBus *pci_bridge_init(PCIBus *bus, int devfn, uint16_t vid, uint16_t did,
|
828 |
pci_map_irq_fn map_irq, const char *name) |
829 |
{ |
830 |
PCIBridge *s; |
831 |
s = (PCIBridge *)pci_register_device(bus, name, sizeof(PCIBridge),
|
832 |
devfn, NULL, pci_bridge_write_config);
|
833 |
|
834 |
pci_config_set_vendor_id(s->dev.config, vid); |
835 |
pci_config_set_device_id(s->dev.config, did); |
836 |
|
837 |
s->dev.config[0x04] = 0x06; // command = bus master, pci mem |
838 |
s->dev.config[0x05] = 0x00; |
839 |
s->dev.config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error |
840 |
s->dev.config[0x07] = 0x00; // status = fast devsel |
841 |
s->dev.config[0x08] = 0x00; // revision |
842 |
s->dev.config[0x09] = 0x00; // programming i/f |
843 |
pci_config_set_class(s->dev.config, PCI_CLASS_BRIDGE_PCI); |
844 |
s->dev.config[0x0D] = 0x10; // latency_timer |
845 |
s->dev.config[PCI_HEADER_TYPE] = |
846 |
PCI_HEADER_TYPE_MULTI_FUNCTION | PCI_HEADER_TYPE_BRIDGE; // header_type
|
847 |
s->dev.config[0x1E] = 0xa0; // secondary status |
848 |
|
849 |
s->bus = pci_register_secondary_bus(&s->dev, map_irq); |
850 |
return s->bus;
|
851 |
} |
852 |
|
853 |
typedef struct { |
854 |
DeviceInfo qdev; |
855 |
pci_qdev_initfn init; |
856 |
} PCIDeviceInfo; |
857 |
|
858 |
static void pci_qdev_init(DeviceState *qdev, DeviceInfo *base) |
859 |
{ |
860 |
PCIDevice *pci_dev = (PCIDevice *)qdev; |
861 |
PCIDeviceInfo *info = container_of(base, PCIDeviceInfo, qdev); |
862 |
PCIBus *bus; |
863 |
int devfn;
|
864 |
|
865 |
bus = FROM_QBUS(PCIBus, qdev_get_parent_bus(qdev)); |
866 |
devfn = qdev_get_prop_int(qdev, "devfn", -1); |
867 |
pci_dev = do_pci_register_device(pci_dev, bus, "FIXME", devfn,
|
868 |
NULL, NULL);//FIXME:config_read, config_write); |
869 |
assert(pci_dev); |
870 |
info->init(pci_dev); |
871 |
} |
872 |
|
873 |
void pci_qdev_register(const char *name, int size, pci_qdev_initfn init) |
874 |
{ |
875 |
PCIDeviceInfo *info; |
876 |
|
877 |
info = qemu_mallocz(sizeof(*info));
|
878 |
info->qdev.name = qemu_strdup(name); |
879 |
info->qdev.size = size; |
880 |
info->init = init; |
881 |
info->qdev.init = pci_qdev_init; |
882 |
info->qdev.bus_type = BUS_TYPE_PCI; |
883 |
|
884 |
qdev_register(&info->qdev); |
885 |
} |
886 |
|
887 |
PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name) |
888 |
{ |
889 |
DeviceState *dev; |
890 |
|
891 |
dev = qdev_create(&bus->qbus, name); |
892 |
qdev_set_prop_int(dev, "devfn", devfn);
|
893 |
qdev_init(dev); |
894 |
|
895 |
return (PCIDevice *)dev;
|
896 |
} |
897 |
|
898 |
static int pci_find_space(PCIDevice *pdev, uint8_t size) |
899 |
{ |
900 |
int offset = PCI_CONFIG_HEADER_SIZE;
|
901 |
int i;
|
902 |
for (i = PCI_CONFIG_HEADER_SIZE; i < PCI_CONFIG_SPACE_SIZE; ++i)
|
903 |
if (pdev->used[i])
|
904 |
offset = i + 1;
|
905 |
else if (i - offset + 1 == size) |
906 |
return offset;
|
907 |
return 0; |
908 |
} |
909 |
|
910 |
static uint8_t pci_find_capability_list(PCIDevice *pdev, uint8_t cap_id,
|
911 |
uint8_t *prev_p) |
912 |
{ |
913 |
uint8_t next, prev; |
914 |
|
915 |
if (!(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST))
|
916 |
return 0; |
917 |
|
918 |
for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]);
|
919 |
prev = next + PCI_CAP_LIST_NEXT) |
920 |
if (pdev->config[next + PCI_CAP_LIST_ID] == cap_id)
|
921 |
break;
|
922 |
|
923 |
if (prev_p)
|
924 |
*prev_p = prev; |
925 |
return next;
|
926 |
} |
927 |
|
928 |
/* Reserve space and add capability to the linked list in pci config space */
|
929 |
int pci_add_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size)
|
930 |
{ |
931 |
uint8_t offset = pci_find_space(pdev, size); |
932 |
uint8_t *config = pdev->config + offset; |
933 |
if (!offset)
|
934 |
return -ENOSPC;
|
935 |
config[PCI_CAP_LIST_ID] = cap_id; |
936 |
config[PCI_CAP_LIST_NEXT] = pdev->config[PCI_CAPABILITY_LIST]; |
937 |
pdev->config[PCI_CAPABILITY_LIST] = offset; |
938 |
pdev->config[PCI_STATUS] |= PCI_STATUS_CAP_LIST; |
939 |
memset(pdev->used + offset, 0xFF, size);
|
940 |
/* Make capability read-only by default */
|
941 |
memset(pdev->wmask + offset, 0, size);
|
942 |
return offset;
|
943 |
} |
944 |
|
945 |
/* Unlink capability from the pci config space. */
|
946 |
void pci_del_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size)
|
947 |
{ |
948 |
uint8_t prev, offset = pci_find_capability_list(pdev, cap_id, &prev); |
949 |
if (!offset)
|
950 |
return;
|
951 |
pdev->config[prev] = pdev->config[offset + PCI_CAP_LIST_NEXT]; |
952 |
/* Make capability writeable again */
|
953 |
memset(pdev->wmask + offset, 0xff, size);
|
954 |
memset(pdev->used + offset, 0, size);
|
955 |
|
956 |
if (!pdev->config[PCI_CAPABILITY_LIST])
|
957 |
pdev->config[PCI_STATUS] &= ~PCI_STATUS_CAP_LIST; |
958 |
} |
959 |
|
960 |
/* Reserve space for capability at a known offset (to call after load). */
|
961 |
void pci_reserve_capability(PCIDevice *pdev, uint8_t offset, uint8_t size)
|
962 |
{ |
963 |
memset(pdev->used + offset, 0xff, size);
|
964 |
} |
965 |
|
966 |
uint8_t pci_find_capability(PCIDevice *pdev, uint8_t cap_id) |
967 |
{ |
968 |
return pci_find_capability_list(pdev, cap_id, NULL); |
969 |
} |