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1 | 4c9649a9 | j_mayer | /*
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2 | 4c9649a9 | j_mayer | * Alpha emulation cpu definitions for qemu.
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3 | 5fafdf24 | ths | *
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4 | 4c9649a9 | j_mayer | * Copyright (c) 2007 Jocelyn Mayer
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5 | 4c9649a9 | j_mayer | *
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6 | 4c9649a9 | j_mayer | * This library is free software; you can redistribute it and/or
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7 | 4c9649a9 | j_mayer | * modify it under the terms of the GNU Lesser General Public
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8 | 4c9649a9 | j_mayer | * License as published by the Free Software Foundation; either
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9 | 4c9649a9 | j_mayer | * version 2 of the License, or (at your option) any later version.
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10 | 4c9649a9 | j_mayer | *
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11 | 4c9649a9 | j_mayer | * This library is distributed in the hope that it will be useful,
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12 | 4c9649a9 | j_mayer | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | 4c9649a9 | j_mayer | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | 4c9649a9 | j_mayer | * Lesser General Public License for more details.
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15 | 4c9649a9 | j_mayer | *
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16 | 4c9649a9 | j_mayer | * You should have received a copy of the GNU Lesser General Public
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17 | 4c9649a9 | j_mayer | * License along with this library; if not, write to the Free Software
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18 | 4c9649a9 | j_mayer | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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19 | 4c9649a9 | j_mayer | */
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20 | 4c9649a9 | j_mayer | |
21 | 4c9649a9 | j_mayer | #if !defined (__CPU_ALPHA_H__)
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22 | 4c9649a9 | j_mayer | #define __CPU_ALPHA_H__
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23 | 4c9649a9 | j_mayer | |
24 | 4c9649a9 | j_mayer | #include "config.h" |
25 | 4c9649a9 | j_mayer | |
26 | 4c9649a9 | j_mayer | #define TARGET_LONG_BITS 64 |
27 | 4c9649a9 | j_mayer | |
28 | 4c9649a9 | j_mayer | #include "cpu-defs.h" |
29 | 4c9649a9 | j_mayer | |
30 | 4c9649a9 | j_mayer | #include <setjmp.h> |
31 | 4c9649a9 | j_mayer | |
32 | 4c9649a9 | j_mayer | #include "softfloat.h" |
33 | 4c9649a9 | j_mayer | |
34 | 4c9649a9 | j_mayer | #define TARGET_HAS_ICE 1 |
35 | 4c9649a9 | j_mayer | |
36 | f071b4d3 | j_mayer | #define ELF_MACHINE EM_ALPHA
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37 | 4c9649a9 | j_mayer | |
38 | 4c9649a9 | j_mayer | #define ICACHE_LINE_SIZE 32 |
39 | 4c9649a9 | j_mayer | #define DCACHE_LINE_SIZE 32 |
40 | 4c9649a9 | j_mayer | |
41 | 4c9649a9 | j_mayer | #define TARGET_PAGE_BITS 12 |
42 | 4c9649a9 | j_mayer | |
43 | 4c9649a9 | j_mayer | #define VA_BITS 43 |
44 | 4c9649a9 | j_mayer | |
45 | 4c9649a9 | j_mayer | /* Alpha major type */
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46 | 4c9649a9 | j_mayer | enum {
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47 | 4c9649a9 | j_mayer | ALPHA_EV3 = 1,
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48 | 4c9649a9 | j_mayer | ALPHA_EV4 = 2,
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49 | 4c9649a9 | j_mayer | ALPHA_SIM = 3,
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50 | 4c9649a9 | j_mayer | ALPHA_LCA = 4,
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51 | 4c9649a9 | j_mayer | ALPHA_EV5 = 5, /* 21164 */ |
52 | 4c9649a9 | j_mayer | ALPHA_EV45 = 6, /* 21064A */ |
53 | 4c9649a9 | j_mayer | ALPHA_EV56 = 7, /* 21164A */ |
54 | 4c9649a9 | j_mayer | }; |
55 | 4c9649a9 | j_mayer | |
56 | 4c9649a9 | j_mayer | /* EV4 minor type */
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57 | 4c9649a9 | j_mayer | enum {
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58 | 4c9649a9 | j_mayer | ALPHA_EV4_2 = 0,
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59 | 4c9649a9 | j_mayer | ALPHA_EV4_3 = 1,
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60 | 4c9649a9 | j_mayer | }; |
61 | 4c9649a9 | j_mayer | |
62 | 4c9649a9 | j_mayer | /* LCA minor type */
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63 | 4c9649a9 | j_mayer | enum {
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64 | 4c9649a9 | j_mayer | ALPHA_LCA_1 = 1, /* 21066 */ |
65 | 4c9649a9 | j_mayer | ALPHA_LCA_2 = 2, /* 20166 */ |
66 | 4c9649a9 | j_mayer | ALPHA_LCA_3 = 3, /* 21068 */ |
67 | 4c9649a9 | j_mayer | ALPHA_LCA_4 = 4, /* 21068 */ |
68 | 4c9649a9 | j_mayer | ALPHA_LCA_5 = 5, /* 21066A */ |
69 | 4c9649a9 | j_mayer | ALPHA_LCA_6 = 6, /* 21068A */ |
70 | 4c9649a9 | j_mayer | }; |
71 | 4c9649a9 | j_mayer | |
72 | 4c9649a9 | j_mayer | /* EV5 minor type */
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73 | 4c9649a9 | j_mayer | enum {
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74 | 4c9649a9 | j_mayer | ALPHA_EV5_1 = 1, /* Rev BA, CA */ |
75 | 4c9649a9 | j_mayer | ALPHA_EV5_2 = 2, /* Rev DA, EA */ |
76 | 4c9649a9 | j_mayer | ALPHA_EV5_3 = 3, /* Pass 3 */ |
77 | 4c9649a9 | j_mayer | ALPHA_EV5_4 = 4, /* Pass 3.2 */ |
78 | 4c9649a9 | j_mayer | ALPHA_EV5_5 = 5, /* Pass 4 */ |
79 | 4c9649a9 | j_mayer | }; |
80 | 4c9649a9 | j_mayer | |
81 | 4c9649a9 | j_mayer | /* EV45 minor type */
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82 | 4c9649a9 | j_mayer | enum {
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83 | 4c9649a9 | j_mayer | ALPHA_EV45_1 = 1, /* Pass 1 */ |
84 | 4c9649a9 | j_mayer | ALPHA_EV45_2 = 2, /* Pass 1.1 */ |
85 | 4c9649a9 | j_mayer | ALPHA_EV45_3 = 3, /* Pass 2 */ |
86 | 4c9649a9 | j_mayer | }; |
87 | 4c9649a9 | j_mayer | |
88 | 4c9649a9 | j_mayer | /* EV56 minor type */
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89 | 4c9649a9 | j_mayer | enum {
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90 | 4c9649a9 | j_mayer | ALPHA_EV56_1 = 1, /* Pass 1 */ |
91 | 4c9649a9 | j_mayer | ALPHA_EV56_2 = 2, /* Pass 2 */ |
92 | 4c9649a9 | j_mayer | }; |
93 | 4c9649a9 | j_mayer | |
94 | 4c9649a9 | j_mayer | enum {
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95 | 4c9649a9 | j_mayer | IMPLVER_2106x = 0, /* EV4, EV45 & LCA45 */ |
96 | 4c9649a9 | j_mayer | IMPLVER_21164 = 1, /* EV5, EV56 & PCA45 */ |
97 | 4c9649a9 | j_mayer | IMPLVER_21264 = 2, /* EV6, EV67 & EV68x */ |
98 | 4c9649a9 | j_mayer | IMPLVER_21364 = 3, /* EV7 & EV79 */ |
99 | 4c9649a9 | j_mayer | }; |
100 | 4c9649a9 | j_mayer | |
101 | 4c9649a9 | j_mayer | enum {
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102 | 4c9649a9 | j_mayer | AMASK_BWX = 0x00000001,
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103 | 4c9649a9 | j_mayer | AMASK_FIX = 0x00000002,
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104 | 4c9649a9 | j_mayer | AMASK_CIX = 0x00000004,
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105 | 4c9649a9 | j_mayer | AMASK_MVI = 0x00000100,
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106 | 4c9649a9 | j_mayer | AMASK_TRAP = 0x00000200,
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107 | 4c9649a9 | j_mayer | AMASK_PREFETCH = 0x00001000,
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108 | 4c9649a9 | j_mayer | }; |
109 | 4c9649a9 | j_mayer | |
110 | 4c9649a9 | j_mayer | enum {
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111 | 4c9649a9 | j_mayer | VAX_ROUND_NORMAL = 0,
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112 | 4c9649a9 | j_mayer | VAX_ROUND_CHOPPED, |
113 | 4c9649a9 | j_mayer | }; |
114 | 4c9649a9 | j_mayer | |
115 | 4c9649a9 | j_mayer | enum {
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116 | 4c9649a9 | j_mayer | IEEE_ROUND_NORMAL = 0,
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117 | 4c9649a9 | j_mayer | IEEE_ROUND_DYNAMIC, |
118 | 4c9649a9 | j_mayer | IEEE_ROUND_PLUS, |
119 | 4c9649a9 | j_mayer | IEEE_ROUND_MINUS, |
120 | 4c9649a9 | j_mayer | IEEE_ROUND_CHOPPED, |
121 | 4c9649a9 | j_mayer | }; |
122 | 4c9649a9 | j_mayer | |
123 | 4c9649a9 | j_mayer | /* IEEE floating-point operations encoding */
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124 | 4c9649a9 | j_mayer | /* Trap mode */
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125 | 4c9649a9 | j_mayer | enum {
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126 | 4c9649a9 | j_mayer | FP_TRAP_I = 0x0,
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127 | 4c9649a9 | j_mayer | FP_TRAP_U = 0x1,
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128 | 4c9649a9 | j_mayer | FP_TRAP_S = 0x4,
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129 | 4c9649a9 | j_mayer | FP_TRAP_SU = 0x5,
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130 | 4c9649a9 | j_mayer | FP_TRAP_SUI = 0x7,
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131 | 4c9649a9 | j_mayer | }; |
132 | 4c9649a9 | j_mayer | |
133 | 4c9649a9 | j_mayer | /* Rounding mode */
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134 | 4c9649a9 | j_mayer | enum {
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135 | 4c9649a9 | j_mayer | FP_ROUND_CHOPPED = 0x0,
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136 | 4c9649a9 | j_mayer | FP_ROUND_MINUS = 0x1,
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137 | 4c9649a9 | j_mayer | FP_ROUND_NORMAL = 0x2,
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138 | 4c9649a9 | j_mayer | FP_ROUND_DYNAMIC = 0x3,
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139 | 4c9649a9 | j_mayer | }; |
140 | 4c9649a9 | j_mayer | |
141 | 4c9649a9 | j_mayer | /* Internal processor registers */
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142 | 4c9649a9 | j_mayer | /* XXX: TOFIX: most of those registers are implementation dependant */
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143 | 4c9649a9 | j_mayer | enum {
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144 | 4c9649a9 | j_mayer | /* Ebox IPRs */
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145 | 4c9649a9 | j_mayer | IPR_CC = 0xC0,
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146 | 4c9649a9 | j_mayer | IPR_CC_CTL = 0xC1,
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147 | 4c9649a9 | j_mayer | IPR_VA = 0xC2,
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148 | 4c9649a9 | j_mayer | IPR_VA_CTL = 0xC4,
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149 | 4c9649a9 | j_mayer | IPR_VA_FORM = 0xC3,
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150 | 4c9649a9 | j_mayer | /* Ibox IPRs */
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151 | 4c9649a9 | j_mayer | IPR_ITB_TAG = 0x00,
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152 | 4c9649a9 | j_mayer | IPR_ITB_PTE = 0x01,
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153 | 4c9649a9 | j_mayer | IPT_ITB_IAP = 0x02,
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154 | 4c9649a9 | j_mayer | IPT_ITB_IA = 0x03,
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155 | 4c9649a9 | j_mayer | IPT_ITB_IS = 0x04,
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156 | 4c9649a9 | j_mayer | IPR_PMPC = 0x05,
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157 | 4c9649a9 | j_mayer | IPR_EXC_ADDR = 0x06,
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158 | 4c9649a9 | j_mayer | IPR_IVA_FORM = 0x07,
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159 | 4c9649a9 | j_mayer | IPR_CM = 0x09,
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160 | 4c9649a9 | j_mayer | IPR_IER = 0x0A,
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161 | 4c9649a9 | j_mayer | IPR_SIRR = 0x0C,
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162 | 4c9649a9 | j_mayer | IPR_ISUM = 0x0D,
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163 | 4c9649a9 | j_mayer | IPR_HW_INT_CLR = 0x0E,
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164 | 4c9649a9 | j_mayer | IPR_EXC_SUM = 0x0F,
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165 | 4c9649a9 | j_mayer | IPR_PAL_BASE = 0x10,
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166 | 4c9649a9 | j_mayer | IPR_I_CTL = 0x11,
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167 | 4c9649a9 | j_mayer | IPR_I_STAT = 0x16,
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168 | 4c9649a9 | j_mayer | IPR_IC_FLUSH = 0x13,
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169 | 4c9649a9 | j_mayer | IPR_IC_FLUSH_ASM = 0x12,
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170 | 4c9649a9 | j_mayer | IPR_CLR_MAP = 0x15,
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171 | 4c9649a9 | j_mayer | IPR_SLEEP = 0x17,
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172 | 4c9649a9 | j_mayer | IPR_PCTX = 0x40,
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173 | 4c9649a9 | j_mayer | IPR_PCTR_CTL = 0x14,
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174 | 4c9649a9 | j_mayer | /* Mbox IPRs */
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175 | 4c9649a9 | j_mayer | IPR_DTB_TAG0 = 0x20,
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176 | 4c9649a9 | j_mayer | IPR_DTB_TAG1 = 0xA0,
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177 | 4c9649a9 | j_mayer | IPR_DTB_PTE0 = 0x21,
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178 | 4c9649a9 | j_mayer | IPR_DTB_PTE1 = 0xA1,
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179 | 4c9649a9 | j_mayer | IPR_DTB_ALTMODE = 0xA6,
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180 | 4c9649a9 | j_mayer | IPR_DTB_IAP = 0xA2,
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181 | 4c9649a9 | j_mayer | IPR_DTB_IA = 0xA3,
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182 | 4c9649a9 | j_mayer | IPR_DTB_IS0 = 0x24,
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183 | 4c9649a9 | j_mayer | IPR_DTB_IS1 = 0xA4,
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184 | 4c9649a9 | j_mayer | IPR_DTB_ASN0 = 0x25,
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185 | 4c9649a9 | j_mayer | IPR_DTB_ASN1 = 0xA5,
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186 | 4c9649a9 | j_mayer | IPR_MM_STAT = 0x27,
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187 | 4c9649a9 | j_mayer | IPR_M_CTL = 0x28,
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188 | 4c9649a9 | j_mayer | IPR_DC_CTL = 0x29,
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189 | 4c9649a9 | j_mayer | IPR_DC_STAT = 0x2A,
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190 | 4c9649a9 | j_mayer | /* Cbox IPRs */
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191 | 4c9649a9 | j_mayer | IPR_C_DATA = 0x2B,
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192 | 4c9649a9 | j_mayer | IPR_C_SHIFT = 0x2C,
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193 | 4c9649a9 | j_mayer | |
194 | 4c9649a9 | j_mayer | IPR_ASN, |
195 | 4c9649a9 | j_mayer | IPR_ASTEN, |
196 | 4c9649a9 | j_mayer | IPR_ASTSR, |
197 | 4c9649a9 | j_mayer | IPR_DATFX, |
198 | 4c9649a9 | j_mayer | IPR_ESP, |
199 | 4c9649a9 | j_mayer | IPR_FEN, |
200 | 4c9649a9 | j_mayer | IPR_IPIR, |
201 | 4c9649a9 | j_mayer | IPR_IPL, |
202 | 4c9649a9 | j_mayer | IPR_KSP, |
203 | 4c9649a9 | j_mayer | IPR_MCES, |
204 | 4c9649a9 | j_mayer | IPR_PERFMON, |
205 | 4c9649a9 | j_mayer | IPR_PCBB, |
206 | 4c9649a9 | j_mayer | IPR_PRBR, |
207 | 4c9649a9 | j_mayer | IPR_PTBR, |
208 | 4c9649a9 | j_mayer | IPR_SCBB, |
209 | 4c9649a9 | j_mayer | IPR_SISR, |
210 | 4c9649a9 | j_mayer | IPR_SSP, |
211 | 4c9649a9 | j_mayer | IPR_SYSPTBR, |
212 | 4c9649a9 | j_mayer | IPR_TBCHK, |
213 | 4c9649a9 | j_mayer | IPR_TBIA, |
214 | 4c9649a9 | j_mayer | IPR_TBIAP, |
215 | 4c9649a9 | j_mayer | IPR_TBIS, |
216 | 4c9649a9 | j_mayer | IPR_TBISD, |
217 | 4c9649a9 | j_mayer | IPR_TBISI, |
218 | 4c9649a9 | j_mayer | IPR_USP, |
219 | 4c9649a9 | j_mayer | IPR_VIRBND, |
220 | 4c9649a9 | j_mayer | IPR_VPTB, |
221 | 4c9649a9 | j_mayer | IPR_WHAMI, |
222 | 4c9649a9 | j_mayer | IPR_ALT_MODE, |
223 | 4c9649a9 | j_mayer | IPR_LAST, |
224 | 4c9649a9 | j_mayer | }; |
225 | 4c9649a9 | j_mayer | |
226 | 4c9649a9 | j_mayer | typedef struct CPUAlphaState CPUAlphaState; |
227 | 4c9649a9 | j_mayer | |
228 | 4c9649a9 | j_mayer | typedef struct pal_handler_t pal_handler_t; |
229 | 4c9649a9 | j_mayer | struct pal_handler_t {
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230 | 4c9649a9 | j_mayer | /* Reset */
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231 | 4c9649a9 | j_mayer | void (*reset)(CPUAlphaState *env);
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232 | 4c9649a9 | j_mayer | /* Uncorrectable hardware error */
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233 | 4c9649a9 | j_mayer | void (*machine_check)(CPUAlphaState *env);
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234 | 4c9649a9 | j_mayer | /* Arithmetic exception */
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235 | 4c9649a9 | j_mayer | void (*arithmetic)(CPUAlphaState *env);
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236 | 4c9649a9 | j_mayer | /* Interrupt / correctable hardware error */
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237 | 4c9649a9 | j_mayer | void (*interrupt)(CPUAlphaState *env);
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238 | 4c9649a9 | j_mayer | /* Data fault */
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239 | 4c9649a9 | j_mayer | void (*dfault)(CPUAlphaState *env);
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240 | 4c9649a9 | j_mayer | /* DTB miss pal */
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241 | 4c9649a9 | j_mayer | void (*dtb_miss_pal)(CPUAlphaState *env);
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242 | 4c9649a9 | j_mayer | /* DTB miss native */
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243 | 4c9649a9 | j_mayer | void (*dtb_miss_native)(CPUAlphaState *env);
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244 | 4c9649a9 | j_mayer | /* Unaligned access */
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245 | 4c9649a9 | j_mayer | void (*unalign)(CPUAlphaState *env);
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246 | 4c9649a9 | j_mayer | /* ITB miss */
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247 | 4c9649a9 | j_mayer | void (*itb_miss)(CPUAlphaState *env);
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248 | 4c9649a9 | j_mayer | /* Instruction stream access violation */
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249 | 4c9649a9 | j_mayer | void (*itb_acv)(CPUAlphaState *env);
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250 | 4c9649a9 | j_mayer | /* Reserved or privileged opcode */
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251 | 4c9649a9 | j_mayer | void (*opcdec)(CPUAlphaState *env);
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252 | 4c9649a9 | j_mayer | /* Floating point exception */
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253 | 4c9649a9 | j_mayer | void (*fen)(CPUAlphaState *env);
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254 | 4c9649a9 | j_mayer | /* Call pal instruction */
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255 | 4c9649a9 | j_mayer | void (*call_pal)(CPUAlphaState *env, uint32_t palcode);
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256 | 4c9649a9 | j_mayer | }; |
257 | 4c9649a9 | j_mayer | |
258 | 6ebbf390 | j_mayer | #define NB_MMU_MODES 4 |
259 | 6ebbf390 | j_mayer | |
260 | 4c9649a9 | j_mayer | struct CPUAlphaState {
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261 | 4c9649a9 | j_mayer | uint64_t ir[31];
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262 | 4c9649a9 | j_mayer | float64 fir[31];
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263 | 4c9649a9 | j_mayer | float_status fp_status; |
264 | 4c9649a9 | j_mayer | uint64_t fpcr; |
265 | 4c9649a9 | j_mayer | uint64_t pc; |
266 | 4c9649a9 | j_mayer | uint64_t lock; |
267 | 4c9649a9 | j_mayer | uint32_t pcc[2];
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268 | 4c9649a9 | j_mayer | uint64_t ipr[IPR_LAST]; |
269 | 4c9649a9 | j_mayer | uint64_t ps; |
270 | 4c9649a9 | j_mayer | uint64_t unique; |
271 | 4c9649a9 | j_mayer | int saved_mode; /* Used for HW_LD / HW_ST */ |
272 | 4c9649a9 | j_mayer | |
273 | bf9525e9 | j_mayer | #if TARGET_LONG_BITS > HOST_LONG_BITS
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274 | bf9525e9 | j_mayer | /* temporary fixed-point registers
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275 | bf9525e9 | j_mayer | * used to emulate 64 bits target on 32 bits hosts
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276 | 5fafdf24 | ths | */
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277 | bf9525e9 | j_mayer | target_ulong t0, t1, t2; |
278 | bf9525e9 | j_mayer | #endif
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279 | 4c9649a9 | j_mayer | /* */
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280 | 4c9649a9 | j_mayer | double ft0, ft1, ft2;
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281 | 4c9649a9 | j_mayer | |
282 | 4c9649a9 | j_mayer | /* Those resources are used only in Qemu core */
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283 | 4c9649a9 | j_mayer | CPU_COMMON |
284 | 4c9649a9 | j_mayer | |
285 | 4c9649a9 | j_mayer | jmp_buf jmp_env; |
286 | 4c9649a9 | j_mayer | int user_mode_only; /* user mode only simulation */ |
287 | 4c9649a9 | j_mayer | uint32_t hflags; |
288 | 4c9649a9 | j_mayer | int halted;
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289 | 4c9649a9 | j_mayer | |
290 | 4c9649a9 | j_mayer | int exception_index;
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291 | 4c9649a9 | j_mayer | int error_code;
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292 | 4c9649a9 | j_mayer | int interrupt_request;
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293 | 4c9649a9 | j_mayer | |
294 | 4c9649a9 | j_mayer | uint32_t features; |
295 | 4c9649a9 | j_mayer | uint32_t amask; |
296 | 4c9649a9 | j_mayer | int implver;
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297 | 4c9649a9 | j_mayer | pal_handler_t *pal_handler; |
298 | 4c9649a9 | j_mayer | }; |
299 | 4c9649a9 | j_mayer | |
300 | 9467d44c | ths | #define CPUState CPUAlphaState
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301 | 9467d44c | ths | #define cpu_init cpu_alpha_init
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302 | 9467d44c | ths | #define cpu_exec cpu_alpha_exec
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303 | 9467d44c | ths | #define cpu_gen_code cpu_alpha_gen_code
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304 | 9467d44c | ths | #define cpu_signal_handler cpu_alpha_signal_handler
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305 | 9467d44c | ths | |
306 | 6ebbf390 | j_mayer | /* MMU modes definitions */
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307 | 6ebbf390 | j_mayer | #define MMU_MODE0_SUFFIX _kernel
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308 | 6ebbf390 | j_mayer | #define MMU_MODE1_SUFFIX _executive
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309 | 6ebbf390 | j_mayer | #define MMU_MODE2_SUFFIX _supervisor
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310 | 6ebbf390 | j_mayer | #define MMU_MODE3_SUFFIX _user
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311 | 6ebbf390 | j_mayer | #define MMU_USER_IDX 3 |
312 | 6ebbf390 | j_mayer | static inline int cpu_mmu_index (CPUState *env) |
313 | 6ebbf390 | j_mayer | { |
314 | 6ebbf390 | j_mayer | return (env->ps >> 3) & 3; |
315 | 6ebbf390 | j_mayer | } |
316 | 6ebbf390 | j_mayer | |
317 | 4c9649a9 | j_mayer | #include "cpu-all.h" |
318 | 4c9649a9 | j_mayer | |
319 | 4c9649a9 | j_mayer | enum {
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320 | 4c9649a9 | j_mayer | FEATURE_ASN = 0x00000001,
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321 | 4c9649a9 | j_mayer | FEATURE_SPS = 0x00000002,
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322 | 4c9649a9 | j_mayer | FEATURE_VIRBND = 0x00000004,
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323 | 4c9649a9 | j_mayer | FEATURE_TBCHK = 0x00000008,
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324 | 4c9649a9 | j_mayer | }; |
325 | 4c9649a9 | j_mayer | |
326 | 4c9649a9 | j_mayer | enum {
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327 | 4c9649a9 | j_mayer | EXCP_RESET = 0x0000,
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328 | 4c9649a9 | j_mayer | EXCP_MCHK = 0x0020,
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329 | 4c9649a9 | j_mayer | EXCP_ARITH = 0x0060,
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330 | 4c9649a9 | j_mayer | EXCP_HW_INTERRUPT = 0x00E0,
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331 | 4c9649a9 | j_mayer | EXCP_DFAULT = 0x01E0,
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332 | 4c9649a9 | j_mayer | EXCP_DTB_MISS_PAL = 0x09E0,
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333 | 4c9649a9 | j_mayer | EXCP_ITB_MISS = 0x03E0,
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334 | 4c9649a9 | j_mayer | EXCP_ITB_ACV = 0x07E0,
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335 | 4c9649a9 | j_mayer | EXCP_DTB_MISS_NATIVE = 0x08E0,
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336 | 4c9649a9 | j_mayer | EXCP_UNALIGN = 0x11E0,
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337 | 4c9649a9 | j_mayer | EXCP_OPCDEC = 0x13E0,
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338 | 4c9649a9 | j_mayer | EXCP_FEN = 0x17E0,
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339 | 4c9649a9 | j_mayer | EXCP_CALL_PAL = 0x2000,
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340 | 4c9649a9 | j_mayer | EXCP_CALL_PALP = 0x3000,
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341 | 4c9649a9 | j_mayer | EXCP_CALL_PALE = 0x4000,
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342 | 4c9649a9 | j_mayer | /* Pseudo exception for console */
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343 | 4c9649a9 | j_mayer | EXCP_CONSOLE_DISPATCH = 0x4001,
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344 | 4c9649a9 | j_mayer | EXCP_CONSOLE_FIXUP = 0x4002,
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345 | 4c9649a9 | j_mayer | }; |
346 | 4c9649a9 | j_mayer | |
347 | 4c9649a9 | j_mayer | /* Arithmetic exception */
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348 | 4c9649a9 | j_mayer | enum {
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349 | 4c9649a9 | j_mayer | EXCP_ARITH_OVERFLOW, |
350 | 4c9649a9 | j_mayer | }; |
351 | 4c9649a9 | j_mayer | |
352 | 4c9649a9 | j_mayer | enum {
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353 | 4c9649a9 | j_mayer | PALCODE_CALL = 0x00000000,
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354 | 4c9649a9 | j_mayer | PALCODE_LD = 0x01000000,
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355 | 4c9649a9 | j_mayer | PALCODE_ST = 0x02000000,
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356 | 4c9649a9 | j_mayer | PALCODE_MFPR = 0x03000000,
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357 | 4c9649a9 | j_mayer | PALCODE_MTPR = 0x04000000,
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358 | 4c9649a9 | j_mayer | PALCODE_REI = 0x05000000,
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359 | 4c9649a9 | j_mayer | PALCODE_INIT = 0xF0000000,
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360 | 4c9649a9 | j_mayer | }; |
361 | 4c9649a9 | j_mayer | |
362 | 4c9649a9 | j_mayer | enum {
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363 | 4c9649a9 | j_mayer | IR_V0 = 0,
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364 | 4c9649a9 | j_mayer | IR_T0 = 1,
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365 | 4c9649a9 | j_mayer | IR_T1 = 2,
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366 | 4c9649a9 | j_mayer | IR_T2 = 3,
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367 | 4c9649a9 | j_mayer | IR_T3 = 4,
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368 | 4c9649a9 | j_mayer | IR_T4 = 5,
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369 | 4c9649a9 | j_mayer | IR_T5 = 6,
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370 | 4c9649a9 | j_mayer | IR_T6 = 7,
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371 | 4c9649a9 | j_mayer | IR_T7 = 8,
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372 | 4c9649a9 | j_mayer | IR_S0 = 9,
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373 | 4c9649a9 | j_mayer | IR_S1 = 10,
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374 | 4c9649a9 | j_mayer | IR_S2 = 11,
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375 | 4c9649a9 | j_mayer | IR_S3 = 12,
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376 | 4c9649a9 | j_mayer | IR_S4 = 13,
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377 | 4c9649a9 | j_mayer | IR_S5 = 14,
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378 | 4c9649a9 | j_mayer | IR_S6 = 15,
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379 | 4c9649a9 | j_mayer | #define IR_FP IR_S6
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380 | 4c9649a9 | j_mayer | IR_A0 = 16,
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381 | 4c9649a9 | j_mayer | IR_A1 = 17,
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382 | 4c9649a9 | j_mayer | IR_A2 = 18,
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383 | 4c9649a9 | j_mayer | IR_A3 = 19,
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384 | 4c9649a9 | j_mayer | IR_A4 = 20,
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385 | 4c9649a9 | j_mayer | IR_A5 = 21,
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386 | 4c9649a9 | j_mayer | IR_T8 = 22,
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387 | 4c9649a9 | j_mayer | IR_T9 = 23,
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388 | 4c9649a9 | j_mayer | IR_T10 = 24,
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389 | 4c9649a9 | j_mayer | IR_T11 = 25,
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390 | 4c9649a9 | j_mayer | IR_RA = 26,
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391 | 4c9649a9 | j_mayer | IR_T12 = 27,
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392 | 4c9649a9 | j_mayer | #define IR_PV IR_T12
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393 | 4c9649a9 | j_mayer | IR_AT = 28,
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394 | 4c9649a9 | j_mayer | IR_GP = 29,
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395 | 4c9649a9 | j_mayer | IR_SP = 30,
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396 | 4c9649a9 | j_mayer | IR_ZERO = 31,
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397 | 4c9649a9 | j_mayer | }; |
398 | 4c9649a9 | j_mayer | |
399 | aaed909a | bellard | CPUAlphaState * cpu_alpha_init (const char *cpu_model); |
400 | e96efcfc | j_mayer | int cpu_alpha_exec(CPUAlphaState *s);
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401 | e96efcfc | j_mayer | /* you can call this signal handler from your SIGBUS and SIGSEGV
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402 | e96efcfc | j_mayer | signal handlers to inform the virtual CPU of exceptions. non zero
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403 | e96efcfc | j_mayer | is returned if the signal was handled by the virtual CPU. */
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404 | 5fafdf24 | ths | int cpu_alpha_signal_handler(int host_signum, void *pinfo, |
405 | e96efcfc | j_mayer | void *puc);
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406 | 4c9649a9 | j_mayer | int cpu_alpha_mfpr (CPUState *env, int iprn, uint64_t *valp); |
407 | 4c9649a9 | j_mayer | int cpu_alpha_mtpr (CPUState *env, int iprn, uint64_t val, uint64_t *oldvalp); |
408 | 4c9649a9 | j_mayer | void cpu_loop_exit (void); |
409 | 4c9649a9 | j_mayer | void pal_init (CPUState *env);
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410 | 4c9649a9 | j_mayer | void call_pal (CPUState *env, int palcode); |
411 | 4c9649a9 | j_mayer | |
412 | 4c9649a9 | j_mayer | #endif /* !defined (__CPU_ALPHA_H__) */ |