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/*
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 *  CRIS emulation micro-operations for qemu.
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 *
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 *  Copyright (c) 2007 Edgar E. Iglesias, Axis Communications AB.
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 *
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 * This library is free software; you can redistribute it and/or
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 * modify it under the terms of the GNU Lesser General Public
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 * License as published by the Free Software Foundation; either
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 * version 2 of the License, or (at your option) any later version.
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 *
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 * This library is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
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 * Lesser General Public License for more details.
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 *
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 * You should have received a copy of the GNU Lesser General Public
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 * License along with this library; if not, write to the Free Software
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 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
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 */
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#include "exec.h"
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#include "host-utils.h"
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#define REGNAME r0
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#define REG (env->regs[0])
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#include "op_template.h"
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#define REGNAME r1
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#define REG (env->regs[1])
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#include "op_template.h"
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#define REGNAME r2
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#define REG (env->regs[2])
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#include "op_template.h"
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#define REGNAME r3
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#define REG (env->regs[3])
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#include "op_template.h"
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#define REGNAME r4
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#define REG (env->regs[4])
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#include "op_template.h"
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#define REGNAME r5
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#define REG (env->regs[5])
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#include "op_template.h"
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#define REGNAME r6
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#define REG (env->regs[6])
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#include "op_template.h"
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#define REGNAME r7
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#define REG (env->regs[7])
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#include "op_template.h"
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#define REGNAME r8
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#define REG (env->regs[8])
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#include "op_template.h"
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#define REGNAME r9
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#define REG (env->regs[9])
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#include "op_template.h"
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#define REGNAME r10
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#define REG (env->regs[10])
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#include "op_template.h"
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#define REGNAME r11
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#define REG (env->regs[11])
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#include "op_template.h"
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#define REGNAME r12
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#define REG (env->regs[12])
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#include "op_template.h"
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#define REGNAME r13
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#define REG (env->regs[13])
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#include "op_template.h"
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#define REGNAME r14
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#define REG (env->regs[14])
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#include "op_template.h"
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#define REGNAME r15
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#define REG (env->regs[15])
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#include "op_template.h"
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#define REGNAME p0
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#define REG (env->pregs[0])
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#include "op_template.h"
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#define REGNAME p1
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#define REG (env->pregs[1])
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#include "op_template.h"
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#define REGNAME p2
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#define REG (env->pregs[2])
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#include "op_template.h"
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#define REGNAME p3
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#define REG (env->pregs[3])
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#include "op_template.h"
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#define REGNAME p4
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#define REG (env->pregs[4])
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#include "op_template.h"
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#define REGNAME p5
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#define REG (env->pregs[5])
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#include "op_template.h"
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#define REGNAME p6
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#define REG (env->pregs[6])
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#include "op_template.h"
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#define REGNAME p7
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#define REG (env->pregs[7])
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#include "op_template.h"
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#define REGNAME p8
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#define REG (env->pregs[8])
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#include "op_template.h"
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#define REGNAME p9
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#define REG (env->pregs[9])
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#include "op_template.h"
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#define REGNAME p10
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#define REG (env->pregs[10])
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#include "op_template.h"
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#define REGNAME p11
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#define REG (env->pregs[11])
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#include "op_template.h"
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#define REGNAME p12
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#define REG (env->pregs[12])
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#include "op_template.h"
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#define REGNAME p13
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#define REG (env->pregs[13])
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#include "op_template.h"
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#define REGNAME p14
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#define REG (env->pregs[14])
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#include "op_template.h"
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#define REGNAME p15
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#define REG (env->pregs[15])
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#include "op_template.h"
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/* Microcode.  */
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void OPPROTO op_break_im(void)
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{
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        env->trap_vector = PARAM1;
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        env->exception_index = EXCP_BREAK;
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        cpu_loop_exit();
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}
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void OPPROTO op_debug(void)
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{
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        env->exception_index = EXCP_DEBUG;
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        cpu_loop_exit();
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}
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void OPPROTO op_exec_insn(void)
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{
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        env->stats.exec_insns++;
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        RETURN();
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}
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void OPPROTO op_exec_load(void)
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{
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        env->stats.exec_loads++;
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        RETURN();
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}
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void OPPROTO op_exec_store(void)
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{
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        env->stats.exec_stores++;
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        RETURN();
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}
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void OPPROTO op_ccs_lshift (void)
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{
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        uint32_t ccs;
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        /* Apply the ccs shift.  */
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        ccs = env->pregs[PR_CCS];
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        ccs = (ccs & 0xc0000000) | ((ccs << 12) >> 2);
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        env->pregs[PR_CCS] = ccs;
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        RETURN();
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}
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void OPPROTO op_ccs_rshift (void)
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{
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        register uint32_t ccs;
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        /* Apply the ccs shift.  */
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        ccs = env->pregs[PR_CCS];
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        ccs = (ccs & 0xc0000000) | ((ccs & 0x0fffffff) >> 10);
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        if (ccs & U_FLAG)
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        {
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                /* Enter user mode.  */
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                env->ksp = env->regs[R_SP];
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                env->regs[R_SP] = env->pregs[PR_USP];
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        }
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        env->pregs[PR_CCS] = ccs;
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        RETURN();
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}
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void OPPROTO op_setf (void)
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{
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        if (!(env->pregs[PR_CCS] & U_FLAG) && (PARAM1 & U_FLAG))
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        {
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                /* Enter user mode.  */
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                env->ksp = env->regs[R_SP];
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                env->regs[R_SP] = env->pregs[PR_USP];
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        }
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        env->pregs[PR_CCS] |= PARAM1;
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        RETURN();
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}
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void OPPROTO op_clrf (void)
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{
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        env->pregs[PR_CCS] &= ~PARAM1;
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        RETURN();
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}
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void OPPROTO op_movl_debug1_T0 (void)
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{
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        env->debug1 = T0;
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        RETURN();
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}
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void OPPROTO op_movl_debug2_T0 (void)
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{
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        env->debug2 = T0;
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        RETURN();
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}
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void OPPROTO op_movl_debug3_T0 (void)
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{
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        env->debug3 = T0;
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        RETURN();
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}
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void OPPROTO op_movl_debug1_T1 (void)
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{
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        env->debug1 = T1;
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        RETURN();
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}
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void OPPROTO op_movl_debug2_T1 (void)
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{
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        env->debug2 = T1;
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        RETURN();
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}
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void OPPROTO op_movl_debug3_T1 (void)
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{
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        env->debug3 = T1;
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        RETURN();
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}
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void OPPROTO op_movl_debug3_im (void)
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{
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        env->debug3 = PARAM1;
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        RETURN();
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}
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void OPPROTO op_movl_T0_flags (void)
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{
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        T0 = env->pregs[PR_CCS];
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        RETURN();
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}
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void OPPROTO op_movl_flags_T0 (void)
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{
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        env->pregs[PR_CCS] = T0;
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        RETURN();
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}
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void OPPROTO op_movl_sreg_T0 (void)
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{
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        uint32_t srs;
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        srs = env->pregs[PR_SRS];
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        srs &= 3;
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        env->sregs[srs][PARAM1] = T0;
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        RETURN();
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}
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void OPPROTO op_movl_tlb_hi_T0 (void)
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{
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        uint32_t srs;
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        srs = env->pregs[PR_SRS];
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        if (srs == 1 || srs == 2)
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        {
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                /* Writes to tlb-hi write to mm_cause as a side effect.  */
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                env->sregs[SFR_RW_MM_TLB_HI] = T0;
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                env->sregs[SFR_R_MM_CAUSE] = T0;
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        }
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        RETURN();
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}
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void OPPROTO op_movl_tlb_lo_T0 (void)
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{
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        uint32_t srs;
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        env->pregs[PR_SRS] &= 3;
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        srs = env->pregs[PR_SRS];
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        if (srs == 1 || srs == 2)
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        {
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                uint32_t set;
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                uint32_t idx;
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                uint32_t lo, hi;
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                idx = set = env->sregs[SFR_RW_MM_TLB_SEL];
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                set >>= 4;
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                set &= 3;
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                idx &= 15;
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                /* We've just made a write to tlb_lo.  */
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                lo = env->sregs[SFR_RW_MM_TLB_LO];
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                /* Writes are done via r_mm_cause.  */
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                hi = env->sregs[SFR_R_MM_CAUSE];
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                env->tlbsets[srs - 1][set][idx].lo = lo;
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                env->tlbsets[srs - 1][set][idx].hi = hi;
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        }
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        RETURN();
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}
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void OPPROTO op_movl_T0_sreg (void)
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{
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        uint32_t srs;
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        env->pregs[PR_SRS] &= 3;
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        srs = env->pregs[PR_SRS];
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        if (srs == 1 || srs == 2)
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        {
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                uint32_t set;
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                uint32_t idx;
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                uint32_t lo, hi;
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                idx = set = env->sregs[SFR_RW_MM_TLB_SEL];
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                set >>= 4;
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                set &= 3;
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                idx &= 15;
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                /* Update the mirror regs.  */
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                hi = env->tlbsets[srs - 1][set][idx].hi;
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                lo = env->tlbsets[srs - 1][set][idx].lo;
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                env->sregs[SFR_RW_MM_TLB_HI] = hi;
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                env->sregs[SFR_RW_MM_TLB_LO] = lo;
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        }
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        T0 = env->sregs[srs][PARAM1];
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        RETURN();
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}
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void OPPROTO op_update_cc (void)
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{
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        env->cc_op = PARAM1;
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        env->cc_dest = PARAM2;
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        env->cc_src = PARAM3;
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        RETURN();
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}
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void OPPROTO op_update_cc_op (void)
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{
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        env->cc_op = PARAM1;
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        RETURN();
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}
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void OPPROTO op_update_cc_mask (void)
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{
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        env->cc_mask = PARAM1;
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        RETURN();
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}
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void OPPROTO op_update_cc_dest_T0 (void)
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{
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        env->cc_dest = T0;
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        RETURN();
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}
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void OPPROTO op_update_cc_result_T0 (void)
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{
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        env->cc_result = T0;
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        RETURN();
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}
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void OPPROTO op_update_cc_size_im (void)
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{
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        env->cc_size = PARAM1;
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        RETURN();
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}
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void OPPROTO op_update_cc_src_T1 (void)
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{
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        env->cc_src = T1;
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        RETURN();
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}
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void OPPROTO op_update_cc_x (void)
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{
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        env->cc_x_live = PARAM1;
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        env->cc_x = PARAM2;
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        RETURN();
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}
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void OPPROTO op_extb_T0_T0 (void)
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{
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        T0 = ((int8_t)T0);
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        RETURN();
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}
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void OPPROTO op_extb_T1_T0 (void)
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{
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        T1 = ((int8_t)T0);
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        RETURN();
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}
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void OPPROTO op_extb_T1_T1 (void)
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{
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        T1 = ((int8_t)T1);
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        RETURN();
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}
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void OPPROTO op_zextb_T0_T0 (void)
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{
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        T0 = ((uint8_t)T0);
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        RETURN();
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}
429 4fa551d7 ths
void OPPROTO op_zextb_T1_T0 (void)
430 4fa551d7 ths
{
431 4fa551d7 ths
        T1 = ((uint8_t)T0);
432 4fa551d7 ths
        RETURN();
433 4fa551d7 ths
}
434 4fa551d7 ths
void OPPROTO op_zextb_T1_T1 (void)
435 4fa551d7 ths
{
436 4fa551d7 ths
        T1 = ((uint8_t)T1);
437 4fa551d7 ths
        RETURN();
438 4fa551d7 ths
}
439 4fa551d7 ths
void OPPROTO op_extw_T0_T0 (void)
440 4fa551d7 ths
{
441 4fa551d7 ths
        T0 = ((int16_t)T0);
442 4fa551d7 ths
        RETURN();
443 4fa551d7 ths
}
444 4fa551d7 ths
void OPPROTO op_extw_T1_T0 (void)
445 4fa551d7 ths
{
446 4fa551d7 ths
        T1 = ((int16_t)T0);
447 4fa551d7 ths
        RETURN();
448 4fa551d7 ths
}
449 4fa551d7 ths
void OPPROTO op_extw_T1_T1 (void)
450 4fa551d7 ths
{
451 4fa551d7 ths
        T1 = ((int16_t)T1);
452 4fa551d7 ths
        RETURN();
453 4fa551d7 ths
}
454 4fa551d7 ths
455 4fa551d7 ths
void OPPROTO op_zextw_T0_T0 (void)
456 4fa551d7 ths
{
457 4fa551d7 ths
        T0 = ((uint16_t)T0);
458 4fa551d7 ths
        RETURN();
459 4fa551d7 ths
}
460 4fa551d7 ths
void OPPROTO op_zextw_T1_T0 (void)
461 4fa551d7 ths
{
462 4fa551d7 ths
        T1 = ((uint16_t)T0);
463 4fa551d7 ths
        RETURN();
464 4fa551d7 ths
}
465 4fa551d7 ths
466 4fa551d7 ths
void OPPROTO op_zextw_T1_T1 (void)
467 4fa551d7 ths
{
468 4fa551d7 ths
        T1 = ((uint16_t)T1);
469 4fa551d7 ths
        RETURN();
470 4fa551d7 ths
}
471 4fa551d7 ths
472 4fa551d7 ths
void OPPROTO op_movl_T0_im (void)
473 4fa551d7 ths
{
474 4fa551d7 ths
        T0 = PARAM1;
475 4fa551d7 ths
        RETURN();
476 4fa551d7 ths
}
477 4fa551d7 ths
void OPPROTO op_movl_T1_im (void)
478 4fa551d7 ths
{
479 4fa551d7 ths
        T1 = PARAM1;
480 4fa551d7 ths
        RETURN();
481 4fa551d7 ths
}
482 4fa551d7 ths
483 4fa551d7 ths
void OPPROTO op_addl_T0_im (void)
484 4fa551d7 ths
{
485 4fa551d7 ths
        T0 += PARAM1;
486 4fa551d7 ths
        RETURN();
487 4fa551d7 ths
}
488 4fa551d7 ths
489 4fa551d7 ths
void OPPROTO op_addl_T1_im (void)
490 4fa551d7 ths
{
491 4fa551d7 ths
        T1 += PARAM1;
492 4fa551d7 ths
        RETURN();
493 4fa551d7 ths
494 4fa551d7 ths
}
495 4fa551d7 ths
void OPPROTO op_subl_T0_im (void)
496 4fa551d7 ths
{
497 4fa551d7 ths
        T0 -= PARAM1;
498 4fa551d7 ths
        RETURN();
499 4fa551d7 ths
}
500 4fa551d7 ths
501 4fa551d7 ths
void OPPROTO op_addxl_T0_C (void)
502 4fa551d7 ths
{
503 9004627f edgar_igl
        if (env->pregs[PR_CCS] & X_FLAG)
504 9004627f edgar_igl
                T0 += !!(env->pregs[PR_CCS] & C_FLAG);
505 4fa551d7 ths
        RETURN();
506 4fa551d7 ths
}
507 4fa551d7 ths
void OPPROTO op_subxl_T0_C (void)
508 4fa551d7 ths
{
509 9004627f edgar_igl
        if (env->pregs[PR_CCS] & X_FLAG)
510 9004627f edgar_igl
                T0 -= !!(env->pregs[PR_CCS] & C_FLAG);
511 4fa551d7 ths
        RETURN();
512 4fa551d7 ths
}
513 4fa551d7 ths
void OPPROTO op_addl_T0_C (void)
514 4fa551d7 ths
{
515 9004627f edgar_igl
        T0 += !!(env->pregs[PR_CCS] & C_FLAG);
516 4fa551d7 ths
        RETURN();
517 4fa551d7 ths
}
518 4fa551d7 ths
void OPPROTO op_addl_T0_R (void)
519 4fa551d7 ths
{
520 9004627f edgar_igl
        T0 += !!(env->pregs[PR_CCS] & R_FLAG);
521 4fa551d7 ths
        RETURN();
522 4fa551d7 ths
}
523 4fa551d7 ths
524 4fa551d7 ths
void OPPROTO op_clr_R (void)
525 4fa551d7 ths
{
526 9004627f edgar_igl
        env->pregs[PR_CCS] &= ~R_FLAG;
527 4fa551d7 ths
        RETURN();
528 4fa551d7 ths
}
529 4fa551d7 ths
530 4fa551d7 ths
531 4fa551d7 ths
void OPPROTO op_andl_T0_im (void)
532 4fa551d7 ths
{
533 4fa551d7 ths
        T0 &= PARAM1;
534 4fa551d7 ths
        RETURN();
535 4fa551d7 ths
}
536 4fa551d7 ths
537 4fa551d7 ths
void OPPROTO op_andl_T1_im (void)
538 4fa551d7 ths
{
539 4fa551d7 ths
        T1 &= PARAM1;
540 4fa551d7 ths
        RETURN();
541 4fa551d7 ths
}
542 4fa551d7 ths
543 4fa551d7 ths
void OPPROTO op_movl_T0_T1 (void)
544 4fa551d7 ths
{
545 4fa551d7 ths
        T0 = T1;
546 4fa551d7 ths
        RETURN();
547 4fa551d7 ths
}
548 4fa551d7 ths
549 4fa551d7 ths
void OPPROTO op_swp_T0_T1 (void)
550 4fa551d7 ths
{
551 4fa551d7 ths
        T0 ^= T1;
552 4fa551d7 ths
        T1 ^= T0;
553 4fa551d7 ths
        T0 ^= T1;
554 4fa551d7 ths
        RETURN();
555 4fa551d7 ths
}
556 4fa551d7 ths
557 4fa551d7 ths
void OPPROTO op_movl_T1_T0 (void)
558 4fa551d7 ths
{
559 4fa551d7 ths
        T1 = T0;
560 4fa551d7 ths
        RETURN();
561 4fa551d7 ths
}
562 4fa551d7 ths
563 4fa551d7 ths
void OPPROTO op_movl_pc_T0 (void)
564 4fa551d7 ths
{
565 4fa551d7 ths
        env->pc = T0;
566 4fa551d7 ths
        RETURN();
567 4fa551d7 ths
}
568 4fa551d7 ths
569 4fa551d7 ths
void OPPROTO op_movl_T0_0 (void)
570 4fa551d7 ths
{
571 4fa551d7 ths
        T0 = 0;
572 4fa551d7 ths
        RETURN();
573 4fa551d7 ths
}
574 4fa551d7 ths
575 4fa551d7 ths
void OPPROTO op_addl_T0_T1 (void)
576 4fa551d7 ths
{
577 4fa551d7 ths
        T0 += T1;
578 4fa551d7 ths
        RETURN();
579 4fa551d7 ths
}
580 4fa551d7 ths
581 4fa551d7 ths
void OPPROTO op_subl_T0_T1 (void)
582 4fa551d7 ths
{
583 4fa551d7 ths
        T0 -= T1;
584 4fa551d7 ths
        RETURN();
585 4fa551d7 ths
}
586 4fa551d7 ths
587 4fa551d7 ths
void OPPROTO op_absl_T1_T1 (void)
588 4fa551d7 ths
{
589 4fa551d7 ths
        int32_t st = T1;
590 4fa551d7 ths
591 4fa551d7 ths
        T1 = st < 0 ? -st : st;
592 4fa551d7 ths
        RETURN();
593 4fa551d7 ths
}
594 4fa551d7 ths
595 4fa551d7 ths
void OPPROTO op_muls_T0_T1 (void)
596 4fa551d7 ths
{
597 4fa551d7 ths
        int64_t tmp, t0 ,t1;
598 4fa551d7 ths
599 4fa551d7 ths
        /* cast into signed values to make GCC sign extend these babies.  */
600 4fa551d7 ths
        t0 = (int32_t)T0;
601 4fa551d7 ths
        t1 = (int32_t)T1;
602 4fa551d7 ths
603 4fa551d7 ths
        tmp = t0 * t1;
604 4fa551d7 ths
        T0 = tmp & 0xffffffff;
605 9004627f edgar_igl
        env->pregs[PR_MOF] = tmp >> 32;
606 4fa551d7 ths
        RETURN();
607 4fa551d7 ths
}
608 4fa551d7 ths
609 4fa551d7 ths
void OPPROTO op_mulu_T0_T1 (void)
610 4fa551d7 ths
{
611 4fa551d7 ths
        uint64_t tmp, t0 ,t1;
612 4fa551d7 ths
        t0 = T0;
613 4fa551d7 ths
        t1 = T1;
614 4fa551d7 ths
615 4fa551d7 ths
        tmp = t0 * t1;
616 4fa551d7 ths
        T0 = tmp & 0xffffffff;
617 9004627f edgar_igl
        env->pregs[PR_MOF] = tmp >> 32;
618 4fa551d7 ths
        RETURN();
619 4fa551d7 ths
}
620 4fa551d7 ths
621 4fa551d7 ths
void OPPROTO op_dstep_T0_T1 (void)
622 4fa551d7 ths
{
623 4fa551d7 ths
        T0 <<= 1;
624 4fa551d7 ths
        if (T0 >= T1)
625 4fa551d7 ths
                T0 -= T1;
626 4fa551d7 ths
        RETURN();
627 4fa551d7 ths
}
628 4fa551d7 ths
629 4fa551d7 ths
void OPPROTO op_orl_T0_T1 (void)
630 4fa551d7 ths
{
631 4fa551d7 ths
        T0 |= T1;
632 4fa551d7 ths
        RETURN();
633 4fa551d7 ths
}
634 4fa551d7 ths
635 4fa551d7 ths
void OPPROTO op_andl_T0_T1 (void)
636 4fa551d7 ths
{
637 4fa551d7 ths
        T0 &= T1;
638 4fa551d7 ths
        RETURN();
639 4fa551d7 ths
}
640 4fa551d7 ths
641 4fa551d7 ths
void OPPROTO op_xorl_T0_T1 (void)
642 4fa551d7 ths
{
643 4fa551d7 ths
        T0 ^= T1;
644 4fa551d7 ths
        RETURN();
645 4fa551d7 ths
}
646 4fa551d7 ths
647 4fa551d7 ths
void OPPROTO op_lsll_T0_T1 (void)
648 4fa551d7 ths
{
649 4fa551d7 ths
        int s = T1;
650 4fa551d7 ths
        if (s > 31)
651 4fa551d7 ths
                T0 = 0;
652 4fa551d7 ths
        else
653 4fa551d7 ths
                T0 <<= s;
654 4fa551d7 ths
        RETURN();
655 4fa551d7 ths
}
656 4fa551d7 ths
657 4fa551d7 ths
void OPPROTO op_lsll_T0_im (void)
658 4fa551d7 ths
{
659 4fa551d7 ths
        T0 <<= PARAM1;
660 4fa551d7 ths
        RETURN();
661 4fa551d7 ths
}
662 4fa551d7 ths
663 4fa551d7 ths
void OPPROTO op_lsrl_T0_T1 (void)
664 4fa551d7 ths
{
665 4fa551d7 ths
        int s = T1;
666 4fa551d7 ths
        if (s > 31)
667 4fa551d7 ths
                T0 = 0;
668 4fa551d7 ths
        else
669 4fa551d7 ths
                T0 >>= s;
670 4fa551d7 ths
        RETURN();
671 4fa551d7 ths
}
672 4fa551d7 ths
673 4fa551d7 ths
/* Rely on GCC emitting an arithmetic shift for signed right shifts.  */
674 4fa551d7 ths
void OPPROTO op_asrl_T0_T1 (void)
675 4fa551d7 ths
{
676 4fa551d7 ths
        int s = T1;
677 4fa551d7 ths
        if (s > 31)
678 4fa551d7 ths
                T0 = T0 & 0x80000000 ? -1 : 0;
679 4fa551d7 ths
        else
680 4fa551d7 ths
                T0 = (int32_t)T0 >> s;
681 4fa551d7 ths
        RETURN();
682 4fa551d7 ths
}
683 4fa551d7 ths
684 4fa551d7 ths
void OPPROTO op_btst_T0_T1 (void)
685 4fa551d7 ths
{
686 4fa551d7 ths
        /* FIXME: clean this up.  */
687 4fa551d7 ths
688 4fa551d7 ths
        /* des ref:
689 4fa551d7 ths
           The N flag is set according to the selected bit in the dest reg.
690 4fa551d7 ths
           The Z flag is set if the selected bit and all bits to the right are
691 4fa551d7 ths
           zero.
692 bbaf29c7 edgar_igl
           The X flag is cleared.
693 bbaf29c7 edgar_igl
           Other flags are left untouched.
694 4fa551d7 ths
           The destination reg is not affected.*/
695 4fa551d7 ths
        unsigned int fz, sbit, bset, mask, masked_t0;
696 4fa551d7 ths
697 4fa551d7 ths
        sbit = T1 & 31;
698 4fa551d7 ths
        bset = !!(T0 & (1 << sbit));
699 4fa551d7 ths
        mask = sbit == 31 ? -1 : (1 << (sbit + 1)) - 1;
700 4fa551d7 ths
        masked_t0 = T0 & mask;
701 4fa551d7 ths
        fz = !(masked_t0 | bset);
702 bbaf29c7 edgar_igl
703 bbaf29c7 edgar_igl
        /* Clear the X, N and Z flags.  */
704 bbaf29c7 edgar_igl
        T0 = env->pregs[PR_CCS] & ~(X_FLAG | N_FLAG | Z_FLAG);
705 4fa551d7 ths
        /* Set the N and Z flags accordingly.  */
706 bbaf29c7 edgar_igl
        T0 |= (bset << 3) | (fz << 2);
707 4fa551d7 ths
        RETURN();
708 4fa551d7 ths
}
709 4fa551d7 ths
710 4fa551d7 ths
void OPPROTO op_bound_T0_T1 (void)
711 4fa551d7 ths
{
712 4fa551d7 ths
        if (T0 > T1)
713 4fa551d7 ths
                T0 = T1;
714 4fa551d7 ths
        RETURN();
715 4fa551d7 ths
}
716 4fa551d7 ths
717 4fa551d7 ths
void OPPROTO op_lz_T0_T1 (void)
718 4fa551d7 ths
{
719 941db528 ths
        T0 = clz32(T1);
720 4fa551d7 ths
        RETURN();
721 4fa551d7 ths
}
722 4fa551d7 ths
723 4fa551d7 ths
void OPPROTO op_negl_T0_T1 (void)
724 4fa551d7 ths
{
725 4fa551d7 ths
        T0 = -T1;
726 4fa551d7 ths
        RETURN();
727 4fa551d7 ths
}
728 4fa551d7 ths
729 4fa551d7 ths
void OPPROTO op_negl_T1_T1 (void)
730 4fa551d7 ths
{
731 4fa551d7 ths
        T1 = -T1;
732 4fa551d7 ths
        RETURN();
733 4fa551d7 ths
}
734 4fa551d7 ths
735 4fa551d7 ths
void OPPROTO op_not_T0_T0 (void)
736 4fa551d7 ths
{
737 4fa551d7 ths
        T0 = ~(T0);
738 4fa551d7 ths
        RETURN();
739 4fa551d7 ths
}
740 4fa551d7 ths
void OPPROTO op_not_T1_T1 (void)
741 4fa551d7 ths
{
742 4fa551d7 ths
        T1 = ~(T1);
743 4fa551d7 ths
        RETURN();
744 4fa551d7 ths
}
745 4fa551d7 ths
746 4fa551d7 ths
void OPPROTO op_swapw_T0_T0 (void)
747 4fa551d7 ths
{
748 4fa551d7 ths
        T0 = (T0 << 16) | ((T0 >> 16));
749 4fa551d7 ths
        RETURN();
750 4fa551d7 ths
}
751 4fa551d7 ths
752 4fa551d7 ths
void OPPROTO op_swapb_T0_T0 (void)
753 4fa551d7 ths
{
754 4fa551d7 ths
        T0 = ((T0 << 8) & 0xff00ff00) | ((T0 >> 8) & 0x00ff00ff);
755 4fa551d7 ths
        RETURN();
756 4fa551d7 ths
}
757 4fa551d7 ths
758 4fa551d7 ths
void OPPROTO op_swapr_T0_T0 (void)
759 4fa551d7 ths
{
760 4fa551d7 ths
        T0 = (((T0 << 7) & 0x80808080) |
761 4fa551d7 ths
              ((T0 << 5) & 0x40404040) |
762 4fa551d7 ths
              ((T0 << 3) & 0x20202020) |
763 4fa551d7 ths
              ((T0 << 1) & 0x10101010) |
764 4fa551d7 ths
              ((T0 >> 1) & 0x08080808) |
765 4fa551d7 ths
              ((T0 >> 3) & 0x04040404) |
766 4fa551d7 ths
              ((T0 >> 5) & 0x02020202) |
767 4fa551d7 ths
              ((T0 >> 7) & 0x01010101));
768 4fa551d7 ths
        RETURN();
769 4fa551d7 ths
}
770 4fa551d7 ths
771 4fa551d7 ths
void OPPROTO op_tst_cc_eq (void) {
772 9004627f edgar_igl
        uint32_t flags = env->pregs[PR_CCS];
773 4fa551d7 ths
        int z_set;
774 4fa551d7 ths
775 4fa551d7 ths
        z_set = !!(flags & Z_FLAG);
776 4fa551d7 ths
        T0 = z_set;
777 4fa551d7 ths
        RETURN();
778 4fa551d7 ths
}
779 4fa551d7 ths
780 4fa551d7 ths
void OPPROTO op_tst_cc_eq_fast (void) {
781 4fa551d7 ths
        T0 = !(env->cc_result);
782 4fa551d7 ths
        RETURN();
783 4fa551d7 ths
}
784 4fa551d7 ths
785 4fa551d7 ths
void OPPROTO op_tst_cc_ne (void) {
786 9004627f edgar_igl
        uint32_t flags = env->pregs[PR_CCS];
787 4fa551d7 ths
        int z_set;
788 4fa551d7 ths
789 4fa551d7 ths
        z_set = !!(flags & Z_FLAG);
790 4fa551d7 ths
        T0 = !z_set;
791 4fa551d7 ths
        RETURN();
792 4fa551d7 ths
}
793 4fa551d7 ths
void OPPROTO op_tst_cc_ne_fast (void) {
794 4fa551d7 ths
        T0 = !!(env->cc_result);
795 4fa551d7 ths
        RETURN();
796 4fa551d7 ths
}
797 4fa551d7 ths
798 4fa551d7 ths
void OPPROTO op_tst_cc_cc (void) {
799 9004627f edgar_igl
        uint32_t flags = env->pregs[PR_CCS];
800 4fa551d7 ths
        int c_set;
801 4fa551d7 ths
802 4fa551d7 ths
        c_set = !!(flags & C_FLAG);
803 4fa551d7 ths
        T0 = !c_set;
804 4fa551d7 ths
        RETURN();
805 4fa551d7 ths
}
806 4fa551d7 ths
void OPPROTO op_tst_cc_cs (void) {
807 9004627f edgar_igl
        uint32_t flags = env->pregs[PR_CCS];
808 4fa551d7 ths
        int c_set;
809 4fa551d7 ths
810 4fa551d7 ths
        c_set = !!(flags & C_FLAG);
811 4fa551d7 ths
        T0 = c_set;
812 4fa551d7 ths
        RETURN();
813 4fa551d7 ths
}
814 4fa551d7 ths
815 4fa551d7 ths
void OPPROTO op_tst_cc_vc (void) {
816 9004627f edgar_igl
        uint32_t flags = env->pregs[PR_CCS];
817 4fa551d7 ths
        int v_set;
818 4fa551d7 ths
819 4fa551d7 ths
        v_set = !!(flags & V_FLAG);
820 4fa551d7 ths
        T0 = !v_set;
821 4fa551d7 ths
        RETURN();
822 4fa551d7 ths
}
823 4fa551d7 ths
void OPPROTO op_tst_cc_vs (void) {
824 9004627f edgar_igl
        uint32_t flags = env->pregs[PR_CCS];
825 4fa551d7 ths
        int v_set;
826 4fa551d7 ths
827 4fa551d7 ths
        v_set = !!(flags & V_FLAG);
828 4fa551d7 ths
        T0 = v_set;
829 4fa551d7 ths
        RETURN();
830 4fa551d7 ths
}
831 4fa551d7 ths
void OPPROTO op_tst_cc_pl (void) {
832 9004627f edgar_igl
        uint32_t flags = env->pregs[PR_CCS];
833 4fa551d7 ths
        int n_set;
834 4fa551d7 ths
835 4fa551d7 ths
        n_set = !!(flags & N_FLAG);
836 4fa551d7 ths
        T0 = !n_set;
837 4fa551d7 ths
        RETURN();
838 4fa551d7 ths
}
839 4fa551d7 ths
void OPPROTO op_tst_cc_pl_fast (void) {
840 4fa551d7 ths
        T0 = ((int32_t)env->cc_result) >= 0;
841 4fa551d7 ths
        RETURN();
842 4fa551d7 ths
}
843 4fa551d7 ths
844 4fa551d7 ths
void OPPROTO op_tst_cc_mi (void) {
845 9004627f edgar_igl
        uint32_t flags = env->pregs[PR_CCS];
846 4fa551d7 ths
        int n_set;
847 4fa551d7 ths
848 4fa551d7 ths
        n_set = !!(flags & N_FLAG);
849 4fa551d7 ths
        T0 = n_set;
850 4fa551d7 ths
        RETURN();
851 4fa551d7 ths
}
852 4fa551d7 ths
void OPPROTO op_tst_cc_mi_fast (void) {
853 4fa551d7 ths
        T0 = ((int32_t)env->cc_result) < 0;
854 4fa551d7 ths
        RETURN();
855 4fa551d7 ths
}
856 4fa551d7 ths
857 4fa551d7 ths
void OPPROTO op_tst_cc_ls (void) {
858 9004627f edgar_igl
        uint32_t flags = env->pregs[PR_CCS];
859 4fa551d7 ths
        int c_set;
860 4fa551d7 ths
        int z_set;
861 4fa551d7 ths
862 4fa551d7 ths
        c_set = !!(flags & C_FLAG);
863 4fa551d7 ths
        z_set = !!(flags & Z_FLAG);
864 4fa551d7 ths
        T0 = c_set || z_set;
865 4fa551d7 ths
        RETURN();
866 4fa551d7 ths
}
867 4fa551d7 ths
void OPPROTO op_tst_cc_hi (void) {
868 9004627f edgar_igl
        uint32_t flags = env->pregs[PR_CCS];
869 4fa551d7 ths
        int z_set;
870 4fa551d7 ths
        int c_set;
871 4fa551d7 ths
872 4fa551d7 ths
        z_set = !!(flags & Z_FLAG);
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        c_set = !!(flags & C_FLAG);
874 4fa551d7 ths
        T0 = !c_set && !z_set;
875 4fa551d7 ths
        RETURN();
876 4fa551d7 ths
877 4fa551d7 ths
}
878 4fa551d7 ths
879 4fa551d7 ths
void OPPROTO op_tst_cc_ge (void) {
880 9004627f edgar_igl
        uint32_t flags = env->pregs[PR_CCS];
881 4fa551d7 ths
        int n_set;
882 4fa551d7 ths
        int v_set;
883 4fa551d7 ths
884 4fa551d7 ths
        n_set = !!(flags & N_FLAG);
885 4fa551d7 ths
        v_set = !!(flags & V_FLAG);
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        T0 = (n_set && v_set) || (!n_set && !v_set);
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        RETURN();
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}
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890 4fa551d7 ths
void OPPROTO op_tst_cc_ge_fast (void) {
891 4fa551d7 ths
        T0 = ((int32_t)env->cc_src < (int32_t)env->cc_dest);
892 4fa551d7 ths
        RETURN();
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}
894 4fa551d7 ths
895 4fa551d7 ths
void OPPROTO op_tst_cc_lt (void) {
896 9004627f edgar_igl
        uint32_t flags = env->pregs[PR_CCS];
897 4fa551d7 ths
        int n_set;
898 4fa551d7 ths
        int v_set;
899 4fa551d7 ths
900 4fa551d7 ths
        n_set = !!(flags & N_FLAG);
901 4fa551d7 ths
        v_set = !!(flags & V_FLAG);
902 4fa551d7 ths
        T0 = (n_set && !v_set) || (!n_set && v_set);
903 4fa551d7 ths
        RETURN();
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}
905 4fa551d7 ths
906 4fa551d7 ths
void OPPROTO op_tst_cc_gt (void) {
907 9004627f edgar_igl
        uint32_t flags = env->pregs[PR_CCS];
908 4fa551d7 ths
        int n_set;
909 4fa551d7 ths
        int v_set;
910 4fa551d7 ths
        int z_set;
911 4fa551d7 ths
912 4fa551d7 ths
        n_set = !!(flags & N_FLAG);
913 4fa551d7 ths
        v_set = !!(flags & V_FLAG);
914 4fa551d7 ths
        z_set = !!(flags & Z_FLAG);
915 4fa551d7 ths
        T0 = (n_set && v_set && !z_set)
916 4fa551d7 ths
                || (!n_set && !v_set && !z_set);
917 4fa551d7 ths
        RETURN();
918 4fa551d7 ths
}
919 4fa551d7 ths
920 4fa551d7 ths
void OPPROTO op_tst_cc_le (void) {
921 9004627f edgar_igl
        uint32_t flags = env->pregs[PR_CCS];
922 4fa551d7 ths
        int n_set;
923 4fa551d7 ths
        int v_set;
924 4fa551d7 ths
        int z_set;
925 4fa551d7 ths
926 4fa551d7 ths
        n_set = !!(flags & N_FLAG);
927 4fa551d7 ths
        v_set = !!(flags & V_FLAG);
928 4fa551d7 ths
        z_set = !!(flags & Z_FLAG);
929 4fa551d7 ths
        T0 = z_set || (n_set && !v_set) || (!n_set && v_set);
930 4fa551d7 ths
        RETURN();
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}
932 4fa551d7 ths
933 4fa551d7 ths
void OPPROTO op_tst_cc_p (void) {
934 9004627f edgar_igl
        uint32_t flags = env->pregs[PR_CCS];
935 4fa551d7 ths
        int p_set;
936 4fa551d7 ths
937 4fa551d7 ths
        p_set = !!(flags & P_FLAG);
938 4fa551d7 ths
        T0 = p_set;
939 4fa551d7 ths
        RETURN();
940 4fa551d7 ths
}
941 4fa551d7 ths
942 4fa551d7 ths
/* Evaluate the if the branch should be taken or not. Needs to be done in
943 4fa551d7 ths
   the original sequence. The acutal branch is rescheduled to right after the
944 4fa551d7 ths
   delay-slot.  */
945 4fa551d7 ths
void OPPROTO op_evaluate_bcc (void)
946 4fa551d7 ths
{
947 4fa551d7 ths
        env->btaken = T0;
948 4fa551d7 ths
        RETURN();
949 4fa551d7 ths
}
950 4fa551d7 ths
951 4fa551d7 ths
/* this one is used on every alu op, optimize it!.  */
952 4fa551d7 ths
void OPPROTO op_goto_if_not_x (void)
953 4fa551d7 ths
{
954 9004627f edgar_igl
        if (env->pregs[PR_CCS] & X_FLAG)
955 4fa551d7 ths
                GOTO_LABEL_PARAM(1);
956 4fa551d7 ths
        RETURN();
957 4fa551d7 ths
}
958 4fa551d7 ths
959 4fa551d7 ths
void OPPROTO op_cc_jmp (void)
960 4fa551d7 ths
{
961 4fa551d7 ths
        if (env->btaken)
962 4fa551d7 ths
                env->pc = PARAM1;
963 4fa551d7 ths
        else
964 4fa551d7 ths
                env->pc = PARAM2;
965 4fa551d7 ths
        RETURN();
966 4fa551d7 ths
}
967 4fa551d7 ths
968 4fa551d7 ths
void OPPROTO op_cc_ngoto (void)
969 4fa551d7 ths
{
970 4fa551d7 ths
        if (!env->btaken)
971 4fa551d7 ths
                GOTO_LABEL_PARAM(1);
972 4fa551d7 ths
        RETURN();
973 4fa551d7 ths
}
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975 4fa551d7 ths
void OPPROTO op_movl_btarget_T0 (void)
976 4fa551d7 ths
{
977 4fa551d7 ths
        env->btarget = T0;
978 4fa551d7 ths
        RETURN();
979 4fa551d7 ths
}
980 4fa551d7 ths
981 57fec1fe bellard
void OPPROTO op_jmp1 (void)
982 4fa551d7 ths
{
983 4fa551d7 ths
        env->pc = env->btarget;
984 4fa551d7 ths
        RETURN();
985 4fa551d7 ths
}