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/*
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* SH4 emulation
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*
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* Copyright (c) 2005 Samuel Tardieu
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include "exec.h" |
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|
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static inline void set_t(void) |
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{ |
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env->sr |= SR_T; |
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} |
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|
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static inline void clr_t(void) |
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{ |
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env->sr &= ~SR_T; |
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} |
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|
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static inline void cond_t(int cond) |
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{ |
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if (cond)
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set_t(); |
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else
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clr_t(); |
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} |
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|
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void OPPROTO op_movl_imm_T0(void) |
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{ |
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T0 = (uint32_t) PARAM1; |
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RETURN(); |
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} |
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|
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void OPPROTO op_movl_imm_T1(void) |
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{ |
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T1 = (uint32_t) PARAM1; |
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RETURN(); |
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} |
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|
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void OPPROTO op_cmp_eq_imm_T0(void) |
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{ |
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cond_t((int32_t) T0 == (int32_t) PARAM1); |
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RETURN(); |
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} |
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|
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void OPPROTO op_cmd_eq_T0_T1(void) |
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{ |
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cond_t(T0 == T1); |
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RETURN(); |
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} |
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|
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void OPPROTO op_cmd_hs_T0_T1(void) |
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{ |
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cond_t((uint32_t) T0 <= (uint32_t) T1); |
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RETURN(); |
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} |
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|
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void OPPROTO op_cmd_ge_T0_T1(void) |
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{ |
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cond_t((int32_t) T0 <= (int32_t) T1); |
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RETURN(); |
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} |
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|
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void OPPROTO op_cmd_hi_T0_T1(void) |
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{ |
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cond_t((uint32_t) T0 < (uint32_t) T1); |
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RETURN(); |
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} |
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|
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void OPPROTO op_cmd_gt_T0_T1(void) |
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{ |
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cond_t((int32_t) T0 < (int32_t) T1); |
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RETURN(); |
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} |
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void OPPROTO op_not_T0(void) |
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{ |
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T0 = ~T0; |
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RETURN(); |
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} |
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|
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void OPPROTO op_bf_s(void) |
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{ |
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env->delayed_pc = PARAM1; |
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if (!(env->sr & SR_T)) {
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env->flags |= DELAY_SLOT_TRUE; |
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} |
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RETURN(); |
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} |
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void OPPROTO op_bt_s(void) |
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{ |
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env->delayed_pc = PARAM1; |
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if (env->sr & SR_T) {
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env->flags |= DELAY_SLOT_TRUE; |
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} |
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RETURN(); |
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} |
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|
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void OPPROTO op_store_flags(void) |
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{ |
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env->flags &= DELAY_SLOT_TRUE; |
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env->flags |= PARAM1; |
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RETURN(); |
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} |
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|
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void OPPROTO op_bra(void) |
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{ |
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env->delayed_pc = PARAM1; |
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RETURN(); |
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} |
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|
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void OPPROTO op_braf_T0(void) |
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{ |
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env->delayed_pc = PARAM1 + T0; |
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RETURN(); |
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} |
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|
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void OPPROTO op_bsr(void) |
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{ |
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env->pr = PARAM1; |
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env->delayed_pc = PARAM2; |
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RETURN(); |
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} |
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void OPPROTO op_bsrf_T0(void) |
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{ |
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env->pr = PARAM1; |
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env->delayed_pc = PARAM1 + T0; |
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RETURN(); |
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} |
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void OPPROTO op_jsr_T0(void) |
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{ |
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env->pr = PARAM1; |
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env->delayed_pc = T0; |
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RETURN(); |
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} |
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void OPPROTO op_rts(void) |
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{ |
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env->delayed_pc = env->pr; |
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RETURN(); |
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} |
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void OPPROTO op_addl_imm_T0(void) |
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{ |
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T0 += PARAM1; |
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RETURN(); |
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} |
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void OPPROTO op_addl_imm_T1(void) |
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{ |
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T1 += PARAM1; |
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RETURN(); |
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} |
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void OPPROTO op_clrmac(void) |
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{ |
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env->mach = env->macl = 0;
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RETURN(); |
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} |
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void OPPROTO op_clrs(void) |
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{ |
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env->sr &= ~SR_S; |
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RETURN(); |
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} |
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void OPPROTO op_clrt(void) |
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{ |
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env->sr &= ~SR_T; |
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RETURN(); |
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} |
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void OPPROTO op_sets(void) |
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{ |
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env->sr |= SR_S; |
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RETURN(); |
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} |
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void OPPROTO op_sett(void) |
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{ |
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env->sr |= SR_T; |
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RETURN(); |
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} |
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void OPPROTO op_frchg(void) |
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{ |
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env->fpscr ^= FPSCR_FR; |
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RETURN(); |
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} |
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void OPPROTO op_fschg(void) |
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{ |
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env->fpscr ^= FPSCR_SZ; |
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RETURN(); |
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} |
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void OPPROTO op_rte(void) |
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{ |
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env->sr = env->ssr; |
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env->delayed_pc = env->spc; |
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RETURN(); |
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} |
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void OPPROTO op_swapb_T0(void) |
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{ |
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T0 = (T0 & 0xffff0000) | ((T0 & 0xff) << 8) | ((T0 >> 8) & 0xff); |
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RETURN(); |
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} |
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void OPPROTO op_swapw_T0(void) |
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{ |
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T0 = ((T0 & 0xffff) << 16) | ((T0 >> 16) & 0xffff); |
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RETURN(); |
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} |
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void OPPROTO op_xtrct_T0_T1(void) |
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{ |
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T1 = ((T0 & 0xffff) << 16) | ((T1 >> 16) & 0xffff); |
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RETURN(); |
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} |
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void OPPROTO op_add_T0_T1(void) |
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{ |
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T1 += T0; |
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RETURN(); |
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} |
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void OPPROTO op_addc_T0_T1(void) |
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{ |
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helper_addc_T0_T1(); |
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RETURN(); |
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} |
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void OPPROTO op_addv_T0_T1(void) |
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{ |
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helper_addv_T0_T1(); |
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RETURN(); |
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} |
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void OPPROTO op_cmp_eq_T0_T1(void) |
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{ |
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cond_t(T1 == T0); |
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RETURN(); |
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} |
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void OPPROTO op_cmp_ge_T0_T1(void) |
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{ |
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cond_t((int32_t) T1 >= (int32_t) T0); |
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RETURN(); |
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} |
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void OPPROTO op_cmp_gt_T0_T1(void) |
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{ |
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cond_t((int32_t) T1 > (int32_t) T0); |
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RETURN(); |
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} |
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void OPPROTO op_cmp_hi_T0_T1(void) |
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{ |
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cond_t((uint32_t) T1 > (uint32_t) T0); |
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RETURN(); |
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} |
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void OPPROTO op_cmp_hs_T0_T1(void) |
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{ |
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cond_t((uint32_t) T1 >= (uint32_t) T0); |
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RETURN(); |
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} |
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void OPPROTO op_cmp_str_T0_T1(void) |
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{ |
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cond_t((T0 & 0x000000ff) == (T1 & 0x000000ff) || |
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(T0 & 0x0000ff00) == (T1 & 0x0000ff00) || |
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(T0 & 0x00ff0000) == (T1 & 0x00ff0000) || |
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(T0 & 0xff000000) == (T1 & 0xff000000)); |
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RETURN(); |
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} |
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void OPPROTO op_tst_T0_T1(void) |
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{ |
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cond_t((T1 & T0) == 0);
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RETURN(); |
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} |
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void OPPROTO op_div0s_T0_T1(void) |
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{ |
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if (T1 & 0x80000000) |
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env->sr |= SR_Q; |
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else
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env->sr &= ~SR_Q; |
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if (T0 & 0x80000000) |
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env->sr |= SR_M; |
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else
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env->sr &= ~SR_M; |
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cond_t((T1 ^ T0) & 0x80000000);
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RETURN(); |
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} |
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void OPPROTO op_div0u(void) |
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{ |
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env->sr &= ~(SR_M | SR_Q | SR_T); |
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RETURN(); |
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} |
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void OPPROTO op_div1_T0_T1(void) |
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{ |
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helper_div1_T0_T1(); |
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RETURN(); |
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} |
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void OPPROTO op_dmulsl_T0_T1(void) |
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{ |
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helper_dmulsl_T0_T1(); |
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RETURN(); |
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} |
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|
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void OPPROTO op_dmulul_T0_T1(void) |
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{ |
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helper_dmulul_T0_T1(); |
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RETURN(); |
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} |
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|
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void OPPROTO op_macl_T0_T1(void) |
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{ |
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helper_macl_T0_T1(); |
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RETURN(); |
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} |
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|
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void OPPROTO op_macw_T0_T1(void) |
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{ |
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helper_macw_T0_T1(); |
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RETURN(); |
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} |
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|
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void OPPROTO op_mull_T0_T1(void) |
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{ |
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env->macl = (T0 * T1) & 0xffffffff;
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RETURN(); |
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} |
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|
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void OPPROTO op_mulsw_T0_T1(void) |
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{ |
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env->macl = (int32_t)(int16_t) T0 *(int32_t)(int16_t) T1; |
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RETURN(); |
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} |
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|
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void OPPROTO op_muluw_T0_T1(void) |
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{ |
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env->macl = (uint32_t)(uint16_t) T0 *(uint32_t)(uint16_t) T1; |
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RETURN(); |
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} |
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|
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void OPPROTO op_neg_T0(void) |
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{ |
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T0 = -T0; |
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RETURN(); |
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} |
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|
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void OPPROTO op_negc_T0(void) |
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{ |
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helper_negc_T0(); |
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RETURN(); |
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} |
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|
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void OPPROTO op_shad_T0_T1(void) |
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{ |
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if ((T0 & 0x80000000) == 0) |
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T1 <<= (T0 & 0x1f);
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else if ((T0 & 0x1f) == 0) |
385 |
T1 = (T1 & 0x80000000)? 0xffffffff : 0; |
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else
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T1 = ((int32_t) T1) >> ((~T0 & 0x1f) + 1); |
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RETURN(); |
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} |
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|
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void OPPROTO op_shld_T0_T1(void) |
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{ |
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if ((T0 & 0x80000000) == 0) |
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T1 <<= (T0 & 0x1f);
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else if ((T0 & 0x1f) == 0) |
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T1 = 0;
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else
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T1 = ((uint32_t) T1) >> ((~T0 & 0x1f) + 1); |
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RETURN(); |
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} |
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|
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void OPPROTO op_subc_T0_T1(void) |
403 |
{ |
404 |
helper_subc_T0_T1(); |
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RETURN(); |
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} |
407 |
|
408 |
void OPPROTO op_subv_T0_T1(void) |
409 |
{ |
410 |
helper_subv_T0_T1(); |
411 |
RETURN(); |
412 |
} |
413 |
|
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void OPPROTO op_trapa(void) |
415 |
{ |
416 |
env->tra = PARAM1 << 2;
|
417 |
env->exception_index = 0x160;
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418 |
do_raise_exception(); |
419 |
RETURN(); |
420 |
} |
421 |
|
422 |
void OPPROTO op_cmp_pl_T0(void) |
423 |
{ |
424 |
cond_t((int32_t) T0 > 0);
|
425 |
RETURN(); |
426 |
} |
427 |
|
428 |
void OPPROTO op_cmp_pz_T0(void) |
429 |
{ |
430 |
cond_t((int32_t) T0 >= 0);
|
431 |
RETURN(); |
432 |
} |
433 |
|
434 |
void OPPROTO op_jmp_T0(void) |
435 |
{ |
436 |
env->delayed_pc = T0; |
437 |
RETURN(); |
438 |
} |
439 |
|
440 |
void OPPROTO op_movl_rN_rN(void) |
441 |
{ |
442 |
env->gregs[PARAM2] = env->gregs[PARAM1]; |
443 |
RETURN(); |
444 |
} |
445 |
|
446 |
void OPPROTO op_ldcl_rMplus_rN_bank(void) |
447 |
{ |
448 |
env->gregs[PARAM2] = env->gregs[PARAM1]; |
449 |
env->gregs[PARAM1] += 4;
|
450 |
RETURN(); |
451 |
} |
452 |
|
453 |
void OPPROTO op_ldc_T0_sr(void) |
454 |
{ |
455 |
env->sr = T0 & 0x700083f3;
|
456 |
RETURN(); |
457 |
} |
458 |
|
459 |
void OPPROTO op_stc_sr_T0(void) |
460 |
{ |
461 |
T0 = env->sr; |
462 |
RETURN(); |
463 |
} |
464 |
|
465 |
#define LDSTOPS(target,load,store) \
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466 |
void OPPROTO op_##load##_T0_##target (void) \ |
467 |
{ env ->target = T0; RETURN(); \ |
468 |
} \ |
469 |
void OPPROTO op_##store##_##target##_T0 (void) \ |
470 |
{ T0 = env->target; RETURN(); \ |
471 |
} \ |
472 |
|
473 |
LDSTOPS(gbr, ldc, stc) |
474 |
LDSTOPS(vbr, ldc, stc) |
475 |
LDSTOPS(ssr, ldc, stc) |
476 |
LDSTOPS(spc, ldc, stc) |
477 |
LDSTOPS(sgr, ldc, stc) |
478 |
LDSTOPS(dbr, ldc, stc) |
479 |
LDSTOPS(mach, lds, sts) |
480 |
LDSTOPS(macl, lds, sts) |
481 |
LDSTOPS(pr, lds, sts) |
482 |
LDSTOPS(fpul, lds, sts) |
483 |
|
484 |
void OPPROTO op_lds_T0_fpscr(void) |
485 |
{ |
486 |
env->fpscr = T0 & 0x003fffff;
|
487 |
env->fp_status.float_rounding_mode = T0 & 0x01 ?
|
488 |
float_round_to_zero : float_round_nearest_even; |
489 |
|
490 |
RETURN(); |
491 |
} |
492 |
|
493 |
void OPPROTO op_sts_fpscr_T0(void) |
494 |
{ |
495 |
T0 = env->fpscr & 0x003fffff;
|
496 |
RETURN(); |
497 |
} |
498 |
|
499 |
void OPPROTO op_movt_rN(void) |
500 |
{ |
501 |
env->gregs[PARAM1] = env->sr & SR_T; |
502 |
RETURN(); |
503 |
} |
504 |
|
505 |
void OPPROTO op_rotcl_Rn(void) |
506 |
{ |
507 |
helper_rotcl(&env->gregs[PARAM1]); |
508 |
RETURN(); |
509 |
} |
510 |
|
511 |
void OPPROTO op_rotcr_Rn(void) |
512 |
{ |
513 |
helper_rotcr(&env->gregs[PARAM1]); |
514 |
RETURN(); |
515 |
} |
516 |
|
517 |
void OPPROTO op_rotl_Rn(void) |
518 |
{ |
519 |
cond_t(env->gregs[PARAM1] & 0x80000000);
|
520 |
env->gregs[PARAM1] = (env->gregs[PARAM1] << 1) | (env->sr & SR_T);
|
521 |
RETURN(); |
522 |
} |
523 |
|
524 |
void OPPROTO op_rotr_Rn(void) |
525 |
{ |
526 |
cond_t(env->gregs[PARAM1] & 1);
|
527 |
env->gregs[PARAM1] = (env->gregs[PARAM1] >> 1) |
|
528 |
((env->sr & SR_T) ? 0x80000000 : 0); |
529 |
RETURN(); |
530 |
} |
531 |
|
532 |
void OPPROTO op_shal_Rn(void) |
533 |
{ |
534 |
cond_t(env->gregs[PARAM1] & 0x80000000);
|
535 |
env->gregs[PARAM1] <<= 1;
|
536 |
RETURN(); |
537 |
} |
538 |
|
539 |
void OPPROTO op_shar_Rn(void) |
540 |
{ |
541 |
cond_t(env->gregs[PARAM1] & 1);
|
542 |
*(int32_t *)&env->gregs[PARAM1] >>= 1;
|
543 |
RETURN(); |
544 |
} |
545 |
|
546 |
void OPPROTO op_shlr_Rn(void) |
547 |
{ |
548 |
cond_t(env->gregs[PARAM1] & 1);
|
549 |
env->gregs[PARAM1] >>= 1;
|
550 |
RETURN(); |
551 |
} |
552 |
|
553 |
void OPPROTO op_shll2_Rn(void) |
554 |
{ |
555 |
env->gregs[PARAM1] <<= 2;
|
556 |
RETURN(); |
557 |
} |
558 |
|
559 |
void OPPROTO op_shll8_Rn(void) |
560 |
{ |
561 |
env->gregs[PARAM1] <<= 8;
|
562 |
RETURN(); |
563 |
} |
564 |
|
565 |
void OPPROTO op_shll16_Rn(void) |
566 |
{ |
567 |
env->gregs[PARAM1] <<= 16;
|
568 |
RETURN(); |
569 |
} |
570 |
|
571 |
void OPPROTO op_shlr2_Rn(void) |
572 |
{ |
573 |
env->gregs[PARAM1] >>= 2;
|
574 |
RETURN(); |
575 |
} |
576 |
|
577 |
void OPPROTO op_shlr8_Rn(void) |
578 |
{ |
579 |
env->gregs[PARAM1] >>= 8;
|
580 |
RETURN(); |
581 |
} |
582 |
|
583 |
void OPPROTO op_shlr16_Rn(void) |
584 |
{ |
585 |
env->gregs[PARAM1] >>= 16;
|
586 |
RETURN(); |
587 |
} |
588 |
|
589 |
void OPPROTO op_tasb_rN(void) |
590 |
{ |
591 |
cond_t(*(int8_t *) env->gregs[PARAM1] == 0);
|
592 |
*(int8_t *) env->gregs[PARAM1] |= 0x80;
|
593 |
RETURN(); |
594 |
} |
595 |
|
596 |
void OPPROTO op_movl_T0_rN(void) |
597 |
{ |
598 |
env->gregs[PARAM1] = T0; |
599 |
RETURN(); |
600 |
} |
601 |
|
602 |
void OPPROTO op_movl_T1_rN(void) |
603 |
{ |
604 |
env->gregs[PARAM1] = T1; |
605 |
RETURN(); |
606 |
} |
607 |
|
608 |
void OPPROTO op_movb_rN_T0(void) |
609 |
{ |
610 |
T0 = (int32_t) (int8_t) (env->gregs[PARAM1] & 0xff);
|
611 |
RETURN(); |
612 |
} |
613 |
|
614 |
void OPPROTO op_movub_rN_T0(void) |
615 |
{ |
616 |
T0 = env->gregs[PARAM1] & 0xff;
|
617 |
RETURN(); |
618 |
} |
619 |
|
620 |
void OPPROTO op_movw_rN_T0(void) |
621 |
{ |
622 |
T0 = (int32_t) (int16_t) (env->gregs[PARAM1] & 0xffff);
|
623 |
RETURN(); |
624 |
} |
625 |
|
626 |
void OPPROTO op_movuw_rN_T0(void) |
627 |
{ |
628 |
T0 = env->gregs[PARAM1] & 0xffff;
|
629 |
RETURN(); |
630 |
} |
631 |
|
632 |
void OPPROTO op_movl_rN_T0(void) |
633 |
{ |
634 |
T0 = env->gregs[PARAM1]; |
635 |
RETURN(); |
636 |
} |
637 |
|
638 |
void OPPROTO op_movb_rN_T1(void) |
639 |
{ |
640 |
T1 = (int32_t) (int8_t) (env->gregs[PARAM1] & 0xff);
|
641 |
RETURN(); |
642 |
} |
643 |
|
644 |
void OPPROTO op_movub_rN_T1(void) |
645 |
{ |
646 |
T1 = env->gregs[PARAM1] & 0xff;
|
647 |
RETURN(); |
648 |
} |
649 |
|
650 |
void OPPROTO op_movw_rN_T1(void) |
651 |
{ |
652 |
T1 = (int32_t) (int16_t) (env->gregs[PARAM1] & 0xffff);
|
653 |
RETURN(); |
654 |
} |
655 |
|
656 |
void OPPROTO op_movuw_rN_T1(void) |
657 |
{ |
658 |
T1 = env->gregs[PARAM1] & 0xffff;
|
659 |
RETURN(); |
660 |
} |
661 |
|
662 |
void OPPROTO op_movl_rN_T1(void) |
663 |
{ |
664 |
T1 = env->gregs[PARAM1]; |
665 |
RETURN(); |
666 |
} |
667 |
|
668 |
void OPPROTO op_movl_imm_rN(void) |
669 |
{ |
670 |
env->gregs[PARAM2] = PARAM1; |
671 |
RETURN(); |
672 |
} |
673 |
|
674 |
void OPPROTO op_fmov_frN_FT0(void) |
675 |
{ |
676 |
FT0 = env->fregs[PARAM1]; |
677 |
RETURN(); |
678 |
} |
679 |
|
680 |
void OPPROTO op_fmov_drN_DT0(void) |
681 |
{ |
682 |
CPU_DoubleU d; |
683 |
|
684 |
d.l.upper = *(uint32_t *)&env->fregs[PARAM1]; |
685 |
d.l.lower = *(uint32_t *)&env->fregs[PARAM1 + 1];
|
686 |
DT0 = d.d; |
687 |
RETURN(); |
688 |
} |
689 |
|
690 |
void OPPROTO op_fmov_frN_FT1(void) |
691 |
{ |
692 |
FT1 = env->fregs[PARAM1]; |
693 |
RETURN(); |
694 |
} |
695 |
|
696 |
void OPPROTO op_fmov_drN_DT1(void) |
697 |
{ |
698 |
CPU_DoubleU d; |
699 |
|
700 |
d.l.upper = *(uint32_t *)&env->fregs[PARAM1]; |
701 |
d.l.lower = *(uint32_t *)&env->fregs[PARAM1 + 1];
|
702 |
DT1 = d.d; |
703 |
RETURN(); |
704 |
} |
705 |
|
706 |
void OPPROTO op_fmov_FT0_frN(void) |
707 |
{ |
708 |
env->fregs[PARAM1] = FT0; |
709 |
RETURN(); |
710 |
} |
711 |
|
712 |
void OPPROTO op_fmov_DT0_drN(void) |
713 |
{ |
714 |
CPU_DoubleU d; |
715 |
|
716 |
d.d = DT0; |
717 |
*(uint32_t *)&env->fregs[PARAM1] = d.l.upper; |
718 |
*(uint32_t *)&env->fregs[PARAM1 + 1] = d.l.lower;
|
719 |
RETURN(); |
720 |
} |
721 |
|
722 |
void OPPROTO op_fadd_FT(void) |
723 |
{ |
724 |
FT0 = float32_add(FT0, FT1, &env->fp_status); |
725 |
RETURN(); |
726 |
} |
727 |
|
728 |
void OPPROTO op_fadd_DT(void) |
729 |
{ |
730 |
DT0 = float64_add(DT0, DT1, &env->fp_status); |
731 |
RETURN(); |
732 |
} |
733 |
|
734 |
void OPPROTO op_fsub_FT(void) |
735 |
{ |
736 |
FT0 = float32_sub(FT0, FT1, &env->fp_status); |
737 |
RETURN(); |
738 |
} |
739 |
|
740 |
void OPPROTO op_fsub_DT(void) |
741 |
{ |
742 |
DT0 = float64_sub(DT0, DT1, &env->fp_status); |
743 |
RETURN(); |
744 |
} |
745 |
|
746 |
void OPPROTO op_fmul_FT(void) |
747 |
{ |
748 |
FT0 = float32_mul(FT0, FT1, &env->fp_status); |
749 |
RETURN(); |
750 |
} |
751 |
|
752 |
void OPPROTO op_fmul_DT(void) |
753 |
{ |
754 |
DT0 = float64_mul(DT0, DT1, &env->fp_status); |
755 |
RETURN(); |
756 |
} |
757 |
|
758 |
void OPPROTO op_fdiv_FT(void) |
759 |
{ |
760 |
FT0 = float32_div(FT0, FT1, &env->fp_status); |
761 |
RETURN(); |
762 |
} |
763 |
|
764 |
void OPPROTO op_fdiv_DT(void) |
765 |
{ |
766 |
DT0 = float64_div(DT0, DT1, &env->fp_status); |
767 |
RETURN(); |
768 |
} |
769 |
|
770 |
void OPPROTO op_fcmp_eq_FT(void) |
771 |
{ |
772 |
cond_t(float32_compare(FT0, FT1, &env->fp_status) == 0);
|
773 |
RETURN(); |
774 |
} |
775 |
|
776 |
void OPPROTO op_fcmp_eq_DT(void) |
777 |
{ |
778 |
cond_t(float64_compare(DT0, DT1, &env->fp_status) == 0);
|
779 |
RETURN(); |
780 |
} |
781 |
|
782 |
void OPPROTO op_fcmp_gt_FT(void) |
783 |
{ |
784 |
cond_t(float32_compare(FT0, FT1, &env->fp_status) == 1);
|
785 |
RETURN(); |
786 |
} |
787 |
|
788 |
void OPPROTO op_fcmp_gt_DT(void) |
789 |
{ |
790 |
cond_t(float64_compare(DT0, DT1, &env->fp_status) == 1);
|
791 |
RETURN(); |
792 |
} |
793 |
|
794 |
void OPPROTO op_float_FT(void) |
795 |
{ |
796 |
FT0 = int32_to_float32(env->fpul, &env->fp_status); |
797 |
RETURN(); |
798 |
} |
799 |
|
800 |
void OPPROTO op_float_DT(void) |
801 |
{ |
802 |
DT0 = int32_to_float64(env->fpul, &env->fp_status); |
803 |
RETURN(); |
804 |
} |
805 |
|
806 |
void OPPROTO op_ftrc_FT(void) |
807 |
{ |
808 |
env->fpul = float32_to_int32_round_to_zero(FT0, &env->fp_status); |
809 |
RETURN(); |
810 |
} |
811 |
|
812 |
void OPPROTO op_ftrc_DT(void) |
813 |
{ |
814 |
env->fpul = float64_to_int32_round_to_zero(DT0, &env->fp_status); |
815 |
RETURN(); |
816 |
} |
817 |
|
818 |
void OPPROTO op_fneg_frN(void) |
819 |
{ |
820 |
env->fregs[PARAM1] = float32_chs(env->fregs[PARAM1]); |
821 |
RETURN(); |
822 |
} |
823 |
|
824 |
void OPPROTO op_fabs_FT(void) |
825 |
{ |
826 |
FT0 = float32_abs(FT0); |
827 |
RETURN(); |
828 |
} |
829 |
|
830 |
void OPPROTO op_fabs_DT(void) |
831 |
{ |
832 |
DT0 = float64_abs(DT0); |
833 |
RETURN(); |
834 |
} |
835 |
|
836 |
void OPPROTO op_fcnvsd_FT_DT(void) |
837 |
{ |
838 |
DT0 = float32_to_float64(FT0, &env->fp_status); |
839 |
RETURN(); |
840 |
} |
841 |
|
842 |
void OPPROTO op_fcnvds_DT_FT(void) |
843 |
{ |
844 |
FT0 = float64_to_float32(DT0, &env->fp_status); |
845 |
RETURN(); |
846 |
} |
847 |
|
848 |
void OPPROTO op_fsqrt_FT(void) |
849 |
{ |
850 |
FT0 = float32_sqrt(FT0, &env->fp_status); |
851 |
RETURN(); |
852 |
} |
853 |
|
854 |
void OPPROTO op_fsqrt_DT(void) |
855 |
{ |
856 |
DT0 = float64_sqrt(DT0, &env->fp_status); |
857 |
RETURN(); |
858 |
} |
859 |
|
860 |
void OPPROTO op_fmov_T0_frN(void) |
861 |
{ |
862 |
*(uint32_t *)&env->fregs[PARAM1] = T0; |
863 |
RETURN(); |
864 |
} |
865 |
|
866 |
void OPPROTO op_dec1_rN(void) |
867 |
{ |
868 |
env->gregs[PARAM1] -= 1;
|
869 |
RETURN(); |
870 |
} |
871 |
|
872 |
void OPPROTO op_dec2_rN(void) |
873 |
{ |
874 |
env->gregs[PARAM1] -= 2;
|
875 |
RETURN(); |
876 |
} |
877 |
|
878 |
void OPPROTO op_dec4_rN(void) |
879 |
{ |
880 |
env->gregs[PARAM1] -= 4;
|
881 |
RETURN(); |
882 |
} |
883 |
|
884 |
void OPPROTO op_dec8_rN(void) |
885 |
{ |
886 |
env->gregs[PARAM1] -= 8;
|
887 |
RETURN(); |
888 |
} |
889 |
|
890 |
void OPPROTO op_inc1_rN(void) |
891 |
{ |
892 |
env->gregs[PARAM1] += 1;
|
893 |
RETURN(); |
894 |
} |
895 |
|
896 |
void OPPROTO op_inc2_rN(void) |
897 |
{ |
898 |
env->gregs[PARAM1] += 2;
|
899 |
RETURN(); |
900 |
} |
901 |
|
902 |
void OPPROTO op_inc4_rN(void) |
903 |
{ |
904 |
env->gregs[PARAM1] += 4;
|
905 |
RETURN(); |
906 |
} |
907 |
|
908 |
void OPPROTO op_inc8_rN(void) |
909 |
{ |
910 |
env->gregs[PARAM1] += 8;
|
911 |
RETURN(); |
912 |
} |
913 |
|
914 |
void OPPROTO op_add_T0_rN(void) |
915 |
{ |
916 |
env->gregs[PARAM1] += T0; |
917 |
RETURN(); |
918 |
} |
919 |
|
920 |
void OPPROTO op_sub_T0_rN(void) |
921 |
{ |
922 |
env->gregs[PARAM1] -= T0; |
923 |
RETURN(); |
924 |
} |
925 |
|
926 |
void OPPROTO op_and_T0_rN(void) |
927 |
{ |
928 |
env->gregs[PARAM1] &= T0; |
929 |
RETURN(); |
930 |
} |
931 |
|
932 |
void OPPROTO op_or_T0_rN(void) |
933 |
{ |
934 |
env->gregs[PARAM1] |= T0; |
935 |
RETURN(); |
936 |
} |
937 |
|
938 |
void OPPROTO op_xor_T0_rN(void) |
939 |
{ |
940 |
env->gregs[PARAM1] ^= T0; |
941 |
RETURN(); |
942 |
} |
943 |
|
944 |
void OPPROTO op_add_rN_T0(void) |
945 |
{ |
946 |
T0 += env->gregs[PARAM1]; |
947 |
RETURN(); |
948 |
} |
949 |
|
950 |
void OPPROTO op_add_rN_T1(void) |
951 |
{ |
952 |
T1 += env->gregs[PARAM1]; |
953 |
RETURN(); |
954 |
} |
955 |
|
956 |
void OPPROTO op_add_imm_rN(void) |
957 |
{ |
958 |
env->gregs[PARAM2] += PARAM1; |
959 |
RETURN(); |
960 |
} |
961 |
|
962 |
void OPPROTO op_and_imm_rN(void) |
963 |
{ |
964 |
env->gregs[PARAM2] &= PARAM1; |
965 |
RETURN(); |
966 |
} |
967 |
|
968 |
void OPPROTO op_or_imm_rN(void) |
969 |
{ |
970 |
env->gregs[PARAM2] |= PARAM1; |
971 |
RETURN(); |
972 |
} |
973 |
|
974 |
void OPPROTO op_xor_imm_rN(void) |
975 |
{ |
976 |
env->gregs[PARAM2] ^= PARAM1; |
977 |
RETURN(); |
978 |
} |
979 |
|
980 |
void OPPROTO op_dt_rN(void) |
981 |
{ |
982 |
cond_t((--env->gregs[PARAM1]) == 0);
|
983 |
RETURN(); |
984 |
} |
985 |
|
986 |
void OPPROTO op_tst_imm_rN(void) |
987 |
{ |
988 |
cond_t((env->gregs[PARAM2] & PARAM1) == 0);
|
989 |
RETURN(); |
990 |
} |
991 |
|
992 |
void OPPROTO op_movl_T0_T1(void) |
993 |
{ |
994 |
T1 = T0; |
995 |
RETURN(); |
996 |
} |
997 |
|
998 |
void OPPROTO op_movl_fpul_FT0(void) |
999 |
{ |
1000 |
FT0 = *(float32 *)&env->fpul; |
1001 |
RETURN(); |
1002 |
} |
1003 |
|
1004 |
void OPPROTO op_movl_FT0_fpul(void) |
1005 |
{ |
1006 |
*(float32 *)&env->fpul = FT0; |
1007 |
RETURN(); |
1008 |
} |
1009 |
|
1010 |
void OPPROTO op_movl_imm_PC(void) |
1011 |
{ |
1012 |
env->pc = PARAM1; |
1013 |
RETURN(); |
1014 |
} |
1015 |
|
1016 |
void OPPROTO op_jT(void) |
1017 |
{ |
1018 |
if (env->sr & SR_T)
|
1019 |
GOTO_LABEL_PARAM(1);
|
1020 |
RETURN(); |
1021 |
} |
1022 |
|
1023 |
void OPPROTO op_jdelayed(void) |
1024 |
{ |
1025 |
if (env->flags & DELAY_SLOT_TRUE) {
|
1026 |
env->flags &= ~DELAY_SLOT_TRUE; |
1027 |
GOTO_LABEL_PARAM(1);
|
1028 |
} |
1029 |
RETURN(); |
1030 |
} |
1031 |
|
1032 |
void OPPROTO op_movl_delayed_pc_PC(void) |
1033 |
{ |
1034 |
env->pc = env->delayed_pc; |
1035 |
RETURN(); |
1036 |
} |
1037 |
|
1038 |
void OPPROTO op_addl_GBR_T0(void) |
1039 |
{ |
1040 |
T0 += env->gbr; |
1041 |
RETURN(); |
1042 |
} |
1043 |
|
1044 |
void OPPROTO op_and_imm_T0(void) |
1045 |
{ |
1046 |
T0 &= PARAM1; |
1047 |
RETURN(); |
1048 |
} |
1049 |
|
1050 |
void OPPROTO op_or_imm_T0(void) |
1051 |
{ |
1052 |
T0 |= PARAM1; |
1053 |
RETURN(); |
1054 |
} |
1055 |
|
1056 |
void OPPROTO op_xor_imm_T0(void) |
1057 |
{ |
1058 |
T0 ^= PARAM1; |
1059 |
RETURN(); |
1060 |
} |
1061 |
|
1062 |
void OPPROTO op_tst_imm_T0(void) |
1063 |
{ |
1064 |
cond_t((T0 & PARAM1) == 0);
|
1065 |
RETURN(); |
1066 |
} |
1067 |
|
1068 |
void OPPROTO op_raise_illegal_instruction(void) |
1069 |
{ |
1070 |
env->exception_index = 0x180;
|
1071 |
do_raise_exception(); |
1072 |
RETURN(); |
1073 |
} |
1074 |
|
1075 |
void OPPROTO op_raise_slot_illegal_instruction(void) |
1076 |
{ |
1077 |
env->exception_index = 0x1a0;
|
1078 |
do_raise_exception(); |
1079 |
RETURN(); |
1080 |
} |
1081 |
|
1082 |
void OPPROTO op_debug(void) |
1083 |
{ |
1084 |
env->exception_index = EXCP_DEBUG; |
1085 |
cpu_loop_exit(); |
1086 |
} |
1087 |
|
1088 |
/* Load and store */
|
1089 |
#define MEMSUFFIX _raw
|
1090 |
#include "op_mem.c" |
1091 |
#undef MEMSUFFIX
|
1092 |
#if !defined(CONFIG_USER_ONLY)
|
1093 |
#define MEMSUFFIX _user
|
1094 |
#include "op_mem.c" |
1095 |
#undef MEMSUFFIX
|
1096 |
|
1097 |
#define MEMSUFFIX _kernel
|
1098 |
#include "op_mem.c" |
1099 |
#undef MEMSUFFIX
|
1100 |
#endif
|