Revision 6fa4cea9

b/cpu-defs.h
108 108 
    target_phys_addr_t addend;
109 109 
} CPUTLBEntry;
110 110 

  		





  
  111
  
    
/* Alpha has 4 different running levels */


  		





  
  112
  
    
#if defined(TARGET_ALPHA)


  		





  
  113
  
    
#define NB_MMU_MODES 4


  		





  
  114
  
    
#elif defined(TARGET_PPC64H) /* PowerPC 64 with hypervisor mode support */


  		





  
  115
  
    
#define NB_MMU_MODES 3


  		





  
  116
  
    
#else


  		





  
  117
  
    
#define NB_MMU_MODES 2


  		





  
  118
  
    
#endif


  		





  
  119
  
    

  		





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#define CPU_COMMON                                                      \


  		





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    struct TranslationBlock *current_tb; /* currently executing TB  */  \


  		





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    /* soft mmu support */                                              \


  		





  ......




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    target_ulong mem_write_vaddr; /* target virtual addr at which the   \


  		





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                                     memory was written */              \


  		





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    /* 0 = kernel, 1 = user */                                          \


  		





  122
  
  
    
    CPUTLBEntry tlb_table[2][CPU_TLB_SIZE];                             \


  		





  
  131
  
    
    CPUTLBEntry tlb_table[NB_MMU_MODES][CPU_TLB_SIZE];                  \


  		





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    struct TranslationBlock *tb_jmp_cache[TB_JMP_CACHE_SIZE];           \


  		





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                                                                        \


  		





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    /* from this point: preserved by CPU reset */                       \


  		












  

    
      b/exec.c
    
  






  1300
  1300
  
    
        env->tlb_table[1][i].addr_read = -1;


  		





  1301
  1301
  
    
        env->tlb_table[1][i].addr_write = -1;


  		





  1302
  1302
  
    
        env->tlb_table[1][i].addr_code = -1;


  		





  
  1303
  
    
#if (NB_MMU_MODES >= 3)


  		





  
  1304
  
    
        env->tlb_table[2][i].addr_read = -1;


  		





  
  1305
  
    
        env->tlb_table[2][i].addr_write = -1;


  		





  
  1306
  
    
        env->tlb_table[2][i].addr_code = -1;


  		





  
  1307
  
    
#if (NB_MMU_MODES == 4)


  		





  
  1308
  
    
        env->tlb_table[3][i].addr_read = -1;


  		





  
  1309
  
    
        env->tlb_table[3][i].addr_write = -1;


  		





  
  1310
  
    
        env->tlb_table[3][i].addr_code = -1;


  		





  
  1311
  
    
#endif


  		





  
  1312
  
    
#endif


  		





  1303
  1313
  
    
    }


  		





  1304
  1314
  
    

  		





  1305
  1315
  
    
    memset (env->tb_jmp_cache, 0, TB_JMP_CACHE_SIZE * sizeof (void *));


  		





  ......




  1345
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    i = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);


  		





  1346
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    tlb_flush_entry(&env->tlb_table[0][i], addr);


  		





  1347
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    tlb_flush_entry(&env->tlb_table[1][i], addr);


  		





  
  1358
  
    
#if (NB_MMU_MODES >= 3)


  		





  
  1359
  
    
    tlb_flush_entry(&env->tlb_table[2][i], addr);


  		





  
  1360
  
    
#if (NB_MMU_MODES == 4)


  		





  
  1361
  
    
    tlb_flush_entry(&env->tlb_table[3][i], addr);


  		





  
  1362
  
    
#endif


  		





  
  1363
  
    
#endif


  		





  1348
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  1349
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    /* Discard jump cache entries for any tb which might potentially


  		





  1350
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       overlap the flushed page.  */


  		





  ......




  1434
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            tlb_reset_dirty_range(&env->tlb_table[0][i], start1, length);


  		





  1435
  1451
  
    
        for(i = 0; i < CPU_TLB_SIZE; i++)


  		





  1436
  1452
  
    
            tlb_reset_dirty_range(&env->tlb_table[1][i], start1, length);


  		





  
  1453
  
    
#if (NB_MMU_MODES >= 3)


  		





  
  1454
  
    
        for(i = 0; i < CPU_TLB_SIZE; i++)


  		





  
  1455
  
    
            tlb_reset_dirty_range(&env->tlb_table[2][i], start1, length);


  		





  
  1456
  
    
#if (NB_MMU_MODES == 4)


  		





  
  1457
  
    
        for(i = 0; i < CPU_TLB_SIZE; i++)


  		





  
  1458
  
    
            tlb_reset_dirty_range(&env->tlb_table[3][i], start1, length);


  		





  
  1459
  
    
#endif


  		





  
  1460
  
    
#endif


  		





  1437
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    }


  		





  1438
  1462
  
    

  		





  1439
  1463
  
    
#if !defined(CONFIG_SOFTMMU)


  		





  ......




  1486
  1510
  
    
        tlb_update_dirty(&env->tlb_table[0][i]);


  		





  1487
  1511
  
    
    for(i = 0; i < CPU_TLB_SIZE; i++)


  		





  1488
  1512
  
    
        tlb_update_dirty(&env->tlb_table[1][i]);


  		





  
  1513
  
    
#if (NB_MMU_MODES >= 3)


  		





  
  1514
  
    
    for(i = 0; i < CPU_TLB_SIZE; i++)


  		





  
  1515
  
    
        tlb_update_dirty(&env->tlb_table[2][i]);


  		





  
  1516
  
    
#if (NB_MMU_MODES == 4)


  		





  
  1517
  
    
    for(i = 0; i < CPU_TLB_SIZE; i++)


  		





  
  1518
  
    
        tlb_update_dirty(&env->tlb_table[3][i]);


  		





  
  1519
  
    
#endif


  		





  
  1520
  
    
#endif


  		





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}


  		





  1490
  1522
  
    

  		





  1491
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static inline void tlb_set_dirty1(CPUTLBEntry *tlb_entry, 


  		





  ......




  1511
  1543
  
    
    i = (vaddr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);


  		





  1512
  1544
  
    
    tlb_set_dirty1(&env->tlb_table[0][i], addr);


  		





  1513
  1545
  
    
    tlb_set_dirty1(&env->tlb_table[1][i], addr);


  		





  
  1546
  
    
#if (NB_MMU_MODES >= 3)


  		





  
  1547
  
    
    tlb_set_dirty1(&env->tlb_table[2][i], addr);


  		





  
  1548
  
    
#if (NB_MMU_MODES == 4)


  		





  
  1549
  
    
    tlb_set_dirty1(&env->tlb_table[3][i], addr);


  		





  
  1550
  
    
#endif


  		





  
  1551
  
    
#endif


  		





  1514
  1552
  
    
}


  		





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  1516
  1554
  
    
/* add a new TLB entry. At most one entry for a given virtual address


  		












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