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1 | 3475187d | bellard | /*
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2 | c7ba218d | blueswir1 | * QEMU Sun4u/Sun4v System Emulator
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3 | 5fafdf24 | ths | *
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4 | 3475187d | bellard | * Copyright (c) 2005 Fabrice Bellard
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5 | 5fafdf24 | ths | *
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6 | 3475187d | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | 3475187d | bellard | * of this software and associated documentation files (the "Software"), to deal
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8 | 3475187d | bellard | * in the Software without restriction, including without limitation the rights
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9 | 3475187d | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | 3475187d | bellard | * copies of the Software, and to permit persons to whom the Software is
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11 | 3475187d | bellard | * furnished to do so, subject to the following conditions:
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12 | 3475187d | bellard | *
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13 | 3475187d | bellard | * The above copyright notice and this permission notice shall be included in
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14 | 3475187d | bellard | * all copies or substantial portions of the Software.
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15 | 3475187d | bellard | *
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16 | 3475187d | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | 3475187d | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | 3475187d | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | 3475187d | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | 3475187d | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | 3475187d | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | 3475187d | bellard | * THE SOFTWARE.
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23 | 3475187d | bellard | */
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24 | 87ecb68b | pbrook | #include "hw.h" |
25 | 87ecb68b | pbrook | #include "pci.h" |
26 | 87ecb68b | pbrook | #include "pc.h" |
27 | 87ecb68b | pbrook | #include "nvram.h" |
28 | 87ecb68b | pbrook | #include "fdc.h" |
29 | 87ecb68b | pbrook | #include "net.h" |
30 | 87ecb68b | pbrook | #include "qemu-timer.h" |
31 | 87ecb68b | pbrook | #include "sysemu.h" |
32 | 87ecb68b | pbrook | #include "boards.h" |
33 | d2c63fc1 | blueswir1 | #include "firmware_abi.h" |
34 | 3cce6243 | blueswir1 | #include "fw_cfg.h" |
35 | 3475187d | bellard | |
36 | 9d926598 | blueswir1 | //#define DEBUG_IRQ
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37 | 9d926598 | blueswir1 | |
38 | 9d926598 | blueswir1 | #ifdef DEBUG_IRQ
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39 | 9d926598 | blueswir1 | #define DPRINTF(fmt, args...) \
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40 | 9d926598 | blueswir1 | do { printf("CPUIRQ: " fmt , ##args); } while (0) |
41 | 9d926598 | blueswir1 | #else
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42 | 9d926598 | blueswir1 | #define DPRINTF(fmt, args...)
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43 | 9d926598 | blueswir1 | #endif
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44 | 9d926598 | blueswir1 | |
45 | 83469015 | bellard | #define KERNEL_LOAD_ADDR 0x00404000 |
46 | 83469015 | bellard | #define CMDLINE_ADDR 0x003ff000 |
47 | 83469015 | bellard | #define INITRD_LOAD_ADDR 0x00300000 |
48 | ac2e9d66 | blueswir1 | #define PROM_SIZE_MAX (4 * 1024 * 1024) |
49 | f930d07e | blueswir1 | #define PROM_VADDR 0x000ffd00000ULL |
50 | 83469015 | bellard | #define APB_SPECIAL_BASE 0x1fe00000000ULL |
51 | f930d07e | blueswir1 | #define APB_MEM_BASE 0x1ff00000000ULL |
52 | f930d07e | blueswir1 | #define VGA_BASE (APB_MEM_BASE + 0x400000ULL) |
53 | f930d07e | blueswir1 | #define PROM_FILENAME "openbios-sparc64" |
54 | 83469015 | bellard | #define NVRAM_SIZE 0x2000 |
55 | e4bcb14c | ths | #define MAX_IDE_BUS 2 |
56 | 3cce6243 | blueswir1 | #define BIOS_CFG_IOPORT 0x510 |
57 | 3475187d | bellard | |
58 | 9d926598 | blueswir1 | #define MAX_PILS 16 |
59 | 9d926598 | blueswir1 | |
60 | 8fa211e8 | blueswir1 | #define TICK_INT_DIS 0x8000000000000000ULL |
61 | 8fa211e8 | blueswir1 | #define TICK_MAX 0x7fffffffffffffffULL |
62 | 8fa211e8 | blueswir1 | |
63 | c7ba218d | blueswir1 | struct hwdef {
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64 | c7ba218d | blueswir1 | const char * const default_cpu_model; |
65 | 905fdcb5 | blueswir1 | uint16_t machine_id; |
66 | e87231d4 | blueswir1 | uint64_t prom_addr; |
67 | e87231d4 | blueswir1 | uint64_t console_serial_base; |
68 | c7ba218d | blueswir1 | }; |
69 | c7ba218d | blueswir1 | |
70 | 3475187d | bellard | int DMA_get_channel_mode (int nchan) |
71 | 3475187d | bellard | { |
72 | 3475187d | bellard | return 0; |
73 | 3475187d | bellard | } |
74 | 3475187d | bellard | int DMA_read_memory (int nchan, void *buf, int pos, int size) |
75 | 3475187d | bellard | { |
76 | 3475187d | bellard | return 0; |
77 | 3475187d | bellard | } |
78 | 3475187d | bellard | int DMA_write_memory (int nchan, void *buf, int pos, int size) |
79 | 3475187d | bellard | { |
80 | 3475187d | bellard | return 0; |
81 | 3475187d | bellard | } |
82 | 3475187d | bellard | void DMA_hold_DREQ (int nchan) {} |
83 | 3475187d | bellard | void DMA_release_DREQ (int nchan) {} |
84 | 3475187d | bellard | void DMA_schedule(int nchan) {} |
85 | 3475187d | bellard | void DMA_init (int high_page_enable) {} |
86 | 3475187d | bellard | void DMA_register_channel (int nchan, |
87 | 3475187d | bellard | DMA_transfer_handler transfer_handler, |
88 | 3475187d | bellard | void *opaque)
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89 | 3475187d | bellard | { |
90 | 3475187d | bellard | } |
91 | 3475187d | bellard | |
92 | 81864572 | blueswir1 | static int nvram_boot_set(void *opaque, const char *boot_device) |
93 | 81864572 | blueswir1 | { |
94 | 81864572 | blueswir1 | unsigned int i; |
95 | 81864572 | blueswir1 | uint8_t image[sizeof(ohwcfg_v3_t)];
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96 | 81864572 | blueswir1 | ohwcfg_v3_t *header = (ohwcfg_v3_t *)ℑ |
97 | 81864572 | blueswir1 | m48t59_t *nvram = (m48t59_t *)opaque; |
98 | 81864572 | blueswir1 | |
99 | 81864572 | blueswir1 | for (i = 0; i < sizeof(image); i++) |
100 | 81864572 | blueswir1 | image[i] = m48t59_read(nvram, i) & 0xff;
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101 | 81864572 | blueswir1 | |
102 | 363a37d5 | blueswir1 | pstrcpy((char *)header->boot_devices, sizeof(header->boot_devices), |
103 | 363a37d5 | blueswir1 | boot_device); |
104 | 81864572 | blueswir1 | header->nboot_devices = strlen(boot_device) & 0xff;
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105 | 81864572 | blueswir1 | header->crc = cpu_to_be16(OHW_compute_crc(header, 0x00, 0xF8)); |
106 | 81864572 | blueswir1 | |
107 | 81864572 | blueswir1 | for (i = 0; i < sizeof(image); i++) |
108 | 81864572 | blueswir1 | m48t59_write(nvram, i, image[i]); |
109 | 81864572 | blueswir1 | |
110 | 81864572 | blueswir1 | return 0; |
111 | 81864572 | blueswir1 | } |
112 | 81864572 | blueswir1 | |
113 | d2c63fc1 | blueswir1 | static int sun4u_NVRAM_set_params (m48t59_t *nvram, uint16_t NVRAM_size, |
114 | e7fb1406 | blueswir1 | const char *arch, |
115 | 77f193da | blueswir1 | ram_addr_t RAM_size, |
116 | 77f193da | blueswir1 | const char *boot_devices, |
117 | d2c63fc1 | blueswir1 | uint32_t kernel_image, uint32_t kernel_size, |
118 | d2c63fc1 | blueswir1 | const char *cmdline, |
119 | d2c63fc1 | blueswir1 | uint32_t initrd_image, uint32_t initrd_size, |
120 | d2c63fc1 | blueswir1 | uint32_t NVRAM_image, |
121 | 0d31cb99 | blueswir1 | int width, int height, int depth, |
122 | 0d31cb99 | blueswir1 | const uint8_t *macaddr)
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123 | 83469015 | bellard | { |
124 | 66508601 | blueswir1 | unsigned int i; |
125 | 66508601 | blueswir1 | uint32_t start, end; |
126 | d2c63fc1 | blueswir1 | uint8_t image[0x1ff0];
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127 | d2c63fc1 | blueswir1 | ohwcfg_v3_t *header = (ohwcfg_v3_t *)ℑ |
128 | d2c63fc1 | blueswir1 | struct sparc_arch_cfg *sparc_header;
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129 | d2c63fc1 | blueswir1 | struct OpenBIOS_nvpart_v1 *part_header;
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130 | d2c63fc1 | blueswir1 | |
131 | d2c63fc1 | blueswir1 | memset(image, '\0', sizeof(image)); |
132 | d2c63fc1 | blueswir1 | |
133 | d2c63fc1 | blueswir1 | // Try to match PPC NVRAM
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134 | 363a37d5 | blueswir1 | pstrcpy((char *)header->struct_ident, sizeof(header->struct_ident), |
135 | 363a37d5 | blueswir1 | "QEMU_BIOS");
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136 | d2c63fc1 | blueswir1 | header->struct_version = cpu_to_be32(3); /* structure v3 */ |
137 | d2c63fc1 | blueswir1 | |
138 | d2c63fc1 | blueswir1 | header->nvram_size = cpu_to_be16(NVRAM_size); |
139 | d2c63fc1 | blueswir1 | header->nvram_arch_ptr = cpu_to_be16(sizeof(ohwcfg_v3_t));
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140 | d2c63fc1 | blueswir1 | header->nvram_arch_size = cpu_to_be16(sizeof(struct sparc_arch_cfg)); |
141 | 363a37d5 | blueswir1 | pstrcpy((char *)header->arch, sizeof(header->arch), arch); |
142 | d2c63fc1 | blueswir1 | header->nb_cpus = smp_cpus & 0xff;
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143 | d2c63fc1 | blueswir1 | header->RAM0_base = 0;
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144 | d2c63fc1 | blueswir1 | header->RAM0_size = cpu_to_be64((uint64_t)RAM_size); |
145 | 363a37d5 | blueswir1 | pstrcpy((char *)header->boot_devices, sizeof(header->boot_devices), |
146 | 363a37d5 | blueswir1 | boot_devices); |
147 | d2c63fc1 | blueswir1 | header->nboot_devices = strlen(boot_devices) & 0xff;
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148 | d2c63fc1 | blueswir1 | header->kernel_image = cpu_to_be64((uint64_t)kernel_image); |
149 | d2c63fc1 | blueswir1 | header->kernel_size = cpu_to_be64((uint64_t)kernel_size); |
150 | 3475187d | bellard | if (cmdline) {
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151 | 293f78bc | blueswir1 | pstrcpy_targphys(CMDLINE_ADDR, TARGET_PAGE_SIZE, cmdline); |
152 | d2c63fc1 | blueswir1 | header->cmdline = cpu_to_be64((uint64_t)CMDLINE_ADDR); |
153 | d2c63fc1 | blueswir1 | header->cmdline_size = cpu_to_be64((uint64_t)strlen(cmdline)); |
154 | 3475187d | bellard | } |
155 | d2c63fc1 | blueswir1 | header->initrd_image = cpu_to_be64((uint64_t)initrd_image); |
156 | d2c63fc1 | blueswir1 | header->initrd_size = cpu_to_be64((uint64_t)initrd_size); |
157 | d2c63fc1 | blueswir1 | header->NVRAM_image = cpu_to_be64((uint64_t)NVRAM_image); |
158 | d2c63fc1 | blueswir1 | |
159 | d2c63fc1 | blueswir1 | header->width = cpu_to_be16(width); |
160 | d2c63fc1 | blueswir1 | header->height = cpu_to_be16(height); |
161 | d2c63fc1 | blueswir1 | header->depth = cpu_to_be16(depth); |
162 | d2c63fc1 | blueswir1 | if (nographic)
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163 | d2c63fc1 | blueswir1 | header->graphic_flags = cpu_to_be16(OHW_GF_NOGRAPHICS); |
164 | 83469015 | bellard | |
165 | d2c63fc1 | blueswir1 | header->crc = cpu_to_be16(OHW_compute_crc(header, 0x00, 0xF8)); |
166 | d2c63fc1 | blueswir1 | |
167 | d2c63fc1 | blueswir1 | // Architecture specific header
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168 | d2c63fc1 | blueswir1 | start = sizeof(ohwcfg_v3_t);
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169 | d2c63fc1 | blueswir1 | sparc_header = (struct sparc_arch_cfg *)&image[start];
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170 | d2c63fc1 | blueswir1 | sparc_header->valid = 0;
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171 | d2c63fc1 | blueswir1 | start += sizeof(struct sparc_arch_cfg); |
172 | 83469015 | bellard | |
173 | 66508601 | blueswir1 | // OpenBIOS nvram variables
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174 | 66508601 | blueswir1 | // Variable partition
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175 | d2c63fc1 | blueswir1 | part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
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176 | d2c63fc1 | blueswir1 | part_header->signature = OPENBIOS_PART_SYSTEM; |
177 | 363a37d5 | blueswir1 | pstrcpy(part_header->name, sizeof(part_header->name), "system"); |
178 | 66508601 | blueswir1 | |
179 | d2c63fc1 | blueswir1 | end = start + sizeof(struct OpenBIOS_nvpart_v1); |
180 | 66508601 | blueswir1 | for (i = 0; i < nb_prom_envs; i++) |
181 | d2c63fc1 | blueswir1 | end = OpenBIOS_set_var(image, end, prom_envs[i]); |
182 | d2c63fc1 | blueswir1 | |
183 | d2c63fc1 | blueswir1 | // End marker
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184 | d2c63fc1 | blueswir1 | image[end++] = '\0';
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185 | 66508601 | blueswir1 | |
186 | 66508601 | blueswir1 | end = start + ((end - start + 15) & ~15); |
187 | d2c63fc1 | blueswir1 | OpenBIOS_finish_partition(part_header, end - start); |
188 | 66508601 | blueswir1 | |
189 | 66508601 | blueswir1 | // free partition
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190 | 66508601 | blueswir1 | start = end; |
191 | d2c63fc1 | blueswir1 | part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
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192 | d2c63fc1 | blueswir1 | part_header->signature = OPENBIOS_PART_FREE; |
193 | 363a37d5 | blueswir1 | pstrcpy(part_header->name, sizeof(part_header->name), "free"); |
194 | 66508601 | blueswir1 | |
195 | 66508601 | blueswir1 | end = 0x1fd0;
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196 | d2c63fc1 | blueswir1 | OpenBIOS_finish_partition(part_header, end - start); |
197 | d2c63fc1 | blueswir1 | |
198 | 0d31cb99 | blueswir1 | Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, 0x80); |
199 | 0d31cb99 | blueswir1 | |
200 | d2c63fc1 | blueswir1 | for (i = 0; i < sizeof(image); i++) |
201 | d2c63fc1 | blueswir1 | m48t59_write(nvram, i, image[i]); |
202 | 66508601 | blueswir1 | |
203 | 81864572 | blueswir1 | qemu_register_boot_set(nvram_boot_set, nvram); |
204 | 81864572 | blueswir1 | |
205 | 83469015 | bellard | return 0; |
206 | 3475187d | bellard | } |
207 | 3475187d | bellard | |
208 | 22548760 | blueswir1 | void pic_info(void) |
209 | 3475187d | bellard | { |
210 | 3475187d | bellard | } |
211 | 3475187d | bellard | |
212 | 22548760 | blueswir1 | void irq_info(void) |
213 | 3475187d | bellard | { |
214 | 3475187d | bellard | } |
215 | 3475187d | bellard | |
216 | 9d926598 | blueswir1 | void cpu_check_irqs(CPUState *env)
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217 | 9d926598 | blueswir1 | { |
218 | 9d926598 | blueswir1 | uint32_t pil = env->pil_in | (env->softint & ~SOFTINT_TIMER) | |
219 | 9d926598 | blueswir1 | ((env->softint & SOFTINT_TIMER) << 14);
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220 | 9d926598 | blueswir1 | |
221 | 9d926598 | blueswir1 | if (pil && (env->interrupt_index == 0 || |
222 | 9d926598 | blueswir1 | (env->interrupt_index & ~15) == TT_EXTINT)) {
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223 | 9d926598 | blueswir1 | unsigned int i; |
224 | 9d926598 | blueswir1 | |
225 | 9d926598 | blueswir1 | for (i = 15; i > 0; i--) { |
226 | 9d926598 | blueswir1 | if (pil & (1 << i)) { |
227 | 9d926598 | blueswir1 | int old_interrupt = env->interrupt_index;
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228 | 9d926598 | blueswir1 | |
229 | 9d926598 | blueswir1 | env->interrupt_index = TT_EXTINT | i; |
230 | 9d926598 | blueswir1 | if (old_interrupt != env->interrupt_index) {
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231 | 9d926598 | blueswir1 | DPRINTF("Set CPU IRQ %d\n", i);
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232 | 9d926598 | blueswir1 | cpu_interrupt(env, CPU_INTERRUPT_HARD); |
233 | 9d926598 | blueswir1 | } |
234 | 9d926598 | blueswir1 | break;
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235 | 9d926598 | blueswir1 | } |
236 | 9d926598 | blueswir1 | } |
237 | 9d926598 | blueswir1 | } else if (!pil && (env->interrupt_index & ~15) == TT_EXTINT) { |
238 | 9d926598 | blueswir1 | DPRINTF("Reset CPU IRQ %d\n", env->interrupt_index & 15); |
239 | 9d926598 | blueswir1 | env->interrupt_index = 0;
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240 | 9d926598 | blueswir1 | cpu_reset_interrupt(env, CPU_INTERRUPT_HARD); |
241 | 9d926598 | blueswir1 | } |
242 | 9d926598 | blueswir1 | } |
243 | 9d926598 | blueswir1 | |
244 | 9d926598 | blueswir1 | static void cpu_set_irq(void *opaque, int irq, int level) |
245 | 9d926598 | blueswir1 | { |
246 | 9d926598 | blueswir1 | CPUState *env = opaque; |
247 | 9d926598 | blueswir1 | |
248 | 9d926598 | blueswir1 | if (level) {
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249 | 9d926598 | blueswir1 | DPRINTF("Raise CPU IRQ %d\n", irq);
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250 | 9d926598 | blueswir1 | env->halted = 0;
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251 | 9d926598 | blueswir1 | env->pil_in |= 1 << irq;
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252 | 9d926598 | blueswir1 | cpu_check_irqs(env); |
253 | 9d926598 | blueswir1 | } else {
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254 | 9d926598 | blueswir1 | DPRINTF("Lower CPU IRQ %d\n", irq);
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255 | 9d926598 | blueswir1 | env->pil_in &= ~(1 << irq);
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256 | 9d926598 | blueswir1 | cpu_check_irqs(env); |
257 | 9d926598 | blueswir1 | } |
258 | 9d926598 | blueswir1 | } |
259 | 9d926598 | blueswir1 | |
260 | 83469015 | bellard | void qemu_system_powerdown(void) |
261 | 3475187d | bellard | { |
262 | 3475187d | bellard | } |
263 | 3475187d | bellard | |
264 | e87231d4 | blueswir1 | typedef struct ResetData { |
265 | e87231d4 | blueswir1 | CPUState *env; |
266 | e87231d4 | blueswir1 | uint64_t reset_addr; |
267 | e87231d4 | blueswir1 | } ResetData; |
268 | e87231d4 | blueswir1 | |
269 | c68ea704 | bellard | static void main_cpu_reset(void *opaque) |
270 | c68ea704 | bellard | { |
271 | e87231d4 | blueswir1 | ResetData *s = (ResetData *)opaque; |
272 | e87231d4 | blueswir1 | CPUState *env = s->env; |
273 | 20c9f095 | blueswir1 | |
274 | c68ea704 | bellard | cpu_reset(env); |
275 | 8fa211e8 | blueswir1 | env->tick_cmpr = TICK_INT_DIS | 0;
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276 | 8fa211e8 | blueswir1 | ptimer_set_limit(env->tick, TICK_MAX, 1);
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277 | 20c9f095 | blueswir1 | ptimer_run(env->tick, 0);
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278 | 8fa211e8 | blueswir1 | env->stick_cmpr = TICK_INT_DIS | 0;
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279 | 8fa211e8 | blueswir1 | ptimer_set_limit(env->stick, TICK_MAX, 1);
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280 | 20c9f095 | blueswir1 | ptimer_run(env->stick, 0);
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281 | 8fa211e8 | blueswir1 | env->hstick_cmpr = TICK_INT_DIS | 0;
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282 | 8fa211e8 | blueswir1 | ptimer_set_limit(env->hstick, TICK_MAX, 1);
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283 | 20c9f095 | blueswir1 | ptimer_run(env->hstick, 0);
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284 | e87231d4 | blueswir1 | env->gregs[1] = 0; // Memory start |
285 | e87231d4 | blueswir1 | env->gregs[2] = ram_size; // Memory size |
286 | e87231d4 | blueswir1 | env->gregs[3] = 0; // Machine description XXX |
287 | e87231d4 | blueswir1 | env->pc = s->reset_addr; |
288 | e87231d4 | blueswir1 | env->npc = env->pc + 4;
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289 | 20c9f095 | blueswir1 | } |
290 | 20c9f095 | blueswir1 | |
291 | 22548760 | blueswir1 | static void tick_irq(void *opaque) |
292 | 20c9f095 | blueswir1 | { |
293 | 20c9f095 | blueswir1 | CPUState *env = opaque; |
294 | 20c9f095 | blueswir1 | |
295 | 8fa211e8 | blueswir1 | if (!(env->tick_cmpr & TICK_INT_DIS)) {
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296 | 8fa211e8 | blueswir1 | env->softint |= SOFTINT_TIMER; |
297 | 8fa211e8 | blueswir1 | cpu_interrupt(env, CPU_INTERRUPT_TIMER); |
298 | 8fa211e8 | blueswir1 | } |
299 | 20c9f095 | blueswir1 | } |
300 | 20c9f095 | blueswir1 | |
301 | 22548760 | blueswir1 | static void stick_irq(void *opaque) |
302 | 20c9f095 | blueswir1 | { |
303 | 20c9f095 | blueswir1 | CPUState *env = opaque; |
304 | 20c9f095 | blueswir1 | |
305 | 8fa211e8 | blueswir1 | if (!(env->stick_cmpr & TICK_INT_DIS)) {
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306 | 8fa211e8 | blueswir1 | env->softint |= SOFTINT_STIMER; |
307 | 8fa211e8 | blueswir1 | cpu_interrupt(env, CPU_INTERRUPT_TIMER); |
308 | 8fa211e8 | blueswir1 | } |
309 | 20c9f095 | blueswir1 | } |
310 | 20c9f095 | blueswir1 | |
311 | 22548760 | blueswir1 | static void hstick_irq(void *opaque) |
312 | 20c9f095 | blueswir1 | { |
313 | 20c9f095 | blueswir1 | CPUState *env = opaque; |
314 | 20c9f095 | blueswir1 | |
315 | 8fa211e8 | blueswir1 | if (!(env->hstick_cmpr & TICK_INT_DIS)) {
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316 | 8fa211e8 | blueswir1 | cpu_interrupt(env, CPU_INTERRUPT_TIMER); |
317 | 8fa211e8 | blueswir1 | } |
318 | c68ea704 | bellard | } |
319 | c68ea704 | bellard | |
320 | f4b1a842 | blueswir1 | void cpu_tick_set_count(void *opaque, uint64_t count) |
321 | f4b1a842 | blueswir1 | { |
322 | f4b1a842 | blueswir1 | ptimer_set_count(opaque, -count); |
323 | f4b1a842 | blueswir1 | } |
324 | f4b1a842 | blueswir1 | |
325 | f4b1a842 | blueswir1 | uint64_t cpu_tick_get_count(void *opaque)
|
326 | f4b1a842 | blueswir1 | { |
327 | f4b1a842 | blueswir1 | return -ptimer_get_count(opaque);
|
328 | f4b1a842 | blueswir1 | } |
329 | f4b1a842 | blueswir1 | |
330 | f4b1a842 | blueswir1 | void cpu_tick_set_limit(void *opaque, uint64_t limit) |
331 | f4b1a842 | blueswir1 | { |
332 | f4b1a842 | blueswir1 | ptimer_set_limit(opaque, -limit, 0);
|
333 | f4b1a842 | blueswir1 | } |
334 | f4b1a842 | blueswir1 | |
335 | 83469015 | bellard | static const int ide_iobase[2] = { 0x1f0, 0x170 }; |
336 | 83469015 | bellard | static const int ide_iobase2[2] = { 0x3f6, 0x376 }; |
337 | 83469015 | bellard | static const int ide_irq[2] = { 14, 15 }; |
338 | 3475187d | bellard | |
339 | 83469015 | bellard | static const int serial_io[MAX_SERIAL_PORTS] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8 }; |
340 | 83469015 | bellard | static const int serial_irq[MAX_SERIAL_PORTS] = { 4, 3, 4, 3 }; |
341 | 83469015 | bellard | |
342 | 83469015 | bellard | static const int parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc }; |
343 | 83469015 | bellard | static const int parallel_irq[MAX_PARALLEL_PORTS] = { 7, 7, 7 }; |
344 | 83469015 | bellard | |
345 | 83469015 | bellard | static fdctrl_t *floppy_controller;
|
346 | 3475187d | bellard | |
347 | c7ba218d | blueswir1 | static void sun4uv_init(ram_addr_t RAM_size, int vga_ram_size, |
348 | c7ba218d | blueswir1 | const char *boot_devices, DisplayState *ds, |
349 | c7ba218d | blueswir1 | const char *kernel_filename, const char *kernel_cmdline, |
350 | c7ba218d | blueswir1 | const char *initrd_filename, const char *cpu_model, |
351 | c7ba218d | blueswir1 | const struct hwdef *hwdef) |
352 | 3475187d | bellard | { |
353 | c68ea704 | bellard | CPUState *env; |
354 | 3475187d | bellard | char buf[1024]; |
355 | 83469015 | bellard | m48t59_t *nvram; |
356 | 3475187d | bellard | int ret, linux_boot;
|
357 | 3475187d | bellard | unsigned int i; |
358 | 5c6602c5 | blueswir1 | ram_addr_t ram_offset, prom_offset, vga_ram_offset; |
359 | 5c6602c5 | blueswir1 | long initrd_size, kernel_size;
|
360 | 83469015 | bellard | PCIBus *pci_bus; |
361 | 20c9f095 | blueswir1 | QEMUBH *bh; |
362 | f19e918d | blueswir1 | qemu_irq *irq; |
363 | 22548760 | blueswir1 | int drive_index;
|
364 | e4bcb14c | ths | BlockDriverState *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; |
365 | e4bcb14c | ths | BlockDriverState *fd[MAX_FD]; |
366 | 3cce6243 | blueswir1 | void *fw_cfg;
|
367 | e87231d4 | blueswir1 | ResetData *reset_info; |
368 | 3475187d | bellard | |
369 | 3475187d | bellard | linux_boot = (kernel_filename != NULL);
|
370 | 3475187d | bellard | |
371 | 62724a37 | blueswir1 | /* init CPUs */
|
372 | c7ba218d | blueswir1 | if (!cpu_model)
|
373 | c7ba218d | blueswir1 | cpu_model = hwdef->default_cpu_model; |
374 | c7ba218d | blueswir1 | |
375 | aaed909a | bellard | env = cpu_init(cpu_model); |
376 | aaed909a | bellard | if (!env) {
|
377 | 62724a37 | blueswir1 | fprintf(stderr, "Unable to find Sparc CPU definition\n");
|
378 | 62724a37 | blueswir1 | exit(1);
|
379 | 62724a37 | blueswir1 | } |
380 | 20c9f095 | blueswir1 | bh = qemu_bh_new(tick_irq, env); |
381 | 20c9f095 | blueswir1 | env->tick = ptimer_init(bh); |
382 | 20c9f095 | blueswir1 | ptimer_set_period(env->tick, 1ULL);
|
383 | 20c9f095 | blueswir1 | |
384 | 20c9f095 | blueswir1 | bh = qemu_bh_new(stick_irq, env); |
385 | 20c9f095 | blueswir1 | env->stick = ptimer_init(bh); |
386 | 20c9f095 | blueswir1 | ptimer_set_period(env->stick, 1ULL);
|
387 | 20c9f095 | blueswir1 | |
388 | 20c9f095 | blueswir1 | bh = qemu_bh_new(hstick_irq, env); |
389 | 20c9f095 | blueswir1 | env->hstick = ptimer_init(bh); |
390 | 20c9f095 | blueswir1 | ptimer_set_period(env->hstick, 1ULL);
|
391 | e87231d4 | blueswir1 | |
392 | e87231d4 | blueswir1 | reset_info = qemu_mallocz(sizeof(ResetData));
|
393 | e87231d4 | blueswir1 | reset_info->env = env; |
394 | e87231d4 | blueswir1 | reset_info->reset_addr = hwdef->prom_addr + 0x40ULL;
|
395 | e87231d4 | blueswir1 | qemu_register_reset(main_cpu_reset, reset_info); |
396 | e87231d4 | blueswir1 | main_cpu_reset(reset_info); |
397 | e87231d4 | blueswir1 | // Override warm reset address with cold start address
|
398 | e87231d4 | blueswir1 | env->pc = hwdef->prom_addr + 0x20ULL;
|
399 | e87231d4 | blueswir1 | env->npc = env->pc + 4;
|
400 | c68ea704 | bellard | |
401 | 3475187d | bellard | /* allocate RAM */
|
402 | 5c6602c5 | blueswir1 | ram_offset = qemu_ram_alloc(RAM_size); |
403 | 5c6602c5 | blueswir1 | cpu_register_physical_memory(0, RAM_size, ram_offset);
|
404 | 3475187d | bellard | |
405 | 5c6602c5 | blueswir1 | prom_offset = qemu_ram_alloc(PROM_SIZE_MAX); |
406 | e87231d4 | blueswir1 | cpu_register_physical_memory(hwdef->prom_addr, |
407 | 77f193da | blueswir1 | (PROM_SIZE_MAX + TARGET_PAGE_SIZE) & |
408 | 77f193da | blueswir1 | TARGET_PAGE_MASK, |
409 | b3783731 | bellard | prom_offset | IO_MEM_ROM); |
410 | 3475187d | bellard | |
411 | 1192dad8 | j_mayer | if (bios_name == NULL) |
412 | 1192dad8 | j_mayer | bios_name = PROM_FILENAME; |
413 | 1192dad8 | j_mayer | snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name); |
414 | e87231d4 | blueswir1 | ret = load_elf(buf, hwdef->prom_addr - PROM_VADDR, NULL, NULL, NULL); |
415 | 3475187d | bellard | if (ret < 0) { |
416 | e87231d4 | blueswir1 | ret = load_image_targphys(buf, hwdef->prom_addr, |
417 | e87231d4 | blueswir1 | (PROM_SIZE_MAX + TARGET_PAGE_SIZE) & |
418 | e87231d4 | blueswir1 | TARGET_PAGE_MASK); |
419 | e87231d4 | blueswir1 | if (ret < 0) { |
420 | e87231d4 | blueswir1 | fprintf(stderr, "qemu: could not load prom '%s'\n",
|
421 | e87231d4 | blueswir1 | buf); |
422 | e87231d4 | blueswir1 | exit(1);
|
423 | e87231d4 | blueswir1 | } |
424 | 3475187d | bellard | } |
425 | 3475187d | bellard | |
426 | 3475187d | bellard | kernel_size = 0;
|
427 | 83469015 | bellard | initrd_size = 0;
|
428 | 3475187d | bellard | if (linux_boot) {
|
429 | b3783731 | bellard | /* XXX: put correct offset */
|
430 | 74287114 | ths | kernel_size = load_elf(kernel_filename, 0, NULL, NULL, NULL); |
431 | 3475187d | bellard | if (kernel_size < 0) |
432 | 293f78bc | blueswir1 | kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR, |
433 | 293f78bc | blueswir1 | ram_size - KERNEL_LOAD_ADDR); |
434 | f930d07e | blueswir1 | if (kernel_size < 0) |
435 | 293f78bc | blueswir1 | kernel_size = load_image_targphys(kernel_filename, |
436 | 293f78bc | blueswir1 | KERNEL_LOAD_ADDR, |
437 | 293f78bc | blueswir1 | ram_size - KERNEL_LOAD_ADDR); |
438 | 3475187d | bellard | if (kernel_size < 0) { |
439 | 5fafdf24 | ths | fprintf(stderr, "qemu: could not load kernel '%s'\n",
|
440 | 3475187d | bellard | kernel_filename); |
441 | f930d07e | blueswir1 | exit(1);
|
442 | 3475187d | bellard | } |
443 | 3475187d | bellard | |
444 | 3475187d | bellard | /* load initrd */
|
445 | 3475187d | bellard | if (initrd_filename) {
|
446 | 293f78bc | blueswir1 | initrd_size = load_image_targphys(initrd_filename, |
447 | 293f78bc | blueswir1 | INITRD_LOAD_ADDR, |
448 | 293f78bc | blueswir1 | ram_size - INITRD_LOAD_ADDR); |
449 | 3475187d | bellard | if (initrd_size < 0) { |
450 | 5fafdf24 | ths | fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
|
451 | 3475187d | bellard | initrd_filename); |
452 | 3475187d | bellard | exit(1);
|
453 | 3475187d | bellard | } |
454 | 3475187d | bellard | } |
455 | 3475187d | bellard | if (initrd_size > 0) { |
456 | f930d07e | blueswir1 | for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) { |
457 | 293f78bc | blueswir1 | if (ldl_phys(KERNEL_LOAD_ADDR + i) == 0x48647253) { // HdrS |
458 | 293f78bc | blueswir1 | stl_phys(KERNEL_LOAD_ADDR + i + 16, INITRD_LOAD_ADDR);
|
459 | 293f78bc | blueswir1 | stl_phys(KERNEL_LOAD_ADDR + i + 20, initrd_size);
|
460 | f930d07e | blueswir1 | break;
|
461 | f930d07e | blueswir1 | } |
462 | f930d07e | blueswir1 | } |
463 | 3475187d | bellard | } |
464 | 3475187d | bellard | } |
465 | 502a5395 | pbrook | pci_bus = pci_apb_init(APB_SPECIAL_BASE, APB_MEM_BASE, NULL);
|
466 | 83469015 | bellard | isa_mem_base = VGA_BASE; |
467 | 5c6602c5 | blueswir1 | vga_ram_offset = qemu_ram_alloc(vga_ram_size); |
468 | 5c6602c5 | blueswir1 | pci_cirrus_vga_init(pci_bus, ds, phys_ram_base + vga_ram_offset, |
469 | 5c6602c5 | blueswir1 | vga_ram_offset, vga_ram_size); |
470 | 83469015 | bellard | |
471 | e87231d4 | blueswir1 | i = 0;
|
472 | e87231d4 | blueswir1 | if (hwdef->console_serial_base) {
|
473 | e87231d4 | blueswir1 | serial_mm_init(hwdef->console_serial_base, 0, NULL, 115200, |
474 | e87231d4 | blueswir1 | serial_hds[i], 1);
|
475 | e87231d4 | blueswir1 | i++; |
476 | e87231d4 | blueswir1 | } |
477 | e87231d4 | blueswir1 | for(; i < MAX_SERIAL_PORTS; i++) {
|
478 | 83469015 | bellard | if (serial_hds[i]) {
|
479 | cbf5c748 | blueswir1 | serial_init(serial_io[i], NULL/*serial_irq[i]*/, 115200, |
480 | cbf5c748 | blueswir1 | serial_hds[i]); |
481 | 83469015 | bellard | } |
482 | 83469015 | bellard | } |
483 | 83469015 | bellard | |
484 | 83469015 | bellard | for(i = 0; i < MAX_PARALLEL_PORTS; i++) { |
485 | 83469015 | bellard | if (parallel_hds[i]) {
|
486 | 77f193da | blueswir1 | parallel_init(parallel_io[i], NULL/*parallel_irq[i]*/, |
487 | 77f193da | blueswir1 | parallel_hds[i]); |
488 | 83469015 | bellard | } |
489 | 83469015 | bellard | } |
490 | 83469015 | bellard | |
491 | 83469015 | bellard | for(i = 0; i < nb_nics; i++) { |
492 | a41b2ff2 | pbrook | if (!nd_table[i].model)
|
493 | a41b2ff2 | pbrook | nd_table[i].model = "ne2k_pci";
|
494 | f930d07e | blueswir1 | pci_nic_init(pci_bus, &nd_table[i], -1);
|
495 | 83469015 | bellard | } |
496 | 83469015 | bellard | |
497 | 9d926598 | blueswir1 | irq = qemu_allocate_irqs(cpu_set_irq, env, MAX_PILS); |
498 | e4bcb14c | ths | if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) {
|
499 | e4bcb14c | ths | fprintf(stderr, "qemu: too many IDE bus\n");
|
500 | e4bcb14c | ths | exit(1);
|
501 | e4bcb14c | ths | } |
502 | e4bcb14c | ths | for(i = 0; i < MAX_IDE_BUS * MAX_IDE_DEVS; i++) { |
503 | 22548760 | blueswir1 | drive_index = drive_get_index(IF_IDE, i / MAX_IDE_DEVS, |
504 | 22548760 | blueswir1 | i % MAX_IDE_DEVS); |
505 | 22548760 | blueswir1 | if (drive_index != -1) |
506 | 22548760 | blueswir1 | hd[i] = drives_table[drive_index].bdrv; |
507 | e4bcb14c | ths | else
|
508 | e4bcb14c | ths | hd[i] = NULL;
|
509 | e4bcb14c | ths | } |
510 | e4bcb14c | ths | |
511 | e4bcb14c | ths | // XXX pci_cmd646_ide_init(pci_bus, hd, 1);
|
512 | e4bcb14c | ths | pci_piix3_ide_init(pci_bus, hd, -1, irq);
|
513 | d537cf6c | pbrook | /* FIXME: wire up interrupts. */
|
514 | d537cf6c | pbrook | i8042_init(NULL/*1*/, NULL/*12*/, 0x60); |
515 | e4bcb14c | ths | for(i = 0; i < MAX_FD; i++) { |
516 | 22548760 | blueswir1 | drive_index = drive_get_index(IF_FLOPPY, 0, i);
|
517 | 22548760 | blueswir1 | if (drive_index != -1) |
518 | 22548760 | blueswir1 | fd[i] = drives_table[drive_index].bdrv; |
519 | e4bcb14c | ths | else
|
520 | e4bcb14c | ths | fd[i] = NULL;
|
521 | e4bcb14c | ths | } |
522 | e4bcb14c | ths | floppy_controller = fdctrl_init(NULL/*6*/, 2, 0, 0x3f0, fd); |
523 | d537cf6c | pbrook | nvram = m48t59_init(NULL/*8*/, 0, 0x0074, NVRAM_SIZE, 59); |
524 | 22548760 | blueswir1 | sun4u_NVRAM_set_params(nvram, NVRAM_SIZE, "Sun4u", RAM_size, boot_devices,
|
525 | 0d31cb99 | blueswir1 | KERNEL_LOAD_ADDR, kernel_size, |
526 | 0d31cb99 | blueswir1 | kernel_cmdline, |
527 | 0d31cb99 | blueswir1 | INITRD_LOAD_ADDR, initrd_size, |
528 | 0d31cb99 | blueswir1 | /* XXX: need an option to load a NVRAM image */
|
529 | 0d31cb99 | blueswir1 | 0,
|
530 | 0d31cb99 | blueswir1 | graphic_width, graphic_height, graphic_depth, |
531 | 0d31cb99 | blueswir1 | (uint8_t *)&nd_table[0].macaddr);
|
532 | 83469015 | bellard | |
533 | 3cce6243 | blueswir1 | fw_cfg = fw_cfg_init(BIOS_CFG_IOPORT, BIOS_CFG_IOPORT + 1, 0, 0); |
534 | 3cce6243 | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
|
535 | 905fdcb5 | blueswir1 | fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); |
536 | 905fdcb5 | blueswir1 | fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id); |
537 | 3475187d | bellard | } |
538 | 3475187d | bellard | |
539 | 905fdcb5 | blueswir1 | enum {
|
540 | 905fdcb5 | blueswir1 | sun4u_id = 0,
|
541 | 905fdcb5 | blueswir1 | sun4v_id = 64,
|
542 | e87231d4 | blueswir1 | niagara_id, |
543 | 905fdcb5 | blueswir1 | }; |
544 | 905fdcb5 | blueswir1 | |
545 | c7ba218d | blueswir1 | static const struct hwdef hwdefs[] = { |
546 | c7ba218d | blueswir1 | /* Sun4u generic PC-like machine */
|
547 | c7ba218d | blueswir1 | { |
548 | c7ba218d | blueswir1 | .default_cpu_model = "TI UltraSparc II",
|
549 | 905fdcb5 | blueswir1 | .machine_id = sun4u_id, |
550 | e87231d4 | blueswir1 | .prom_addr = 0x1fff0000000ULL,
|
551 | e87231d4 | blueswir1 | .console_serial_base = 0,
|
552 | c7ba218d | blueswir1 | }, |
553 | c7ba218d | blueswir1 | /* Sun4v generic PC-like machine */
|
554 | c7ba218d | blueswir1 | { |
555 | c7ba218d | blueswir1 | .default_cpu_model = "Sun UltraSparc T1",
|
556 | 905fdcb5 | blueswir1 | .machine_id = sun4v_id, |
557 | e87231d4 | blueswir1 | .prom_addr = 0x1fff0000000ULL,
|
558 | e87231d4 | blueswir1 | .console_serial_base = 0,
|
559 | e87231d4 | blueswir1 | }, |
560 | e87231d4 | blueswir1 | /* Sun4v generic Niagara machine */
|
561 | e87231d4 | blueswir1 | { |
562 | e87231d4 | blueswir1 | .default_cpu_model = "Sun UltraSparc T1",
|
563 | e87231d4 | blueswir1 | .machine_id = niagara_id, |
564 | e87231d4 | blueswir1 | .prom_addr = 0xfff0000000ULL,
|
565 | e87231d4 | blueswir1 | .console_serial_base = 0xfff0c2c000ULL,
|
566 | c7ba218d | blueswir1 | }, |
567 | c7ba218d | blueswir1 | }; |
568 | c7ba218d | blueswir1 | |
569 | c7ba218d | blueswir1 | /* Sun4u hardware initialisation */
|
570 | c7ba218d | blueswir1 | static void sun4u_init(ram_addr_t RAM_size, int vga_ram_size, |
571 | c7ba218d | blueswir1 | const char *boot_devices, DisplayState *ds, |
572 | c7ba218d | blueswir1 | const char *kernel_filename, const char *kernel_cmdline, |
573 | c7ba218d | blueswir1 | const char *initrd_filename, const char *cpu_model) |
574 | c7ba218d | blueswir1 | { |
575 | c7ba218d | blueswir1 | sun4uv_init(RAM_size, vga_ram_size, boot_devices, ds, kernel_filename, |
576 | c7ba218d | blueswir1 | kernel_cmdline, initrd_filename, cpu_model, &hwdefs[0]);
|
577 | c7ba218d | blueswir1 | } |
578 | c7ba218d | blueswir1 | |
579 | c7ba218d | blueswir1 | /* Sun4v hardware initialisation */
|
580 | c7ba218d | blueswir1 | static void sun4v_init(ram_addr_t RAM_size, int vga_ram_size, |
581 | c7ba218d | blueswir1 | const char *boot_devices, DisplayState *ds, |
582 | c7ba218d | blueswir1 | const char *kernel_filename, const char *kernel_cmdline, |
583 | c7ba218d | blueswir1 | const char *initrd_filename, const char *cpu_model) |
584 | c7ba218d | blueswir1 | { |
585 | c7ba218d | blueswir1 | sun4uv_init(RAM_size, vga_ram_size, boot_devices, ds, kernel_filename, |
586 | c7ba218d | blueswir1 | kernel_cmdline, initrd_filename, cpu_model, &hwdefs[1]);
|
587 | c7ba218d | blueswir1 | } |
588 | c7ba218d | blueswir1 | |
589 | e87231d4 | blueswir1 | /* Niagara hardware initialisation */
|
590 | e87231d4 | blueswir1 | static void niagara_init(ram_addr_t RAM_size, int vga_ram_size, |
591 | e87231d4 | blueswir1 | const char *boot_devices, DisplayState *ds, |
592 | e87231d4 | blueswir1 | const char *kernel_filename, const char *kernel_cmdline, |
593 | e87231d4 | blueswir1 | const char *initrd_filename, const char *cpu_model) |
594 | e87231d4 | blueswir1 | { |
595 | e87231d4 | blueswir1 | sun4uv_init(RAM_size, vga_ram_size, boot_devices, ds, kernel_filename, |
596 | e87231d4 | blueswir1 | kernel_cmdline, initrd_filename, cpu_model, &hwdefs[2]);
|
597 | e87231d4 | blueswir1 | } |
598 | e87231d4 | blueswir1 | |
599 | 3475187d | bellard | QEMUMachine sun4u_machine = { |
600 | 66de733b | blueswir1 | .name = "sun4u",
|
601 | 66de733b | blueswir1 | .desc = "Sun4u platform",
|
602 | 66de733b | blueswir1 | .init = sun4u_init, |
603 | 66de733b | blueswir1 | .ram_require = PROM_SIZE_MAX + VGA_RAM_SIZE, |
604 | f88e4b91 | blueswir1 | .nodisk_ok = 1,
|
605 | 1bcee014 | blueswir1 | .max_cpus = 1, // XXX for now |
606 | 3475187d | bellard | }; |
607 | c7ba218d | blueswir1 | |
608 | c7ba218d | blueswir1 | QEMUMachine sun4v_machine = { |
609 | 66de733b | blueswir1 | .name = "sun4v",
|
610 | 66de733b | blueswir1 | .desc = "Sun4v platform",
|
611 | 66de733b | blueswir1 | .init = sun4v_init, |
612 | 66de733b | blueswir1 | .ram_require = PROM_SIZE_MAX + VGA_RAM_SIZE, |
613 | f88e4b91 | blueswir1 | .nodisk_ok = 1,
|
614 | 1bcee014 | blueswir1 | .max_cpus = 1, // XXX for now |
615 | c7ba218d | blueswir1 | }; |
616 | e87231d4 | blueswir1 | |
617 | e87231d4 | blueswir1 | QEMUMachine niagara_machine = { |
618 | e87231d4 | blueswir1 | .name = "Niagara",
|
619 | e87231d4 | blueswir1 | .desc = "Sun4v platform, Niagara",
|
620 | e87231d4 | blueswir1 | .init = niagara_init, |
621 | e87231d4 | blueswir1 | .ram_require = PROM_SIZE_MAX + VGA_RAM_SIZE, |
622 | e87231d4 | blueswir1 | .nodisk_ok = 1,
|
623 | 1bcee014 | blueswir1 | .max_cpus = 1, // XXX for now |
624 | e87231d4 | blueswir1 | }; |