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1 | e69954b9 | pbrook | /*
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2 | e69954b9 | pbrook | * ARM AMBA Generic/Distributed Interrupt Controller
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3 | e69954b9 | pbrook | *
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4 | e69954b9 | pbrook | * Copyright (c) 2006 CodeSourcery.
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5 | e69954b9 | pbrook | * Written by Paul Brook
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6 | e69954b9 | pbrook | *
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7 | e69954b9 | pbrook | * This code is licenced under the GPL.
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8 | e69954b9 | pbrook | */
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9 | e69954b9 | pbrook | |
10 | e69954b9 | pbrook | /* TODO: Some variants of this controller can handle multiple CPUs.
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11 | e69954b9 | pbrook | Currently only single CPU operation is implemented. */
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12 | e69954b9 | pbrook | |
13 | e69954b9 | pbrook | #include "vl.h" |
14 | e69954b9 | pbrook | #include "arm_pic.h" |
15 | e69954b9 | pbrook | |
16 | e69954b9 | pbrook | //#define DEBUG_GIC
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17 | e69954b9 | pbrook | |
18 | e69954b9 | pbrook | #ifdef DEBUG_GIC
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19 | e69954b9 | pbrook | #define DPRINTF(fmt, args...) \
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20 | e69954b9 | pbrook | do { printf("arm_gic: " fmt , (int)s->base, ##args); } while (0) |
21 | e69954b9 | pbrook | #else
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22 | e69954b9 | pbrook | #define DPRINTF(fmt, args...) do {} while(0) |
23 | e69954b9 | pbrook | #endif
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24 | e69954b9 | pbrook | |
25 | e69954b9 | pbrook | /* Distributed interrupt controller. */
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26 | e69954b9 | pbrook | |
27 | e69954b9 | pbrook | static const uint8_t gic_id[] = |
28 | e69954b9 | pbrook | { 0x90, 0x13, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 }; |
29 | e69954b9 | pbrook | |
30 | e69954b9 | pbrook | #define GIC_NIRQ 96 |
31 | e69954b9 | pbrook | |
32 | e69954b9 | pbrook | typedef struct gic_irq_state |
33 | e69954b9 | pbrook | { |
34 | e69954b9 | pbrook | unsigned enabled:1; |
35 | e69954b9 | pbrook | unsigned pending:1; |
36 | e69954b9 | pbrook | unsigned active:1; |
37 | e69954b9 | pbrook | unsigned level:1; |
38 | e69954b9 | pbrook | unsigned model:1; /* 0 = 1:N, 1 = N:N */ |
39 | e69954b9 | pbrook | unsigned trigger:1; /* nonzero = edge triggered. */ |
40 | e69954b9 | pbrook | } gic_irq_state; |
41 | e69954b9 | pbrook | |
42 | e69954b9 | pbrook | #define GIC_SET_ENABLED(irq) s->irq_state[irq].enabled = 1 |
43 | e69954b9 | pbrook | #define GIC_CLEAR_ENABLED(irq) s->irq_state[irq].enabled = 0 |
44 | e69954b9 | pbrook | #define GIC_TEST_ENABLED(irq) s->irq_state[irq].enabled
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45 | e69954b9 | pbrook | #define GIC_SET_PENDING(irq) s->irq_state[irq].pending = 1 |
46 | e69954b9 | pbrook | #define GIC_CLEAR_PENDING(irq) s->irq_state[irq].pending = 0 |
47 | e69954b9 | pbrook | #define GIC_TEST_PENDING(irq) s->irq_state[irq].pending
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48 | e69954b9 | pbrook | #define GIC_SET_ACTIVE(irq) s->irq_state[irq].active = 1 |
49 | e69954b9 | pbrook | #define GIC_CLEAR_ACTIVE(irq) s->irq_state[irq].active = 0 |
50 | e69954b9 | pbrook | #define GIC_TEST_ACTIVE(irq) s->irq_state[irq].active
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51 | e69954b9 | pbrook | #define GIC_SET_MODEL(irq) s->irq_state[irq].model = 1 |
52 | e69954b9 | pbrook | #define GIC_CLEAR_MODEL(irq) s->irq_state[irq].model = 0 |
53 | e69954b9 | pbrook | #define GIC_TEST_MODEL(irq) s->irq_state[irq].model
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54 | e69954b9 | pbrook | #define GIC_SET_LEVEL(irq) s->irq_state[irq].level = 1 |
55 | e69954b9 | pbrook | #define GIC_CLEAR_LEVEL(irq) s->irq_state[irq].level = 0 |
56 | e69954b9 | pbrook | #define GIC_TEST_LEVEL(irq) s->irq_state[irq].level
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57 | e69954b9 | pbrook | #define GIC_SET_TRIGGER(irq) s->irq_state[irq].trigger = 1 |
58 | e69954b9 | pbrook | #define GIC_CLEAR_TRIGGER(irq) s->irq_state[irq].trigger = 0 |
59 | e69954b9 | pbrook | #define GIC_TEST_TRIGGER(irq) s->irq_state[irq].trigger
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60 | e69954b9 | pbrook | |
61 | e69954b9 | pbrook | typedef struct gic_state |
62 | e69954b9 | pbrook | { |
63 | e69954b9 | pbrook | arm_pic_handler handler; |
64 | e69954b9 | pbrook | uint32_t base; |
65 | e69954b9 | pbrook | void *parent;
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66 | e69954b9 | pbrook | int parent_irq;
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67 | e69954b9 | pbrook | int enabled;
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68 | e69954b9 | pbrook | int cpu_enabled;
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69 | e69954b9 | pbrook | |
70 | e69954b9 | pbrook | gic_irq_state irq_state[GIC_NIRQ]; |
71 | e69954b9 | pbrook | int irq_target[GIC_NIRQ];
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72 | e69954b9 | pbrook | int priority[GIC_NIRQ];
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73 | e69954b9 | pbrook | int last_active[GIC_NIRQ];
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74 | e69954b9 | pbrook | |
75 | e69954b9 | pbrook | int priority_mask;
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76 | e69954b9 | pbrook | int running_irq;
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77 | e69954b9 | pbrook | int running_priority;
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78 | e69954b9 | pbrook | int current_pending;
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79 | e69954b9 | pbrook | } gic_state; |
80 | e69954b9 | pbrook | |
81 | e69954b9 | pbrook | /* TODO: Many places that call this routine could be optimized. */
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82 | e69954b9 | pbrook | /* Update interrupt status after enabled or pending bits have been changed. */
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83 | e69954b9 | pbrook | static void gic_update(gic_state *s) |
84 | e69954b9 | pbrook | { |
85 | e69954b9 | pbrook | int best_irq;
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86 | e69954b9 | pbrook | int best_prio;
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87 | e69954b9 | pbrook | int irq;
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88 | e69954b9 | pbrook | |
89 | e69954b9 | pbrook | s->current_pending = 1023;
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90 | e69954b9 | pbrook | if (!s->enabled || !s->cpu_enabled) {
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91 | e69954b9 | pbrook | pic_set_irq_new(s->parent, s->parent_irq, 0);
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92 | e69954b9 | pbrook | return;
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93 | e69954b9 | pbrook | } |
94 | e69954b9 | pbrook | best_prio = 0x100;
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95 | e69954b9 | pbrook | best_irq = 1023;
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96 | e69954b9 | pbrook | for (irq = 0; irq < 96; irq++) { |
97 | e69954b9 | pbrook | if (GIC_TEST_ENABLED(irq) && GIC_TEST_PENDING(irq)) {
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98 | e69954b9 | pbrook | if (s->priority[irq] < best_prio) {
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99 | e69954b9 | pbrook | best_prio = s->priority[irq]; |
100 | e69954b9 | pbrook | best_irq = irq; |
101 | e69954b9 | pbrook | } |
102 | e69954b9 | pbrook | } |
103 | e69954b9 | pbrook | } |
104 | e69954b9 | pbrook | if (best_prio > s->priority_mask) {
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105 | e69954b9 | pbrook | pic_set_irq_new(s->parent, s->parent_irq, 0);
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106 | e69954b9 | pbrook | } else {
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107 | e69954b9 | pbrook | s->current_pending = best_irq; |
108 | e69954b9 | pbrook | if (best_prio < s->running_priority) {
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109 | e69954b9 | pbrook | DPRINTF("Raised pending IRQ %d\n", best_irq);
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110 | e69954b9 | pbrook | pic_set_irq_new(s->parent, s->parent_irq, 1);
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111 | e69954b9 | pbrook | } |
112 | e69954b9 | pbrook | } |
113 | e69954b9 | pbrook | } |
114 | e69954b9 | pbrook | |
115 | e69954b9 | pbrook | static void gic_set_irq(void *opaque, int irq, int level) |
116 | e69954b9 | pbrook | { |
117 | e69954b9 | pbrook | gic_state *s = (gic_state *)opaque; |
118 | e69954b9 | pbrook | /* The first external input line is internal interrupt 32. */
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119 | e69954b9 | pbrook | irq += 32;
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120 | e69954b9 | pbrook | if (level == GIC_TEST_LEVEL(irq))
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121 | e69954b9 | pbrook | return;
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122 | e69954b9 | pbrook | |
123 | e69954b9 | pbrook | if (level) {
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124 | e69954b9 | pbrook | GIC_SET_LEVEL(irq); |
125 | e69954b9 | pbrook | if (GIC_TEST_TRIGGER(irq) || GIC_TEST_ENABLED(irq)) {
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126 | e69954b9 | pbrook | DPRINTF("Set %d pending\n", irq);
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127 | e69954b9 | pbrook | GIC_SET_PENDING(irq); |
128 | e69954b9 | pbrook | } |
129 | e69954b9 | pbrook | } else {
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130 | e69954b9 | pbrook | GIC_CLEAR_LEVEL(irq); |
131 | e69954b9 | pbrook | } |
132 | e69954b9 | pbrook | gic_update(s); |
133 | e69954b9 | pbrook | } |
134 | e69954b9 | pbrook | |
135 | e69954b9 | pbrook | static void gic_set_running_irq(gic_state *s, int irq) |
136 | e69954b9 | pbrook | { |
137 | e69954b9 | pbrook | s->running_irq = irq; |
138 | e69954b9 | pbrook | s->running_priority = s->priority[irq]; |
139 | e69954b9 | pbrook | gic_update(s); |
140 | e69954b9 | pbrook | } |
141 | e69954b9 | pbrook | |
142 | e69954b9 | pbrook | static uint32_t gic_acknowledge_irq(gic_state *s)
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143 | e69954b9 | pbrook | { |
144 | e69954b9 | pbrook | int new_irq;
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145 | e69954b9 | pbrook | new_irq = s->current_pending; |
146 | e69954b9 | pbrook | if (new_irq == 1023 || s->priority[new_irq] >= s->running_priority) { |
147 | e69954b9 | pbrook | DPRINTF("ACK no pending IRQ\n");
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148 | e69954b9 | pbrook | return 1023; |
149 | e69954b9 | pbrook | } |
150 | e69954b9 | pbrook | pic_set_irq_new(s->parent, s->parent_irq, 0);
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151 | e69954b9 | pbrook | s->last_active[new_irq] = s->running_irq; |
152 | e69954b9 | pbrook | /* For level triggered interrupts we clear the pending bit while
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153 | e69954b9 | pbrook | the interrupt is active. */
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154 | e69954b9 | pbrook | GIC_CLEAR_PENDING(new_irq); |
155 | e69954b9 | pbrook | gic_set_running_irq(s, new_irq); |
156 | e69954b9 | pbrook | DPRINTF("ACK %d\n", new_irq);
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157 | e69954b9 | pbrook | return new_irq;
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158 | e69954b9 | pbrook | } |
159 | e69954b9 | pbrook | |
160 | e69954b9 | pbrook | static void gic_complete_irq(gic_state * s, int irq) |
161 | e69954b9 | pbrook | { |
162 | e69954b9 | pbrook | int update = 0; |
163 | e69954b9 | pbrook | DPRINTF("EIO %d\n", irq);
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164 | e69954b9 | pbrook | if (s->running_irq == 1023) |
165 | e69954b9 | pbrook | return; /* No active IRQ. */ |
166 | e69954b9 | pbrook | if (irq != 1023) { |
167 | e69954b9 | pbrook | /* Mark level triggered interrupts as pending if they are still
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168 | e69954b9 | pbrook | raised. */
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169 | e69954b9 | pbrook | if (!GIC_TEST_TRIGGER(irq) && GIC_TEST_ENABLED(irq)
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170 | e69954b9 | pbrook | && GIC_TEST_LEVEL(irq)) { |
171 | e69954b9 | pbrook | GIC_SET_PENDING(irq); |
172 | e69954b9 | pbrook | update = 1;
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173 | e69954b9 | pbrook | } |
174 | e69954b9 | pbrook | } |
175 | e69954b9 | pbrook | if (irq != s->running_irq) {
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176 | e69954b9 | pbrook | /* Complete an IRQ that is not currently running. */
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177 | e69954b9 | pbrook | int tmp = s->running_irq;
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178 | e69954b9 | pbrook | while (s->last_active[tmp] != 1023) { |
179 | e69954b9 | pbrook | if (s->last_active[tmp] == irq) {
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180 | e69954b9 | pbrook | s->last_active[tmp] = s->last_active[irq]; |
181 | e69954b9 | pbrook | break;
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182 | e69954b9 | pbrook | } |
183 | e69954b9 | pbrook | tmp = s->last_active[tmp]; |
184 | e69954b9 | pbrook | } |
185 | e69954b9 | pbrook | if (update) {
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186 | e69954b9 | pbrook | gic_update(s); |
187 | e69954b9 | pbrook | } |
188 | e69954b9 | pbrook | } else {
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189 | e69954b9 | pbrook | /* Complete the current running IRQ. */
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190 | e69954b9 | pbrook | gic_set_running_irq(s, s->last_active[s->running_irq]); |
191 | e69954b9 | pbrook | } |
192 | e69954b9 | pbrook | } |
193 | e69954b9 | pbrook | |
194 | e69954b9 | pbrook | static uint32_t gic_dist_readb(void *opaque, target_phys_addr_t offset) |
195 | e69954b9 | pbrook | { |
196 | e69954b9 | pbrook | gic_state *s = (gic_state *)opaque; |
197 | e69954b9 | pbrook | uint32_t res; |
198 | e69954b9 | pbrook | int irq;
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199 | e69954b9 | pbrook | int i;
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200 | e69954b9 | pbrook | |
201 | e69954b9 | pbrook | offset -= s->base + 0x1000;
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202 | e69954b9 | pbrook | if (offset < 0x100) { |
203 | e69954b9 | pbrook | if (offset == 0) |
204 | e69954b9 | pbrook | return s->enabled;
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205 | e69954b9 | pbrook | if (offset == 4) |
206 | e69954b9 | pbrook | return (GIC_NIRQ / 32) - 1; |
207 | e69954b9 | pbrook | if (offset < 0x08) |
208 | e69954b9 | pbrook | return 0; |
209 | e69954b9 | pbrook | goto bad_reg;
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210 | e69954b9 | pbrook | } else if (offset < 0x200) { |
211 | e69954b9 | pbrook | /* Interrupt Set/Clear Enable. */
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212 | e69954b9 | pbrook | if (offset < 0x180) |
213 | e69954b9 | pbrook | irq = (offset - 0x100) * 8; |
214 | e69954b9 | pbrook | else
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215 | e69954b9 | pbrook | irq = (offset - 0x180) * 8; |
216 | e69954b9 | pbrook | if (irq >= GIC_NIRQ)
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217 | e69954b9 | pbrook | goto bad_reg;
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218 | e69954b9 | pbrook | res = 0;
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219 | e69954b9 | pbrook | for (i = 0; i < 8; i++) { |
220 | e69954b9 | pbrook | if (GIC_TEST_ENABLED(irq + i)) {
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221 | e69954b9 | pbrook | res |= (1 << i);
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222 | e69954b9 | pbrook | } |
223 | e69954b9 | pbrook | } |
224 | e69954b9 | pbrook | } else if (offset < 0x300) { |
225 | e69954b9 | pbrook | /* Interrupt Set/Clear Pending. */
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226 | e69954b9 | pbrook | if (offset < 0x280) |
227 | e69954b9 | pbrook | irq = (offset - 0x200) * 8; |
228 | e69954b9 | pbrook | else
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229 | e69954b9 | pbrook | irq = (offset - 0x280) * 8; |
230 | e69954b9 | pbrook | if (irq >= GIC_NIRQ)
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231 | e69954b9 | pbrook | goto bad_reg;
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232 | e69954b9 | pbrook | res = 0;
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233 | e69954b9 | pbrook | for (i = 0; i < 8; i++) { |
234 | e69954b9 | pbrook | if (GIC_TEST_PENDING(irq + i)) {
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235 | e69954b9 | pbrook | res |= (1 << i);
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236 | e69954b9 | pbrook | } |
237 | e69954b9 | pbrook | } |
238 | e69954b9 | pbrook | } else if (offset < 0x400) { |
239 | e69954b9 | pbrook | /* Interrupt Active. */
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240 | e69954b9 | pbrook | irq = (offset - 0x300) * 8; |
241 | e69954b9 | pbrook | if (irq >= GIC_NIRQ)
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242 | e69954b9 | pbrook | goto bad_reg;
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243 | e69954b9 | pbrook | res = 0;
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244 | e69954b9 | pbrook | for (i = 0; i < 8; i++) { |
245 | e69954b9 | pbrook | if (GIC_TEST_ACTIVE(irq + i)) {
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246 | e69954b9 | pbrook | res |= (1 << i);
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247 | e69954b9 | pbrook | } |
248 | e69954b9 | pbrook | } |
249 | e69954b9 | pbrook | } else if (offset < 0x800) { |
250 | e69954b9 | pbrook | /* Interrupt Priority. */
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251 | e69954b9 | pbrook | irq = offset - 0x400;
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252 | e69954b9 | pbrook | if (irq >= GIC_NIRQ)
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253 | e69954b9 | pbrook | goto bad_reg;
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254 | e69954b9 | pbrook | res = s->priority[irq]; |
255 | e69954b9 | pbrook | } else if (offset < 0xc00) { |
256 | e69954b9 | pbrook | /* Interrupt CPU Target. */
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257 | e69954b9 | pbrook | irq = offset - 0x800;
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258 | e69954b9 | pbrook | if (irq >= GIC_NIRQ)
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259 | e69954b9 | pbrook | goto bad_reg;
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260 | e69954b9 | pbrook | res = s->irq_target[irq]; |
261 | e69954b9 | pbrook | } else if (offset < 0xf00) { |
262 | e69954b9 | pbrook | /* Interrupt Configuration. */
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263 | e69954b9 | pbrook | irq = (offset - 0xc00) * 2; |
264 | e69954b9 | pbrook | if (irq >= GIC_NIRQ)
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265 | e69954b9 | pbrook | goto bad_reg;
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266 | e69954b9 | pbrook | res = 0;
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267 | e69954b9 | pbrook | for (i = 0; i < 4; i++) { |
268 | e69954b9 | pbrook | if (GIC_TEST_MODEL(irq + i))
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269 | e69954b9 | pbrook | res |= (1 << (i * 2)); |
270 | e69954b9 | pbrook | if (GIC_TEST_TRIGGER(irq + i))
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271 | e69954b9 | pbrook | res |= (2 << (i * 2)); |
272 | e69954b9 | pbrook | } |
273 | e69954b9 | pbrook | } else if (offset < 0xfe0) { |
274 | e69954b9 | pbrook | goto bad_reg;
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275 | e69954b9 | pbrook | } else /* offset >= 0xfe0 */ { |
276 | e69954b9 | pbrook | if (offset & 3) { |
277 | e69954b9 | pbrook | res = 0;
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278 | e69954b9 | pbrook | } else {
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279 | e69954b9 | pbrook | res = gic_id[(offset - 0xfe0) >> 2]; |
280 | e69954b9 | pbrook | } |
281 | e69954b9 | pbrook | } |
282 | e69954b9 | pbrook | return res;
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283 | e69954b9 | pbrook | bad_reg:
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284 | e69954b9 | pbrook | cpu_abort (cpu_single_env, "gic_dist_readb: Bad offset %x\n", offset);
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285 | e69954b9 | pbrook | return 0; |
286 | e69954b9 | pbrook | } |
287 | e69954b9 | pbrook | |
288 | e69954b9 | pbrook | static uint32_t gic_dist_readw(void *opaque, target_phys_addr_t offset) |
289 | e69954b9 | pbrook | { |
290 | e69954b9 | pbrook | uint32_t val; |
291 | e69954b9 | pbrook | val = gic_dist_readb(opaque, offset); |
292 | e69954b9 | pbrook | val |= gic_dist_readb(opaque, offset + 1) << 8; |
293 | e69954b9 | pbrook | return val;
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294 | e69954b9 | pbrook | } |
295 | e69954b9 | pbrook | |
296 | e69954b9 | pbrook | static uint32_t gic_dist_readl(void *opaque, target_phys_addr_t offset) |
297 | e69954b9 | pbrook | { |
298 | e69954b9 | pbrook | uint32_t val; |
299 | e69954b9 | pbrook | val = gic_dist_readw(opaque, offset); |
300 | e69954b9 | pbrook | val |= gic_dist_readw(opaque, offset + 2) << 16; |
301 | e69954b9 | pbrook | return val;
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302 | e69954b9 | pbrook | } |
303 | e69954b9 | pbrook | |
304 | e69954b9 | pbrook | static void gic_dist_writeb(void *opaque, target_phys_addr_t offset, |
305 | e69954b9 | pbrook | uint32_t value) |
306 | e69954b9 | pbrook | { |
307 | e69954b9 | pbrook | gic_state *s = (gic_state *)opaque; |
308 | e69954b9 | pbrook | int irq;
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309 | e69954b9 | pbrook | int i;
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310 | e69954b9 | pbrook | |
311 | e69954b9 | pbrook | offset -= s->base + 0x1000;
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312 | e69954b9 | pbrook | if (offset < 0x100) { |
313 | e69954b9 | pbrook | if (offset == 0) { |
314 | e69954b9 | pbrook | s->enabled = (value & 1);
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315 | e69954b9 | pbrook | DPRINTF("Distribution %sabled\n", s->enabled ? "En" : "Dis"); |
316 | e69954b9 | pbrook | } else if (offset < 4) { |
317 | e69954b9 | pbrook | /* ignored. */
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318 | e69954b9 | pbrook | } else {
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319 | e69954b9 | pbrook | goto bad_reg;
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320 | e69954b9 | pbrook | } |
321 | e69954b9 | pbrook | } else if (offset < 0x180) { |
322 | e69954b9 | pbrook | /* Interrupt Set Enable. */
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323 | e69954b9 | pbrook | irq = (offset - 0x100) * 8; |
324 | e69954b9 | pbrook | if (irq >= GIC_NIRQ)
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325 | e69954b9 | pbrook | goto bad_reg;
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326 | e69954b9 | pbrook | for (i = 0; i < 8; i++) { |
327 | e69954b9 | pbrook | if (value & (1 << i)) { |
328 | e69954b9 | pbrook | if (!GIC_TEST_ENABLED(irq + i))
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329 | e69954b9 | pbrook | DPRINTF("Enabled IRQ %d\n", irq + i);
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330 | e69954b9 | pbrook | GIC_SET_ENABLED(irq + i); |
331 | e69954b9 | pbrook | /* If a raised level triggered IRQ enabled then mark
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332 | e69954b9 | pbrook | is as pending. */
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333 | e69954b9 | pbrook | if (GIC_TEST_LEVEL(irq + i) && !GIC_TEST_TRIGGER(irq + i))
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334 | e69954b9 | pbrook | GIC_SET_PENDING(irq + i); |
335 | e69954b9 | pbrook | } |
336 | e69954b9 | pbrook | } |
337 | e69954b9 | pbrook | } else if (offset < 0x200) { |
338 | e69954b9 | pbrook | /* Interrupt Clear Enable. */
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339 | e69954b9 | pbrook | irq = (offset - 0x180) * 8; |
340 | e69954b9 | pbrook | if (irq >= GIC_NIRQ)
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341 | e69954b9 | pbrook | goto bad_reg;
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342 | e69954b9 | pbrook | for (i = 0; i < 8; i++) { |
343 | e69954b9 | pbrook | if (value & (1 << i)) { |
344 | e69954b9 | pbrook | if (GIC_TEST_ENABLED(irq + i))
|
345 | e69954b9 | pbrook | DPRINTF("Disabled IRQ %d\n", irq + i);
|
346 | e69954b9 | pbrook | GIC_CLEAR_ENABLED(irq + i); |
347 | e69954b9 | pbrook | } |
348 | e69954b9 | pbrook | } |
349 | e69954b9 | pbrook | } else if (offset < 0x280) { |
350 | e69954b9 | pbrook | /* Interrupt Set Pending. */
|
351 | e69954b9 | pbrook | irq = (offset - 0x200) * 8; |
352 | e69954b9 | pbrook | if (irq >= GIC_NIRQ)
|
353 | e69954b9 | pbrook | goto bad_reg;
|
354 | e69954b9 | pbrook | for (i = 0; i < 8; i++) { |
355 | e69954b9 | pbrook | if (value & (1 << i)) { |
356 | e69954b9 | pbrook | GIC_SET_PENDING(irq + i); |
357 | e69954b9 | pbrook | } |
358 | e69954b9 | pbrook | } |
359 | e69954b9 | pbrook | } else if (offset < 0x300) { |
360 | e69954b9 | pbrook | /* Interrupt Clear Pending. */
|
361 | e69954b9 | pbrook | irq = (offset - 0x280) * 8; |
362 | e69954b9 | pbrook | if (irq >= GIC_NIRQ)
|
363 | e69954b9 | pbrook | goto bad_reg;
|
364 | e69954b9 | pbrook | for (i = 0; i < 8; i++) { |
365 | e69954b9 | pbrook | if (value & (1 << i)) { |
366 | e69954b9 | pbrook | GIC_CLEAR_PENDING(irq + i); |
367 | e69954b9 | pbrook | } |
368 | e69954b9 | pbrook | } |
369 | e69954b9 | pbrook | } else if (offset < 0x400) { |
370 | e69954b9 | pbrook | /* Interrupt Active. */
|
371 | e69954b9 | pbrook | goto bad_reg;
|
372 | e69954b9 | pbrook | } else if (offset < 0x800) { |
373 | e69954b9 | pbrook | /* Interrupt Priority. */
|
374 | e69954b9 | pbrook | irq = offset - 0x400;
|
375 | e69954b9 | pbrook | if (irq >= GIC_NIRQ)
|
376 | e69954b9 | pbrook | goto bad_reg;
|
377 | e69954b9 | pbrook | s->priority[irq] = value; |
378 | e69954b9 | pbrook | } else if (offset < 0xc00) { |
379 | e69954b9 | pbrook | /* Interrupt CPU Target. */
|
380 | e69954b9 | pbrook | irq = offset - 0x800;
|
381 | e69954b9 | pbrook | if (irq >= GIC_NIRQ)
|
382 | e69954b9 | pbrook | goto bad_reg;
|
383 | e69954b9 | pbrook | s->irq_target[irq] = value; |
384 | e69954b9 | pbrook | } else if (offset < 0xf00) { |
385 | e69954b9 | pbrook | /* Interrupt Configuration. */
|
386 | 326199c2 | pbrook | irq = (offset - 0xc00) * 4; |
387 | e69954b9 | pbrook | if (irq >= GIC_NIRQ)
|
388 | e69954b9 | pbrook | goto bad_reg;
|
389 | e69954b9 | pbrook | for (i = 0; i < 4; i++) { |
390 | e69954b9 | pbrook | if (value & (1 << (i * 2))) { |
391 | e69954b9 | pbrook | GIC_SET_MODEL(irq + i); |
392 | e69954b9 | pbrook | } else {
|
393 | e69954b9 | pbrook | GIC_CLEAR_MODEL(irq + i); |
394 | e69954b9 | pbrook | } |
395 | e69954b9 | pbrook | if (value & (2 << (i * 2))) { |
396 | e69954b9 | pbrook | GIC_SET_TRIGGER(irq + i); |
397 | e69954b9 | pbrook | } else {
|
398 | e69954b9 | pbrook | GIC_CLEAR_TRIGGER(irq + i); |
399 | e69954b9 | pbrook | } |
400 | e69954b9 | pbrook | } |
401 | e69954b9 | pbrook | } else {
|
402 | e69954b9 | pbrook | /* 0xf00 is only handled for word writes. */
|
403 | e69954b9 | pbrook | goto bad_reg;
|
404 | e69954b9 | pbrook | } |
405 | e69954b9 | pbrook | gic_update(s); |
406 | e69954b9 | pbrook | return;
|
407 | e69954b9 | pbrook | bad_reg:
|
408 | e69954b9 | pbrook | cpu_abort (cpu_single_env, "gic_dist_writeb: Bad offset %x\n", offset);
|
409 | e69954b9 | pbrook | } |
410 | e69954b9 | pbrook | |
411 | e69954b9 | pbrook | static void gic_dist_writew(void *opaque, target_phys_addr_t offset, |
412 | e69954b9 | pbrook | uint32_t value) |
413 | e69954b9 | pbrook | { |
414 | e69954b9 | pbrook | gic_state *s = (gic_state *)opaque; |
415 | e69954b9 | pbrook | if (offset - s->base == 0xf00) { |
416 | e69954b9 | pbrook | GIC_SET_PENDING(value & 0x3ff);
|
417 | e69954b9 | pbrook | gic_update(s); |
418 | e69954b9 | pbrook | return;
|
419 | e69954b9 | pbrook | } |
420 | e69954b9 | pbrook | gic_dist_writeb(opaque, offset, value & 0xff);
|
421 | e69954b9 | pbrook | gic_dist_writeb(opaque, offset + 1, value >> 8); |
422 | e69954b9 | pbrook | } |
423 | e69954b9 | pbrook | |
424 | e69954b9 | pbrook | static void gic_dist_writel(void *opaque, target_phys_addr_t offset, |
425 | e69954b9 | pbrook | uint32_t value) |
426 | e69954b9 | pbrook | { |
427 | e69954b9 | pbrook | gic_dist_writew(opaque, offset, value & 0xffff);
|
428 | e69954b9 | pbrook | gic_dist_writew(opaque, offset + 2, value >> 16); |
429 | e69954b9 | pbrook | } |
430 | e69954b9 | pbrook | |
431 | e69954b9 | pbrook | static CPUReadMemoryFunc *gic_dist_readfn[] = {
|
432 | e69954b9 | pbrook | gic_dist_readb, |
433 | e69954b9 | pbrook | gic_dist_readw, |
434 | e69954b9 | pbrook | gic_dist_readl |
435 | e69954b9 | pbrook | }; |
436 | e69954b9 | pbrook | |
437 | e69954b9 | pbrook | static CPUWriteMemoryFunc *gic_dist_writefn[] = {
|
438 | e69954b9 | pbrook | gic_dist_writeb, |
439 | e69954b9 | pbrook | gic_dist_writew, |
440 | e69954b9 | pbrook | gic_dist_writel |
441 | e69954b9 | pbrook | }; |
442 | e69954b9 | pbrook | |
443 | e69954b9 | pbrook | static uint32_t gic_cpu_read(void *opaque, target_phys_addr_t offset) |
444 | e69954b9 | pbrook | { |
445 | e69954b9 | pbrook | gic_state *s = (gic_state *)opaque; |
446 | e69954b9 | pbrook | offset -= s->base; |
447 | e69954b9 | pbrook | switch (offset) {
|
448 | e69954b9 | pbrook | case 0x00: /* Control */ |
449 | e69954b9 | pbrook | return s->cpu_enabled;
|
450 | e69954b9 | pbrook | case 0x04: /* Priority mask */ |
451 | e69954b9 | pbrook | return s->priority_mask;
|
452 | e69954b9 | pbrook | case 0x08: /* Binary Point */ |
453 | e69954b9 | pbrook | /* ??? Not implemented. */
|
454 | e69954b9 | pbrook | return 0; |
455 | e69954b9 | pbrook | case 0x0c: /* Acknowledge */ |
456 | e69954b9 | pbrook | return gic_acknowledge_irq(s);
|
457 | e69954b9 | pbrook | case 0x14: /* Runing Priority */ |
458 | e69954b9 | pbrook | return s->running_priority;
|
459 | e69954b9 | pbrook | case 0x18: /* Highest Pending Interrupt */ |
460 | e69954b9 | pbrook | return s->current_pending;
|
461 | e69954b9 | pbrook | default:
|
462 | e69954b9 | pbrook | cpu_abort (cpu_single_env, "gic_cpu_writeb: Bad offset %x\n", offset);
|
463 | e69954b9 | pbrook | return 0; |
464 | e69954b9 | pbrook | } |
465 | e69954b9 | pbrook | } |
466 | e69954b9 | pbrook | |
467 | e69954b9 | pbrook | static void gic_cpu_write(void *opaque, target_phys_addr_t offset, |
468 | e69954b9 | pbrook | uint32_t value) |
469 | e69954b9 | pbrook | { |
470 | e69954b9 | pbrook | gic_state *s = (gic_state *)opaque; |
471 | e69954b9 | pbrook | offset -= s->base; |
472 | e69954b9 | pbrook | switch (offset) {
|
473 | e69954b9 | pbrook | case 0x00: /* Control */ |
474 | e69954b9 | pbrook | s->cpu_enabled = (value & 1);
|
475 | e69954b9 | pbrook | DPRINTF("CPU %sabled\n", s->cpu_enabled ? "En" : "Dis"); |
476 | e69954b9 | pbrook | break;
|
477 | e69954b9 | pbrook | case 0x04: /* Priority mask */ |
478 | e69954b9 | pbrook | s->priority_mask = (value & 0x3ff);
|
479 | e69954b9 | pbrook | break;
|
480 | e69954b9 | pbrook | case 0x08: /* Binary Point */ |
481 | e69954b9 | pbrook | /* ??? Not implemented. */
|
482 | e69954b9 | pbrook | break;
|
483 | e69954b9 | pbrook | case 0x10: /* End Of Interrupt */ |
484 | e69954b9 | pbrook | return gic_complete_irq(s, value & 0x3ff); |
485 | e69954b9 | pbrook | default:
|
486 | e69954b9 | pbrook | cpu_abort (cpu_single_env, "gic_cpu_writeb: Bad offset %x\n", offset);
|
487 | e69954b9 | pbrook | return;
|
488 | e69954b9 | pbrook | } |
489 | e69954b9 | pbrook | gic_update(s); |
490 | e69954b9 | pbrook | } |
491 | e69954b9 | pbrook | |
492 | e69954b9 | pbrook | static CPUReadMemoryFunc *gic_cpu_readfn[] = {
|
493 | e69954b9 | pbrook | gic_cpu_read, |
494 | e69954b9 | pbrook | gic_cpu_read, |
495 | e69954b9 | pbrook | gic_cpu_read |
496 | e69954b9 | pbrook | }; |
497 | e69954b9 | pbrook | |
498 | e69954b9 | pbrook | static CPUWriteMemoryFunc *gic_cpu_writefn[] = {
|
499 | e69954b9 | pbrook | gic_cpu_write, |
500 | e69954b9 | pbrook | gic_cpu_write, |
501 | e69954b9 | pbrook | gic_cpu_write |
502 | e69954b9 | pbrook | }; |
503 | e69954b9 | pbrook | |
504 | e69954b9 | pbrook | static void gic_reset(gic_state *s) |
505 | e69954b9 | pbrook | { |
506 | e69954b9 | pbrook | int i;
|
507 | e69954b9 | pbrook | memset(s->irq_state, 0, GIC_NIRQ * sizeof(gic_irq_state)); |
508 | e69954b9 | pbrook | s->priority_mask = 0xf0;
|
509 | e69954b9 | pbrook | s->current_pending = 1023;
|
510 | e69954b9 | pbrook | s->running_irq = 1023;
|
511 | e69954b9 | pbrook | s->running_priority = 0x100;
|
512 | e69954b9 | pbrook | for (i = 0; i < 15; i++) { |
513 | e69954b9 | pbrook | GIC_SET_ENABLED(i); |
514 | e69954b9 | pbrook | GIC_SET_TRIGGER(i); |
515 | e69954b9 | pbrook | } |
516 | e69954b9 | pbrook | s->enabled = 0;
|
517 | e69954b9 | pbrook | s->cpu_enabled = 0;
|
518 | e69954b9 | pbrook | } |
519 | e69954b9 | pbrook | |
520 | e69954b9 | pbrook | void *arm_gic_init(uint32_t base, void *parent, int parent_irq) |
521 | e69954b9 | pbrook | { |
522 | e69954b9 | pbrook | gic_state *s; |
523 | e69954b9 | pbrook | int iomemtype;
|
524 | e69954b9 | pbrook | |
525 | e69954b9 | pbrook | s = (gic_state *)qemu_mallocz(sizeof(gic_state));
|
526 | e69954b9 | pbrook | if (!s)
|
527 | e69954b9 | pbrook | return NULL; |
528 | e69954b9 | pbrook | s->handler = gic_set_irq; |
529 | e69954b9 | pbrook | s->parent = parent; |
530 | e69954b9 | pbrook | s->parent_irq = parent_irq; |
531 | e69954b9 | pbrook | if (base != 0xffffffff) { |
532 | e69954b9 | pbrook | iomemtype = cpu_register_io_memory(0, gic_cpu_readfn,
|
533 | e69954b9 | pbrook | gic_cpu_writefn, s); |
534 | e69954b9 | pbrook | cpu_register_physical_memory(base, 0x00000fff, iomemtype);
|
535 | e69954b9 | pbrook | iomemtype = cpu_register_io_memory(0, gic_dist_readfn,
|
536 | e69954b9 | pbrook | gic_dist_writefn, s); |
537 | e69954b9 | pbrook | cpu_register_physical_memory(base + 0x1000, 0x00000fff, iomemtype); |
538 | e69954b9 | pbrook | s->base = base; |
539 | e69954b9 | pbrook | } else {
|
540 | e69954b9 | pbrook | s->base = 0;
|
541 | e69954b9 | pbrook | } |
542 | e69954b9 | pbrook | gic_reset(s); |
543 | e69954b9 | pbrook | return s;
|
544 | e69954b9 | pbrook | } |