root / hw / arm_gic.c @ 7105b056
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1 | 5fafdf24 | ths | /*
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2 | 9ee6e8bb | pbrook | * ARM Generic/Distributed Interrupt Controller
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3 | e69954b9 | pbrook | *
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4 | 9ee6e8bb | pbrook | * Copyright (c) 2006-2007 CodeSourcery.
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5 | e69954b9 | pbrook | * Written by Paul Brook
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6 | e69954b9 | pbrook | *
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7 | e69954b9 | pbrook | * This code is licenced under the GPL.
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8 | e69954b9 | pbrook | */
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9 | e69954b9 | pbrook | |
10 | 9ee6e8bb | pbrook | /* This file contains implementation code for the RealView EB interrupt
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11 | 9ee6e8bb | pbrook | controller, MPCore distributed interrupt controller and ARMv7-M
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12 | 9ee6e8bb | pbrook | Nested Vectored Interrupt Controller. */
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13 | e69954b9 | pbrook | |
14 | e69954b9 | pbrook | //#define DEBUG_GIC
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15 | e69954b9 | pbrook | |
16 | e69954b9 | pbrook | #ifdef DEBUG_GIC
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17 | 001faf32 | Blue Swirl | #define DPRINTF(fmt, ...) \
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18 | 001faf32 | Blue Swirl | do { printf("arm_gic: " fmt , ## __VA_ARGS__); } while (0) |
19 | e69954b9 | pbrook | #else
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20 | 001faf32 | Blue Swirl | #define DPRINTF(fmt, ...) do {} while(0) |
21 | e69954b9 | pbrook | #endif
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22 | e69954b9 | pbrook | |
23 | 9ee6e8bb | pbrook | #ifdef NVIC
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24 | 9ee6e8bb | pbrook | static const uint8_t gic_id[] = |
25 | 9ee6e8bb | pbrook | { 0x00, 0xb0, 0x1b, 0x00, 0x0d, 0xe0, 0x05, 0xb1 }; |
26 | 9ee6e8bb | pbrook | /* The NVIC has 16 internal vectors. However these are not exposed
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27 | 9ee6e8bb | pbrook | through the normal GIC interface. */
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28 | 9ee6e8bb | pbrook | #define GIC_BASE_IRQ 32 |
29 | 9ee6e8bb | pbrook | #else
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30 | e69954b9 | pbrook | static const uint8_t gic_id[] = |
31 | e69954b9 | pbrook | { 0x90, 0x13, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 }; |
32 | 9ee6e8bb | pbrook | #define GIC_BASE_IRQ 0 |
33 | 9ee6e8bb | pbrook | #endif
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34 | e69954b9 | pbrook | |
35 | fe7e8758 | Paul Brook | #define FROM_SYSBUSGIC(type, dev) \
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36 | fe7e8758 | Paul Brook | DO_UPCAST(type, gic, FROM_SYSBUS(gic_state, dev)) |
37 | fe7e8758 | Paul Brook | |
38 | e69954b9 | pbrook | typedef struct gic_irq_state |
39 | e69954b9 | pbrook | { |
40 | 9ee6e8bb | pbrook | /* ??? The documentation seems to imply the enable bits are global, even
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41 | 9ee6e8bb | pbrook | for per-cpu interrupts. This seems strange. */
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42 | e69954b9 | pbrook | unsigned enabled:1; |
43 | 9ee6e8bb | pbrook | unsigned pending:NCPU;
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44 | 9ee6e8bb | pbrook | unsigned active:NCPU;
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45 | a45db6c6 | aurel32 | unsigned level:NCPU;
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46 | 9ee6e8bb | pbrook | unsigned model:1; /* 0 = N:N, 1 = 1:N */ |
47 | e69954b9 | pbrook | unsigned trigger:1; /* nonzero = edge triggered. */ |
48 | e69954b9 | pbrook | } gic_irq_state; |
49 | e69954b9 | pbrook | |
50 | 9ee6e8bb | pbrook | #define ALL_CPU_MASK ((1 << NCPU) - 1) |
51 | 9ee6e8bb | pbrook | |
52 | e69954b9 | pbrook | #define GIC_SET_ENABLED(irq) s->irq_state[irq].enabled = 1 |
53 | e69954b9 | pbrook | #define GIC_CLEAR_ENABLED(irq) s->irq_state[irq].enabled = 0 |
54 | e69954b9 | pbrook | #define GIC_TEST_ENABLED(irq) s->irq_state[irq].enabled
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55 | 9ee6e8bb | pbrook | #define GIC_SET_PENDING(irq, cm) s->irq_state[irq].pending |= (cm)
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56 | 9ee6e8bb | pbrook | #define GIC_CLEAR_PENDING(irq, cm) s->irq_state[irq].pending &= ~(cm)
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57 | 9ee6e8bb | pbrook | #define GIC_TEST_PENDING(irq, cm) ((s->irq_state[irq].pending & (cm)) != 0) |
58 | 9ee6e8bb | pbrook | #define GIC_SET_ACTIVE(irq, cm) s->irq_state[irq].active |= (cm)
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59 | 9ee6e8bb | pbrook | #define GIC_CLEAR_ACTIVE(irq, cm) s->irq_state[irq].active &= ~(cm)
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60 | 9ee6e8bb | pbrook | #define GIC_TEST_ACTIVE(irq, cm) ((s->irq_state[irq].active & (cm)) != 0) |
61 | e69954b9 | pbrook | #define GIC_SET_MODEL(irq) s->irq_state[irq].model = 1 |
62 | e69954b9 | pbrook | #define GIC_CLEAR_MODEL(irq) s->irq_state[irq].model = 0 |
63 | e69954b9 | pbrook | #define GIC_TEST_MODEL(irq) s->irq_state[irq].model
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64 | 9ee6e8bb | pbrook | #define GIC_SET_LEVEL(irq, cm) s->irq_state[irq].level = (cm)
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65 | 9ee6e8bb | pbrook | #define GIC_CLEAR_LEVEL(irq, cm) s->irq_state[irq].level &= ~(cm)
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66 | 57d69a91 | balrog | #define GIC_TEST_LEVEL(irq, cm) ((s->irq_state[irq].level & (cm)) != 0) |
67 | e69954b9 | pbrook | #define GIC_SET_TRIGGER(irq) s->irq_state[irq].trigger = 1 |
68 | e69954b9 | pbrook | #define GIC_CLEAR_TRIGGER(irq) s->irq_state[irq].trigger = 0 |
69 | e69954b9 | pbrook | #define GIC_TEST_TRIGGER(irq) s->irq_state[irq].trigger
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70 | 9ee6e8bb | pbrook | #define GIC_GET_PRIORITY(irq, cpu) \
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71 | 9ee6e8bb | pbrook | (((irq) < 32) ? s->priority1[irq][cpu] : s->priority2[(irq) - 32]) |
72 | 9ee6e8bb | pbrook | #ifdef NVIC
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73 | 9ee6e8bb | pbrook | #define GIC_TARGET(irq) 1 |
74 | 9ee6e8bb | pbrook | #else
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75 | 9ee6e8bb | pbrook | #define GIC_TARGET(irq) s->irq_target[irq]
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76 | 9ee6e8bb | pbrook | #endif
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77 | e69954b9 | pbrook | |
78 | e69954b9 | pbrook | typedef struct gic_state |
79 | e69954b9 | pbrook | { |
80 | fe7e8758 | Paul Brook | SysBusDevice busdev; |
81 | 9ee6e8bb | pbrook | qemu_irq parent_irq[NCPU]; |
82 | e69954b9 | pbrook | int enabled;
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83 | 9ee6e8bb | pbrook | int cpu_enabled[NCPU];
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84 | e69954b9 | pbrook | |
85 | e69954b9 | pbrook | gic_irq_state irq_state[GIC_NIRQ]; |
86 | 9ee6e8bb | pbrook | #ifndef NVIC
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87 | e69954b9 | pbrook | int irq_target[GIC_NIRQ];
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88 | 9ee6e8bb | pbrook | #endif
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89 | 9ee6e8bb | pbrook | int priority1[32][NCPU]; |
90 | 9ee6e8bb | pbrook | int priority2[GIC_NIRQ - 32]; |
91 | 9ee6e8bb | pbrook | int last_active[GIC_NIRQ][NCPU];
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92 | 9ee6e8bb | pbrook | |
93 | 9ee6e8bb | pbrook | int priority_mask[NCPU];
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94 | 9ee6e8bb | pbrook | int running_irq[NCPU];
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95 | 9ee6e8bb | pbrook | int running_priority[NCPU];
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96 | 9ee6e8bb | pbrook | int current_pending[NCPU];
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97 | 9ee6e8bb | pbrook | |
98 | fe7e8758 | Paul Brook | int iomemtype;
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99 | e69954b9 | pbrook | } gic_state; |
100 | e69954b9 | pbrook | |
101 | e69954b9 | pbrook | /* TODO: Many places that call this routine could be optimized. */
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102 | e69954b9 | pbrook | /* Update interrupt status after enabled or pending bits have been changed. */
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103 | e69954b9 | pbrook | static void gic_update(gic_state *s) |
104 | e69954b9 | pbrook | { |
105 | e69954b9 | pbrook | int best_irq;
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106 | e69954b9 | pbrook | int best_prio;
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107 | e69954b9 | pbrook | int irq;
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108 | 9ee6e8bb | pbrook | int level;
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109 | 9ee6e8bb | pbrook | int cpu;
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110 | 9ee6e8bb | pbrook | int cm;
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111 | 9ee6e8bb | pbrook | |
112 | 9ee6e8bb | pbrook | for (cpu = 0; cpu < NCPU; cpu++) { |
113 | 9ee6e8bb | pbrook | cm = 1 << cpu;
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114 | 9ee6e8bb | pbrook | s->current_pending[cpu] = 1023;
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115 | 9ee6e8bb | pbrook | if (!s->enabled || !s->cpu_enabled[cpu]) {
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116 | 9ee6e8bb | pbrook | qemu_irq_lower(s->parent_irq[cpu]); |
117 | 9ee6e8bb | pbrook | return;
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118 | 9ee6e8bb | pbrook | } |
119 | 9ee6e8bb | pbrook | best_prio = 0x100;
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120 | 9ee6e8bb | pbrook | best_irq = 1023;
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121 | 9ee6e8bb | pbrook | for (irq = 0; irq < GIC_NIRQ; irq++) { |
122 | 9ee6e8bb | pbrook | if (GIC_TEST_ENABLED(irq) && GIC_TEST_PENDING(irq, cm)) {
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123 | 9ee6e8bb | pbrook | if (GIC_GET_PRIORITY(irq, cpu) < best_prio) {
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124 | 9ee6e8bb | pbrook | best_prio = GIC_GET_PRIORITY(irq, cpu); |
125 | 9ee6e8bb | pbrook | best_irq = irq; |
126 | 9ee6e8bb | pbrook | } |
127 | e69954b9 | pbrook | } |
128 | e69954b9 | pbrook | } |
129 | 9ee6e8bb | pbrook | level = 0;
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130 | 9ee6e8bb | pbrook | if (best_prio <= s->priority_mask[cpu]) {
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131 | 9ee6e8bb | pbrook | s->current_pending[cpu] = best_irq; |
132 | 9ee6e8bb | pbrook | if (best_prio < s->running_priority[cpu]) {
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133 | 9ee6e8bb | pbrook | DPRINTF("Raised pending IRQ %d\n", best_irq);
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134 | 9ee6e8bb | pbrook | level = 1;
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135 | 9ee6e8bb | pbrook | } |
136 | e69954b9 | pbrook | } |
137 | 9ee6e8bb | pbrook | qemu_set_irq(s->parent_irq[cpu], level); |
138 | e69954b9 | pbrook | } |
139 | e69954b9 | pbrook | } |
140 | e69954b9 | pbrook | |
141 | 9ee6e8bb | pbrook | static void __attribute__((unused)) |
142 | 9ee6e8bb | pbrook | gic_set_pending_private(gic_state *s, int cpu, int irq) |
143 | 9ee6e8bb | pbrook | { |
144 | 9ee6e8bb | pbrook | int cm = 1 << cpu; |
145 | 9ee6e8bb | pbrook | |
146 | 9ee6e8bb | pbrook | if (GIC_TEST_PENDING(irq, cm))
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147 | 9ee6e8bb | pbrook | return;
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148 | 9ee6e8bb | pbrook | |
149 | 9ee6e8bb | pbrook | DPRINTF("Set %d pending cpu %d\n", irq, cpu);
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150 | 9ee6e8bb | pbrook | GIC_SET_PENDING(irq, cm); |
151 | 9ee6e8bb | pbrook | gic_update(s); |
152 | 9ee6e8bb | pbrook | } |
153 | 9ee6e8bb | pbrook | |
154 | 9ee6e8bb | pbrook | /* Process a change in an external IRQ input. */
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155 | e69954b9 | pbrook | static void gic_set_irq(void *opaque, int irq, int level) |
156 | e69954b9 | pbrook | { |
157 | e69954b9 | pbrook | gic_state *s = (gic_state *)opaque; |
158 | e69954b9 | pbrook | /* The first external input line is internal interrupt 32. */
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159 | e69954b9 | pbrook | irq += 32;
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160 | 9ee6e8bb | pbrook | if (level == GIC_TEST_LEVEL(irq, ALL_CPU_MASK))
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161 | e69954b9 | pbrook | return;
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162 | e69954b9 | pbrook | |
163 | e69954b9 | pbrook | if (level) {
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164 | 9ee6e8bb | pbrook | GIC_SET_LEVEL(irq, ALL_CPU_MASK); |
165 | e69954b9 | pbrook | if (GIC_TEST_TRIGGER(irq) || GIC_TEST_ENABLED(irq)) {
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166 | 9ee6e8bb | pbrook | DPRINTF("Set %d pending mask %x\n", irq, GIC_TARGET(irq));
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167 | 9ee6e8bb | pbrook | GIC_SET_PENDING(irq, GIC_TARGET(irq)); |
168 | e69954b9 | pbrook | } |
169 | e69954b9 | pbrook | } else {
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170 | 9ee6e8bb | pbrook | GIC_CLEAR_LEVEL(irq, ALL_CPU_MASK); |
171 | e69954b9 | pbrook | } |
172 | e69954b9 | pbrook | gic_update(s); |
173 | e69954b9 | pbrook | } |
174 | e69954b9 | pbrook | |
175 | 9ee6e8bb | pbrook | static void gic_set_running_irq(gic_state *s, int cpu, int irq) |
176 | e69954b9 | pbrook | { |
177 | 9ee6e8bb | pbrook | s->running_irq[cpu] = irq; |
178 | 9ee6e8bb | pbrook | if (irq == 1023) { |
179 | 9ee6e8bb | pbrook | s->running_priority[cpu] = 0x100;
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180 | 9ee6e8bb | pbrook | } else {
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181 | 9ee6e8bb | pbrook | s->running_priority[cpu] = GIC_GET_PRIORITY(irq, cpu); |
182 | 9ee6e8bb | pbrook | } |
183 | e69954b9 | pbrook | gic_update(s); |
184 | e69954b9 | pbrook | } |
185 | e69954b9 | pbrook | |
186 | 9ee6e8bb | pbrook | static uint32_t gic_acknowledge_irq(gic_state *s, int cpu) |
187 | e69954b9 | pbrook | { |
188 | e69954b9 | pbrook | int new_irq;
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189 | 9ee6e8bb | pbrook | int cm = 1 << cpu; |
190 | 9ee6e8bb | pbrook | new_irq = s->current_pending[cpu]; |
191 | 9ee6e8bb | pbrook | if (new_irq == 1023 |
192 | 9ee6e8bb | pbrook | || GIC_GET_PRIORITY(new_irq, cpu) >= s->running_priority[cpu]) { |
193 | e69954b9 | pbrook | DPRINTF("ACK no pending IRQ\n");
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194 | e69954b9 | pbrook | return 1023; |
195 | e69954b9 | pbrook | } |
196 | 9ee6e8bb | pbrook | s->last_active[new_irq][cpu] = s->running_irq[cpu]; |
197 | 9ee6e8bb | pbrook | /* Clear pending flags for both level and edge triggered interrupts.
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198 | 9ee6e8bb | pbrook | Level triggered IRQs will be reasserted once they become inactive. */
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199 | 9ee6e8bb | pbrook | GIC_CLEAR_PENDING(new_irq, GIC_TEST_MODEL(new_irq) ? ALL_CPU_MASK : cm); |
200 | 9ee6e8bb | pbrook | gic_set_running_irq(s, cpu, new_irq); |
201 | e69954b9 | pbrook | DPRINTF("ACK %d\n", new_irq);
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202 | e69954b9 | pbrook | return new_irq;
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203 | e69954b9 | pbrook | } |
204 | e69954b9 | pbrook | |
205 | 9ee6e8bb | pbrook | static void gic_complete_irq(gic_state * s, int cpu, int irq) |
206 | e69954b9 | pbrook | { |
207 | e69954b9 | pbrook | int update = 0; |
208 | 9ee6e8bb | pbrook | int cm = 1 << cpu; |
209 | df628ff1 | pbrook | DPRINTF("EOI %d\n", irq);
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210 | 9ee6e8bb | pbrook | if (s->running_irq[cpu] == 1023) |
211 | e69954b9 | pbrook | return; /* No active IRQ. */ |
212 | e69954b9 | pbrook | if (irq != 1023) { |
213 | e69954b9 | pbrook | /* Mark level triggered interrupts as pending if they are still
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214 | e69954b9 | pbrook | raised. */
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215 | e69954b9 | pbrook | if (!GIC_TEST_TRIGGER(irq) && GIC_TEST_ENABLED(irq)
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216 | 9ee6e8bb | pbrook | && GIC_TEST_LEVEL(irq, cm) && (GIC_TARGET(irq) & cm) != 0) {
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217 | 9ee6e8bb | pbrook | DPRINTF("Set %d pending mask %x\n", irq, cm);
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218 | 9ee6e8bb | pbrook | GIC_SET_PENDING(irq, cm); |
219 | e69954b9 | pbrook | update = 1;
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220 | e69954b9 | pbrook | } |
221 | e69954b9 | pbrook | } |
222 | 9ee6e8bb | pbrook | if (irq != s->running_irq[cpu]) {
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223 | e69954b9 | pbrook | /* Complete an IRQ that is not currently running. */
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224 | 9ee6e8bb | pbrook | int tmp = s->running_irq[cpu];
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225 | 9ee6e8bb | pbrook | while (s->last_active[tmp][cpu] != 1023) { |
226 | 9ee6e8bb | pbrook | if (s->last_active[tmp][cpu] == irq) {
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227 | 9ee6e8bb | pbrook | s->last_active[tmp][cpu] = s->last_active[irq][cpu]; |
228 | e69954b9 | pbrook | break;
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229 | e69954b9 | pbrook | } |
230 | 9ee6e8bb | pbrook | tmp = s->last_active[tmp][cpu]; |
231 | e69954b9 | pbrook | } |
232 | e69954b9 | pbrook | if (update) {
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233 | e69954b9 | pbrook | gic_update(s); |
234 | e69954b9 | pbrook | } |
235 | e69954b9 | pbrook | } else {
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236 | e69954b9 | pbrook | /* Complete the current running IRQ. */
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237 | 9ee6e8bb | pbrook | gic_set_running_irq(s, cpu, s->last_active[s->running_irq[cpu]][cpu]); |
238 | e69954b9 | pbrook | } |
239 | e69954b9 | pbrook | } |
240 | e69954b9 | pbrook | |
241 | e69954b9 | pbrook | static uint32_t gic_dist_readb(void *opaque, target_phys_addr_t offset) |
242 | e69954b9 | pbrook | { |
243 | e69954b9 | pbrook | gic_state *s = (gic_state *)opaque; |
244 | e69954b9 | pbrook | uint32_t res; |
245 | e69954b9 | pbrook | int irq;
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246 | e69954b9 | pbrook | int i;
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247 | 9ee6e8bb | pbrook | int cpu;
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248 | 9ee6e8bb | pbrook | int cm;
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249 | 9ee6e8bb | pbrook | int mask;
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250 | e69954b9 | pbrook | |
251 | 9ee6e8bb | pbrook | cpu = gic_get_current_cpu(); |
252 | 9ee6e8bb | pbrook | cm = 1 << cpu;
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253 | e69954b9 | pbrook | if (offset < 0x100) { |
254 | 9ee6e8bb | pbrook | #ifndef NVIC
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255 | e69954b9 | pbrook | if (offset == 0) |
256 | e69954b9 | pbrook | return s->enabled;
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257 | e69954b9 | pbrook | if (offset == 4) |
258 | 9ee6e8bb | pbrook | return ((GIC_NIRQ / 32) - 1) | ((NCPU - 1) << 5); |
259 | e69954b9 | pbrook | if (offset < 0x08) |
260 | e69954b9 | pbrook | return 0; |
261 | 9ee6e8bb | pbrook | #endif
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262 | e69954b9 | pbrook | goto bad_reg;
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263 | e69954b9 | pbrook | } else if (offset < 0x200) { |
264 | e69954b9 | pbrook | /* Interrupt Set/Clear Enable. */
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265 | e69954b9 | pbrook | if (offset < 0x180) |
266 | e69954b9 | pbrook | irq = (offset - 0x100) * 8; |
267 | e69954b9 | pbrook | else
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268 | e69954b9 | pbrook | irq = (offset - 0x180) * 8; |
269 | 9ee6e8bb | pbrook | irq += GIC_BASE_IRQ; |
270 | e69954b9 | pbrook | if (irq >= GIC_NIRQ)
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271 | e69954b9 | pbrook | goto bad_reg;
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272 | e69954b9 | pbrook | res = 0;
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273 | e69954b9 | pbrook | for (i = 0; i < 8; i++) { |
274 | e69954b9 | pbrook | if (GIC_TEST_ENABLED(irq + i)) {
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275 | e69954b9 | pbrook | res |= (1 << i);
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276 | e69954b9 | pbrook | } |
277 | e69954b9 | pbrook | } |
278 | e69954b9 | pbrook | } else if (offset < 0x300) { |
279 | e69954b9 | pbrook | /* Interrupt Set/Clear Pending. */
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280 | e69954b9 | pbrook | if (offset < 0x280) |
281 | e69954b9 | pbrook | irq = (offset - 0x200) * 8; |
282 | e69954b9 | pbrook | else
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283 | e69954b9 | pbrook | irq = (offset - 0x280) * 8; |
284 | 9ee6e8bb | pbrook | irq += GIC_BASE_IRQ; |
285 | e69954b9 | pbrook | if (irq >= GIC_NIRQ)
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286 | e69954b9 | pbrook | goto bad_reg;
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287 | e69954b9 | pbrook | res = 0;
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288 | 9ee6e8bb | pbrook | mask = (irq < 32) ? cm : ALL_CPU_MASK;
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289 | e69954b9 | pbrook | for (i = 0; i < 8; i++) { |
290 | 9ee6e8bb | pbrook | if (GIC_TEST_PENDING(irq + i, mask)) {
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291 | e69954b9 | pbrook | res |= (1 << i);
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292 | e69954b9 | pbrook | } |
293 | e69954b9 | pbrook | } |
294 | e69954b9 | pbrook | } else if (offset < 0x400) { |
295 | e69954b9 | pbrook | /* Interrupt Active. */
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296 | 9ee6e8bb | pbrook | irq = (offset - 0x300) * 8 + GIC_BASE_IRQ; |
297 | e69954b9 | pbrook | if (irq >= GIC_NIRQ)
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298 | e69954b9 | pbrook | goto bad_reg;
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299 | e69954b9 | pbrook | res = 0;
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300 | 9ee6e8bb | pbrook | mask = (irq < 32) ? cm : ALL_CPU_MASK;
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301 | e69954b9 | pbrook | for (i = 0; i < 8; i++) { |
302 | 9ee6e8bb | pbrook | if (GIC_TEST_ACTIVE(irq + i, mask)) {
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303 | e69954b9 | pbrook | res |= (1 << i);
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304 | e69954b9 | pbrook | } |
305 | e69954b9 | pbrook | } |
306 | e69954b9 | pbrook | } else if (offset < 0x800) { |
307 | e69954b9 | pbrook | /* Interrupt Priority. */
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308 | 9ee6e8bb | pbrook | irq = (offset - 0x400) + GIC_BASE_IRQ;
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309 | e69954b9 | pbrook | if (irq >= GIC_NIRQ)
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310 | e69954b9 | pbrook | goto bad_reg;
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311 | 9ee6e8bb | pbrook | res = GIC_GET_PRIORITY(irq, cpu); |
312 | 9ee6e8bb | pbrook | #ifndef NVIC
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313 | e69954b9 | pbrook | } else if (offset < 0xc00) { |
314 | e69954b9 | pbrook | /* Interrupt CPU Target. */
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315 | 9ee6e8bb | pbrook | irq = (offset - 0x800) + GIC_BASE_IRQ;
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316 | e69954b9 | pbrook | if (irq >= GIC_NIRQ)
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317 | e69954b9 | pbrook | goto bad_reg;
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318 | 9ee6e8bb | pbrook | if (irq >= 29 && irq <= 31) { |
319 | 9ee6e8bb | pbrook | res = cm; |
320 | 9ee6e8bb | pbrook | } else {
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321 | 9ee6e8bb | pbrook | res = GIC_TARGET(irq); |
322 | 9ee6e8bb | pbrook | } |
323 | e69954b9 | pbrook | } else if (offset < 0xf00) { |
324 | e69954b9 | pbrook | /* Interrupt Configuration. */
|
325 | 9ee6e8bb | pbrook | irq = (offset - 0xc00) * 2 + GIC_BASE_IRQ; |
326 | e69954b9 | pbrook | if (irq >= GIC_NIRQ)
|
327 | e69954b9 | pbrook | goto bad_reg;
|
328 | e69954b9 | pbrook | res = 0;
|
329 | e69954b9 | pbrook | for (i = 0; i < 4; i++) { |
330 | e69954b9 | pbrook | if (GIC_TEST_MODEL(irq + i))
|
331 | e69954b9 | pbrook | res |= (1 << (i * 2)); |
332 | e69954b9 | pbrook | if (GIC_TEST_TRIGGER(irq + i))
|
333 | e69954b9 | pbrook | res |= (2 << (i * 2)); |
334 | e69954b9 | pbrook | } |
335 | 9ee6e8bb | pbrook | #endif
|
336 | e69954b9 | pbrook | } else if (offset < 0xfe0) { |
337 | e69954b9 | pbrook | goto bad_reg;
|
338 | e69954b9 | pbrook | } else /* offset >= 0xfe0 */ { |
339 | e69954b9 | pbrook | if (offset & 3) { |
340 | e69954b9 | pbrook | res = 0;
|
341 | e69954b9 | pbrook | } else {
|
342 | e69954b9 | pbrook | res = gic_id[(offset - 0xfe0) >> 2]; |
343 | e69954b9 | pbrook | } |
344 | e69954b9 | pbrook | } |
345 | e69954b9 | pbrook | return res;
|
346 | e69954b9 | pbrook | bad_reg:
|
347 | 2ac71179 | Paul Brook | hw_error("gic_dist_readb: Bad offset %x\n", (int)offset); |
348 | e69954b9 | pbrook | return 0; |
349 | e69954b9 | pbrook | } |
350 | e69954b9 | pbrook | |
351 | e69954b9 | pbrook | static uint32_t gic_dist_readw(void *opaque, target_phys_addr_t offset) |
352 | e69954b9 | pbrook | { |
353 | e69954b9 | pbrook | uint32_t val; |
354 | e69954b9 | pbrook | val = gic_dist_readb(opaque, offset); |
355 | e69954b9 | pbrook | val |= gic_dist_readb(opaque, offset + 1) << 8; |
356 | e69954b9 | pbrook | return val;
|
357 | e69954b9 | pbrook | } |
358 | e69954b9 | pbrook | |
359 | e69954b9 | pbrook | static uint32_t gic_dist_readl(void *opaque, target_phys_addr_t offset) |
360 | e69954b9 | pbrook | { |
361 | e69954b9 | pbrook | uint32_t val; |
362 | 9ee6e8bb | pbrook | #ifdef NVIC
|
363 | 9ee6e8bb | pbrook | gic_state *s = (gic_state *)opaque; |
364 | 9ee6e8bb | pbrook | uint32_t addr; |
365 | 8da3ff18 | pbrook | addr = offset; |
366 | 9ee6e8bb | pbrook | if (addr < 0x100 || addr > 0xd00) |
367 | fe7e8758 | Paul Brook | return nvic_readl(s, addr);
|
368 | 9ee6e8bb | pbrook | #endif
|
369 | e69954b9 | pbrook | val = gic_dist_readw(opaque, offset); |
370 | e69954b9 | pbrook | val |= gic_dist_readw(opaque, offset + 2) << 16; |
371 | e69954b9 | pbrook | return val;
|
372 | e69954b9 | pbrook | } |
373 | e69954b9 | pbrook | |
374 | e69954b9 | pbrook | static void gic_dist_writeb(void *opaque, target_phys_addr_t offset, |
375 | e69954b9 | pbrook | uint32_t value) |
376 | e69954b9 | pbrook | { |
377 | e69954b9 | pbrook | gic_state *s = (gic_state *)opaque; |
378 | e69954b9 | pbrook | int irq;
|
379 | e69954b9 | pbrook | int i;
|
380 | 9ee6e8bb | pbrook | int cpu;
|
381 | e69954b9 | pbrook | |
382 | 9ee6e8bb | pbrook | cpu = gic_get_current_cpu(); |
383 | e69954b9 | pbrook | if (offset < 0x100) { |
384 | 9ee6e8bb | pbrook | #ifdef NVIC
|
385 | 9ee6e8bb | pbrook | goto bad_reg;
|
386 | 9ee6e8bb | pbrook | #else
|
387 | e69954b9 | pbrook | if (offset == 0) { |
388 | e69954b9 | pbrook | s->enabled = (value & 1);
|
389 | e69954b9 | pbrook | DPRINTF("Distribution %sabled\n", s->enabled ? "En" : "Dis"); |
390 | e69954b9 | pbrook | } else if (offset < 4) { |
391 | e69954b9 | pbrook | /* ignored. */
|
392 | e69954b9 | pbrook | } else {
|
393 | e69954b9 | pbrook | goto bad_reg;
|
394 | e69954b9 | pbrook | } |
395 | 9ee6e8bb | pbrook | #endif
|
396 | e69954b9 | pbrook | } else if (offset < 0x180) { |
397 | e69954b9 | pbrook | /* Interrupt Set Enable. */
|
398 | 9ee6e8bb | pbrook | irq = (offset - 0x100) * 8 + GIC_BASE_IRQ; |
399 | e69954b9 | pbrook | if (irq >= GIC_NIRQ)
|
400 | e69954b9 | pbrook | goto bad_reg;
|
401 | 9ee6e8bb | pbrook | if (irq < 16) |
402 | 9ee6e8bb | pbrook | value = 0xff;
|
403 | e69954b9 | pbrook | for (i = 0; i < 8; i++) { |
404 | e69954b9 | pbrook | if (value & (1 << i)) { |
405 | 9ee6e8bb | pbrook | int mask = (irq < 32) ? (1 << cpu) : GIC_TARGET(irq); |
406 | e69954b9 | pbrook | if (!GIC_TEST_ENABLED(irq + i))
|
407 | e69954b9 | pbrook | DPRINTF("Enabled IRQ %d\n", irq + i);
|
408 | e69954b9 | pbrook | GIC_SET_ENABLED(irq + i); |
409 | e69954b9 | pbrook | /* If a raised level triggered IRQ enabled then mark
|
410 | e69954b9 | pbrook | is as pending. */
|
411 | 9ee6e8bb | pbrook | if (GIC_TEST_LEVEL(irq + i, mask)
|
412 | 9ee6e8bb | pbrook | && !GIC_TEST_TRIGGER(irq + i)) { |
413 | 9ee6e8bb | pbrook | DPRINTF("Set %d pending mask %x\n", irq + i, mask);
|
414 | 9ee6e8bb | pbrook | GIC_SET_PENDING(irq + i, mask); |
415 | 9ee6e8bb | pbrook | } |
416 | e69954b9 | pbrook | } |
417 | e69954b9 | pbrook | } |
418 | e69954b9 | pbrook | } else if (offset < 0x200) { |
419 | e69954b9 | pbrook | /* Interrupt Clear Enable. */
|
420 | 9ee6e8bb | pbrook | irq = (offset - 0x180) * 8 + GIC_BASE_IRQ; |
421 | e69954b9 | pbrook | if (irq >= GIC_NIRQ)
|
422 | e69954b9 | pbrook | goto bad_reg;
|
423 | 9ee6e8bb | pbrook | if (irq < 16) |
424 | 9ee6e8bb | pbrook | value = 0;
|
425 | e69954b9 | pbrook | for (i = 0; i < 8; i++) { |
426 | e69954b9 | pbrook | if (value & (1 << i)) { |
427 | e69954b9 | pbrook | if (GIC_TEST_ENABLED(irq + i))
|
428 | e69954b9 | pbrook | DPRINTF("Disabled IRQ %d\n", irq + i);
|
429 | e69954b9 | pbrook | GIC_CLEAR_ENABLED(irq + i); |
430 | e69954b9 | pbrook | } |
431 | e69954b9 | pbrook | } |
432 | e69954b9 | pbrook | } else if (offset < 0x280) { |
433 | e69954b9 | pbrook | /* Interrupt Set Pending. */
|
434 | 9ee6e8bb | pbrook | irq = (offset - 0x200) * 8 + GIC_BASE_IRQ; |
435 | e69954b9 | pbrook | if (irq >= GIC_NIRQ)
|
436 | e69954b9 | pbrook | goto bad_reg;
|
437 | 9ee6e8bb | pbrook | if (irq < 16) |
438 | 9ee6e8bb | pbrook | irq = 0;
|
439 | 9ee6e8bb | pbrook | |
440 | e69954b9 | pbrook | for (i = 0; i < 8; i++) { |
441 | e69954b9 | pbrook | if (value & (1 << i)) { |
442 | 9ee6e8bb | pbrook | GIC_SET_PENDING(irq + i, GIC_TARGET(irq)); |
443 | e69954b9 | pbrook | } |
444 | e69954b9 | pbrook | } |
445 | e69954b9 | pbrook | } else if (offset < 0x300) { |
446 | e69954b9 | pbrook | /* Interrupt Clear Pending. */
|
447 | 9ee6e8bb | pbrook | irq = (offset - 0x280) * 8 + GIC_BASE_IRQ; |
448 | e69954b9 | pbrook | if (irq >= GIC_NIRQ)
|
449 | e69954b9 | pbrook | goto bad_reg;
|
450 | e69954b9 | pbrook | for (i = 0; i < 8; i++) { |
451 | 9ee6e8bb | pbrook | /* ??? This currently clears the pending bit for all CPUs, even
|
452 | 9ee6e8bb | pbrook | for per-CPU interrupts. It's unclear whether this is the
|
453 | 9ee6e8bb | pbrook | corect behavior. */
|
454 | e69954b9 | pbrook | if (value & (1 << i)) { |
455 | 9ee6e8bb | pbrook | GIC_CLEAR_PENDING(irq + i, ALL_CPU_MASK); |
456 | e69954b9 | pbrook | } |
457 | e69954b9 | pbrook | } |
458 | e69954b9 | pbrook | } else if (offset < 0x400) { |
459 | e69954b9 | pbrook | /* Interrupt Active. */
|
460 | e69954b9 | pbrook | goto bad_reg;
|
461 | e69954b9 | pbrook | } else if (offset < 0x800) { |
462 | e69954b9 | pbrook | /* Interrupt Priority. */
|
463 | 9ee6e8bb | pbrook | irq = (offset - 0x400) + GIC_BASE_IRQ;
|
464 | e69954b9 | pbrook | if (irq >= GIC_NIRQ)
|
465 | e69954b9 | pbrook | goto bad_reg;
|
466 | 9ee6e8bb | pbrook | if (irq < 32) { |
467 | 9ee6e8bb | pbrook | s->priority1[irq][cpu] = value; |
468 | 9ee6e8bb | pbrook | } else {
|
469 | 9ee6e8bb | pbrook | s->priority2[irq - 32] = value;
|
470 | 9ee6e8bb | pbrook | } |
471 | 9ee6e8bb | pbrook | #ifndef NVIC
|
472 | e69954b9 | pbrook | } else if (offset < 0xc00) { |
473 | e69954b9 | pbrook | /* Interrupt CPU Target. */
|
474 | 9ee6e8bb | pbrook | irq = (offset - 0x800) + GIC_BASE_IRQ;
|
475 | e69954b9 | pbrook | if (irq >= GIC_NIRQ)
|
476 | e69954b9 | pbrook | goto bad_reg;
|
477 | 9ee6e8bb | pbrook | if (irq < 29) |
478 | 9ee6e8bb | pbrook | value = 0;
|
479 | 9ee6e8bb | pbrook | else if (irq < 32) |
480 | 9ee6e8bb | pbrook | value = ALL_CPU_MASK; |
481 | 9ee6e8bb | pbrook | s->irq_target[irq] = value & ALL_CPU_MASK; |
482 | e69954b9 | pbrook | } else if (offset < 0xf00) { |
483 | e69954b9 | pbrook | /* Interrupt Configuration. */
|
484 | 9ee6e8bb | pbrook | irq = (offset - 0xc00) * 4 + GIC_BASE_IRQ; |
485 | e69954b9 | pbrook | if (irq >= GIC_NIRQ)
|
486 | e69954b9 | pbrook | goto bad_reg;
|
487 | 9ee6e8bb | pbrook | if (irq < 32) |
488 | 9ee6e8bb | pbrook | value |= 0xaa;
|
489 | e69954b9 | pbrook | for (i = 0; i < 4; i++) { |
490 | e69954b9 | pbrook | if (value & (1 << (i * 2))) { |
491 | e69954b9 | pbrook | GIC_SET_MODEL(irq + i); |
492 | e69954b9 | pbrook | } else {
|
493 | e69954b9 | pbrook | GIC_CLEAR_MODEL(irq + i); |
494 | e69954b9 | pbrook | } |
495 | e69954b9 | pbrook | if (value & (2 << (i * 2))) { |
496 | e69954b9 | pbrook | GIC_SET_TRIGGER(irq + i); |
497 | e69954b9 | pbrook | } else {
|
498 | e69954b9 | pbrook | GIC_CLEAR_TRIGGER(irq + i); |
499 | e69954b9 | pbrook | } |
500 | e69954b9 | pbrook | } |
501 | 9ee6e8bb | pbrook | #endif
|
502 | e69954b9 | pbrook | } else {
|
503 | 9ee6e8bb | pbrook | /* 0xf00 is only handled for 32-bit writes. */
|
504 | e69954b9 | pbrook | goto bad_reg;
|
505 | e69954b9 | pbrook | } |
506 | e69954b9 | pbrook | gic_update(s); |
507 | e69954b9 | pbrook | return;
|
508 | e69954b9 | pbrook | bad_reg:
|
509 | 2ac71179 | Paul Brook | hw_error("gic_dist_writeb: Bad offset %x\n", (int)offset); |
510 | e69954b9 | pbrook | } |
511 | e69954b9 | pbrook | |
512 | e69954b9 | pbrook | static void gic_dist_writew(void *opaque, target_phys_addr_t offset, |
513 | e69954b9 | pbrook | uint32_t value) |
514 | e69954b9 | pbrook | { |
515 | e69954b9 | pbrook | gic_dist_writeb(opaque, offset, value & 0xff);
|
516 | e69954b9 | pbrook | gic_dist_writeb(opaque, offset + 1, value >> 8); |
517 | e69954b9 | pbrook | } |
518 | e69954b9 | pbrook | |
519 | e69954b9 | pbrook | static void gic_dist_writel(void *opaque, target_phys_addr_t offset, |
520 | e69954b9 | pbrook | uint32_t value) |
521 | e69954b9 | pbrook | { |
522 | 9ee6e8bb | pbrook | gic_state *s = (gic_state *)opaque; |
523 | 9ee6e8bb | pbrook | #ifdef NVIC
|
524 | 9ee6e8bb | pbrook | uint32_t addr; |
525 | 8da3ff18 | pbrook | addr = offset; |
526 | 9ee6e8bb | pbrook | if (addr < 0x100 || (addr > 0xd00 && addr != 0xf00)) { |
527 | fe7e8758 | Paul Brook | nvic_writel(s, addr, value); |
528 | 9ee6e8bb | pbrook | return;
|
529 | 9ee6e8bb | pbrook | } |
530 | 9ee6e8bb | pbrook | #endif
|
531 | 8da3ff18 | pbrook | if (offset == 0xf00) { |
532 | 9ee6e8bb | pbrook | int cpu;
|
533 | 9ee6e8bb | pbrook | int irq;
|
534 | 9ee6e8bb | pbrook | int mask;
|
535 | 9ee6e8bb | pbrook | |
536 | 9ee6e8bb | pbrook | cpu = gic_get_current_cpu(); |
537 | 9ee6e8bb | pbrook | irq = value & 0x3ff;
|
538 | 9ee6e8bb | pbrook | switch ((value >> 24) & 3) { |
539 | 9ee6e8bb | pbrook | case 0: |
540 | 9ee6e8bb | pbrook | mask = (value >> 16) & ALL_CPU_MASK;
|
541 | 9ee6e8bb | pbrook | break;
|
542 | 9ee6e8bb | pbrook | case 1: |
543 | 9ee6e8bb | pbrook | mask = 1 << cpu;
|
544 | 9ee6e8bb | pbrook | break;
|
545 | 9ee6e8bb | pbrook | case 2: |
546 | 9ee6e8bb | pbrook | mask = ALL_CPU_MASK ^ (1 << cpu);
|
547 | 9ee6e8bb | pbrook | break;
|
548 | 9ee6e8bb | pbrook | default:
|
549 | 9ee6e8bb | pbrook | DPRINTF("Bad Soft Int target filter\n");
|
550 | 9ee6e8bb | pbrook | mask = ALL_CPU_MASK; |
551 | 9ee6e8bb | pbrook | break;
|
552 | 9ee6e8bb | pbrook | } |
553 | 9ee6e8bb | pbrook | GIC_SET_PENDING(irq, mask); |
554 | 9ee6e8bb | pbrook | gic_update(s); |
555 | 9ee6e8bb | pbrook | return;
|
556 | 9ee6e8bb | pbrook | } |
557 | e69954b9 | pbrook | gic_dist_writew(opaque, offset, value & 0xffff);
|
558 | e69954b9 | pbrook | gic_dist_writew(opaque, offset + 2, value >> 16); |
559 | e69954b9 | pbrook | } |
560 | e69954b9 | pbrook | |
561 | e69954b9 | pbrook | static CPUReadMemoryFunc *gic_dist_readfn[] = {
|
562 | e69954b9 | pbrook | gic_dist_readb, |
563 | e69954b9 | pbrook | gic_dist_readw, |
564 | e69954b9 | pbrook | gic_dist_readl |
565 | e69954b9 | pbrook | }; |
566 | e69954b9 | pbrook | |
567 | e69954b9 | pbrook | static CPUWriteMemoryFunc *gic_dist_writefn[] = {
|
568 | e69954b9 | pbrook | gic_dist_writeb, |
569 | e69954b9 | pbrook | gic_dist_writew, |
570 | e69954b9 | pbrook | gic_dist_writel |
571 | e69954b9 | pbrook | }; |
572 | e69954b9 | pbrook | |
573 | 9ee6e8bb | pbrook | #ifndef NVIC
|
574 | 9ee6e8bb | pbrook | static uint32_t gic_cpu_read(gic_state *s, int cpu, int offset) |
575 | e69954b9 | pbrook | { |
576 | e69954b9 | pbrook | switch (offset) {
|
577 | e69954b9 | pbrook | case 0x00: /* Control */ |
578 | 9ee6e8bb | pbrook | return s->cpu_enabled[cpu];
|
579 | e69954b9 | pbrook | case 0x04: /* Priority mask */ |
580 | 9ee6e8bb | pbrook | return s->priority_mask[cpu];
|
581 | e69954b9 | pbrook | case 0x08: /* Binary Point */ |
582 | e69954b9 | pbrook | /* ??? Not implemented. */
|
583 | e69954b9 | pbrook | return 0; |
584 | e69954b9 | pbrook | case 0x0c: /* Acknowledge */ |
585 | 9ee6e8bb | pbrook | return gic_acknowledge_irq(s, cpu);
|
586 | e69954b9 | pbrook | case 0x14: /* Runing Priority */ |
587 | 9ee6e8bb | pbrook | return s->running_priority[cpu];
|
588 | e69954b9 | pbrook | case 0x18: /* Highest Pending Interrupt */ |
589 | 9ee6e8bb | pbrook | return s->current_pending[cpu];
|
590 | e69954b9 | pbrook | default:
|
591 | 2ac71179 | Paul Brook | hw_error("gic_cpu_read: Bad offset %x\n", (int)offset); |
592 | e69954b9 | pbrook | return 0; |
593 | e69954b9 | pbrook | } |
594 | e69954b9 | pbrook | } |
595 | e69954b9 | pbrook | |
596 | 9ee6e8bb | pbrook | static void gic_cpu_write(gic_state *s, int cpu, int offset, uint32_t value) |
597 | e69954b9 | pbrook | { |
598 | e69954b9 | pbrook | switch (offset) {
|
599 | e69954b9 | pbrook | case 0x00: /* Control */ |
600 | 9ee6e8bb | pbrook | s->cpu_enabled[cpu] = (value & 1);
|
601 | e69954b9 | pbrook | DPRINTF("CPU %sabled\n", s->cpu_enabled ? "En" : "Dis"); |
602 | e69954b9 | pbrook | break;
|
603 | e69954b9 | pbrook | case 0x04: /* Priority mask */ |
604 | 9ee6e8bb | pbrook | s->priority_mask[cpu] = (value & 0xff);
|
605 | e69954b9 | pbrook | break;
|
606 | e69954b9 | pbrook | case 0x08: /* Binary Point */ |
607 | e69954b9 | pbrook | /* ??? Not implemented. */
|
608 | e69954b9 | pbrook | break;
|
609 | e69954b9 | pbrook | case 0x10: /* End Of Interrupt */ |
610 | 9ee6e8bb | pbrook | return gic_complete_irq(s, cpu, value & 0x3ff); |
611 | e69954b9 | pbrook | default:
|
612 | 2ac71179 | Paul Brook | hw_error("gic_cpu_write: Bad offset %x\n", (int)offset); |
613 | e69954b9 | pbrook | return;
|
614 | e69954b9 | pbrook | } |
615 | e69954b9 | pbrook | gic_update(s); |
616 | e69954b9 | pbrook | } |
617 | 9ee6e8bb | pbrook | #endif
|
618 | e69954b9 | pbrook | |
619 | e69954b9 | pbrook | static void gic_reset(gic_state *s) |
620 | e69954b9 | pbrook | { |
621 | e69954b9 | pbrook | int i;
|
622 | e69954b9 | pbrook | memset(s->irq_state, 0, GIC_NIRQ * sizeof(gic_irq_state)); |
623 | 9ee6e8bb | pbrook | for (i = 0 ; i < NCPU; i++) { |
624 | 9ee6e8bb | pbrook | s->priority_mask[i] = 0xf0;
|
625 | 9ee6e8bb | pbrook | s->current_pending[i] = 1023;
|
626 | 9ee6e8bb | pbrook | s->running_irq[i] = 1023;
|
627 | 9ee6e8bb | pbrook | s->running_priority[i] = 0x100;
|
628 | 9ee6e8bb | pbrook | #ifdef NVIC
|
629 | 9ee6e8bb | pbrook | /* The NVIC doesn't have per-cpu interfaces, so enable by default. */
|
630 | 9ee6e8bb | pbrook | s->cpu_enabled[i] = 1;
|
631 | 9ee6e8bb | pbrook | #else
|
632 | 9ee6e8bb | pbrook | s->cpu_enabled[i] = 0;
|
633 | 9ee6e8bb | pbrook | #endif
|
634 | 9ee6e8bb | pbrook | } |
635 | e57ec016 | pbrook | for (i = 0; i < 16; i++) { |
636 | e69954b9 | pbrook | GIC_SET_ENABLED(i); |
637 | e69954b9 | pbrook | GIC_SET_TRIGGER(i); |
638 | e69954b9 | pbrook | } |
639 | 9ee6e8bb | pbrook | #ifdef NVIC
|
640 | 9ee6e8bb | pbrook | /* The NVIC is always enabled. */
|
641 | 9ee6e8bb | pbrook | s->enabled = 1;
|
642 | 9ee6e8bb | pbrook | #else
|
643 | e69954b9 | pbrook | s->enabled = 0;
|
644 | 9ee6e8bb | pbrook | #endif
|
645 | e69954b9 | pbrook | } |
646 | e69954b9 | pbrook | |
647 | 23e39294 | pbrook | static void gic_save(QEMUFile *f, void *opaque) |
648 | 23e39294 | pbrook | { |
649 | 23e39294 | pbrook | gic_state *s = (gic_state *)opaque; |
650 | 23e39294 | pbrook | int i;
|
651 | 23e39294 | pbrook | int j;
|
652 | 23e39294 | pbrook | |
653 | 23e39294 | pbrook | qemu_put_be32(f, s->enabled); |
654 | 23e39294 | pbrook | for (i = 0; i < NCPU; i++) { |
655 | 23e39294 | pbrook | qemu_put_be32(f, s->cpu_enabled[i]); |
656 | 23e39294 | pbrook | #ifndef NVIC
|
657 | 23e39294 | pbrook | qemu_put_be32(f, s->irq_target[i]); |
658 | 23e39294 | pbrook | #endif
|
659 | 23e39294 | pbrook | for (j = 0; j < 32; j++) |
660 | 23e39294 | pbrook | qemu_put_be32(f, s->priority1[j][i]); |
661 | 23e39294 | pbrook | for (j = 0; j < GIC_NIRQ; j++) |
662 | 23e39294 | pbrook | qemu_put_be32(f, s->last_active[j][i]); |
663 | 23e39294 | pbrook | qemu_put_be32(f, s->priority_mask[i]); |
664 | 23e39294 | pbrook | qemu_put_be32(f, s->running_irq[i]); |
665 | 23e39294 | pbrook | qemu_put_be32(f, s->running_priority[i]); |
666 | 23e39294 | pbrook | qemu_put_be32(f, s->current_pending[i]); |
667 | 23e39294 | pbrook | } |
668 | 23e39294 | pbrook | for (i = 0; i < GIC_NIRQ - 32; i++) { |
669 | 23e39294 | pbrook | qemu_put_be32(f, s->priority2[i]); |
670 | 23e39294 | pbrook | } |
671 | 23e39294 | pbrook | for (i = 0; i < GIC_NIRQ; i++) { |
672 | 23e39294 | pbrook | qemu_put_byte(f, s->irq_state[i].enabled); |
673 | 23e39294 | pbrook | qemu_put_byte(f, s->irq_state[i].pending); |
674 | 23e39294 | pbrook | qemu_put_byte(f, s->irq_state[i].active); |
675 | 23e39294 | pbrook | qemu_put_byte(f, s->irq_state[i].level); |
676 | 23e39294 | pbrook | qemu_put_byte(f, s->irq_state[i].model); |
677 | 23e39294 | pbrook | qemu_put_byte(f, s->irq_state[i].trigger); |
678 | 23e39294 | pbrook | } |
679 | 23e39294 | pbrook | } |
680 | 23e39294 | pbrook | |
681 | 23e39294 | pbrook | static int gic_load(QEMUFile *f, void *opaque, int version_id) |
682 | 23e39294 | pbrook | { |
683 | 23e39294 | pbrook | gic_state *s = (gic_state *)opaque; |
684 | 23e39294 | pbrook | int i;
|
685 | 23e39294 | pbrook | int j;
|
686 | 23e39294 | pbrook | |
687 | 23e39294 | pbrook | if (version_id != 1) |
688 | 23e39294 | pbrook | return -EINVAL;
|
689 | 23e39294 | pbrook | |
690 | 23e39294 | pbrook | s->enabled = qemu_get_be32(f); |
691 | 23e39294 | pbrook | for (i = 0; i < NCPU; i++) { |
692 | 23e39294 | pbrook | s->cpu_enabled[i] = qemu_get_be32(f); |
693 | 23e39294 | pbrook | #ifndef NVIC
|
694 | 23e39294 | pbrook | s->irq_target[i] = qemu_get_be32(f); |
695 | 23e39294 | pbrook | #endif
|
696 | 23e39294 | pbrook | for (j = 0; j < 32; j++) |
697 | 23e39294 | pbrook | s->priority1[j][i] = qemu_get_be32(f); |
698 | 23e39294 | pbrook | for (j = 0; j < GIC_NIRQ; j++) |
699 | 23e39294 | pbrook | s->last_active[j][i] = qemu_get_be32(f); |
700 | 23e39294 | pbrook | s->priority_mask[i] = qemu_get_be32(f); |
701 | 23e39294 | pbrook | s->running_irq[i] = qemu_get_be32(f); |
702 | 23e39294 | pbrook | s->running_priority[i] = qemu_get_be32(f); |
703 | 23e39294 | pbrook | s->current_pending[i] = qemu_get_be32(f); |
704 | 23e39294 | pbrook | } |
705 | 23e39294 | pbrook | for (i = 0; i < GIC_NIRQ - 32; i++) { |
706 | 23e39294 | pbrook | s->priority2[i] = qemu_get_be32(f); |
707 | 23e39294 | pbrook | } |
708 | 23e39294 | pbrook | for (i = 0; i < GIC_NIRQ; i++) { |
709 | 23e39294 | pbrook | s->irq_state[i].enabled = qemu_get_byte(f); |
710 | 23e39294 | pbrook | s->irq_state[i].pending = qemu_get_byte(f); |
711 | 23e39294 | pbrook | s->irq_state[i].active = qemu_get_byte(f); |
712 | 23e39294 | pbrook | s->irq_state[i].level = qemu_get_byte(f); |
713 | 23e39294 | pbrook | s->irq_state[i].model = qemu_get_byte(f); |
714 | 23e39294 | pbrook | s->irq_state[i].trigger = qemu_get_byte(f); |
715 | 23e39294 | pbrook | } |
716 | 23e39294 | pbrook | |
717 | 23e39294 | pbrook | return 0; |
718 | 23e39294 | pbrook | } |
719 | 23e39294 | pbrook | |
720 | fe7e8758 | Paul Brook | static void gic_init(gic_state *s) |
721 | e69954b9 | pbrook | { |
722 | 9ee6e8bb | pbrook | int i;
|
723 | e69954b9 | pbrook | |
724 | 067a3ddc | Paul Brook | qdev_init_gpio_in(&s->busdev.qdev, gic_set_irq, GIC_NIRQ - 32);
|
725 | 9ee6e8bb | pbrook | for (i = 0; i < NCPU; i++) { |
726 | fe7e8758 | Paul Brook | sysbus_init_irq(&s->busdev, &s->parent_irq[i]); |
727 | e69954b9 | pbrook | } |
728 | fe7e8758 | Paul Brook | s->iomemtype = cpu_register_io_memory(0, gic_dist_readfn,
|
729 | fe7e8758 | Paul Brook | gic_dist_writefn, s); |
730 | e69954b9 | pbrook | gic_reset(s); |
731 | 23e39294 | pbrook | register_savevm("arm_gic", -1, 1, gic_save, gic_load, s); |
732 | e69954b9 | pbrook | } |