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1 | 02eb84d0 | Michael S. Tsirkin | /*
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2 | 02eb84d0 | Michael S. Tsirkin | * MSI-X device support
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3 | 02eb84d0 | Michael S. Tsirkin | *
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4 | 02eb84d0 | Michael S. Tsirkin | * This module includes support for MSI-X in pci devices.
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5 | 02eb84d0 | Michael S. Tsirkin | *
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6 | 02eb84d0 | Michael S. Tsirkin | * Author: Michael S. Tsirkin <mst@redhat.com>
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7 | 02eb84d0 | Michael S. Tsirkin | *
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8 | 02eb84d0 | Michael S. Tsirkin | * Copyright (c) 2009, Red Hat Inc, Michael S. Tsirkin (mst@redhat.com)
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9 | 02eb84d0 | Michael S. Tsirkin | *
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10 | 02eb84d0 | Michael S. Tsirkin | * This work is licensed under the terms of the GNU GPL, version 2. See
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11 | 02eb84d0 | Michael S. Tsirkin | * the COPYING file in the top-level directory.
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12 | 6b620ca3 | Paolo Bonzini | *
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13 | 6b620ca3 | Paolo Bonzini | * Contributions after 2012-01-13 are licensed under the terms of the
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14 | 6b620ca3 | Paolo Bonzini | * GNU GPL, version 2 or (at your option) any later version.
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15 | 02eb84d0 | Michael S. Tsirkin | */
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16 | 02eb84d0 | Michael S. Tsirkin | |
17 | 02eb84d0 | Michael S. Tsirkin | #include "hw.h" |
18 | 60ba3cc2 | Jan Kiszka | #include "msi.h" |
19 | 02eb84d0 | Michael S. Tsirkin | #include "msix.h" |
20 | 02eb84d0 | Michael S. Tsirkin | #include "pci.h" |
21 | bf1b0071 | Blue Swirl | #include "range.h" |
22 | 02eb84d0 | Michael S. Tsirkin | |
23 | 02eb84d0 | Michael S. Tsirkin | #define MSIX_CAP_LENGTH 12 |
24 | 02eb84d0 | Michael S. Tsirkin | |
25 | 2760952b | Michael S. Tsirkin | /* MSI enable bit and maskall bit are in byte 1 in FLAGS register */
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26 | 2760952b | Michael S. Tsirkin | #define MSIX_CONTROL_OFFSET (PCI_MSIX_FLAGS + 1) |
27 | 02eb84d0 | Michael S. Tsirkin | #define MSIX_ENABLE_MASK (PCI_MSIX_FLAGS_ENABLE >> 8) |
28 | 5b5cb086 | Michael S. Tsirkin | #define MSIX_MASKALL_MASK (PCI_MSIX_FLAGS_MASKALL >> 8) |
29 | 02eb84d0 | Michael S. Tsirkin | |
30 | bc4caf49 | Jan Kiszka | static MSIMessage msix_get_message(PCIDevice *dev, unsigned vector) |
31 | bc4caf49 | Jan Kiszka | { |
32 | d35e428c | Alex Williamson | uint8_t *table_entry = dev->msix_table + vector * PCI_MSIX_ENTRY_SIZE; |
33 | bc4caf49 | Jan Kiszka | MSIMessage msg; |
34 | bc4caf49 | Jan Kiszka | |
35 | bc4caf49 | Jan Kiszka | msg.address = pci_get_quad(table_entry + PCI_MSIX_ENTRY_LOWER_ADDR); |
36 | bc4caf49 | Jan Kiszka | msg.data = pci_get_long(table_entry + PCI_MSIX_ENTRY_DATA); |
37 | bc4caf49 | Jan Kiszka | return msg;
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38 | bc4caf49 | Jan Kiszka | } |
39 | 02eb84d0 | Michael S. Tsirkin | |
40 | 932d4a42 | Alexey Kardashevskiy | /*
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41 | 932d4a42 | Alexey Kardashevskiy | * Special API for POWER to configure the vectors through
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42 | 932d4a42 | Alexey Kardashevskiy | * a side channel. Should never be used by devices.
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43 | 932d4a42 | Alexey Kardashevskiy | */
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44 | 932d4a42 | Alexey Kardashevskiy | void msix_set_message(PCIDevice *dev, int vector, struct MSIMessage msg) |
45 | 932d4a42 | Alexey Kardashevskiy | { |
46 | 932d4a42 | Alexey Kardashevskiy | uint8_t *table_entry = dev->msix_table + vector * PCI_MSIX_ENTRY_SIZE; |
47 | 932d4a42 | Alexey Kardashevskiy | |
48 | 932d4a42 | Alexey Kardashevskiy | pci_set_quad(table_entry + PCI_MSIX_ENTRY_LOWER_ADDR, msg.address); |
49 | 932d4a42 | Alexey Kardashevskiy | pci_set_long(table_entry + PCI_MSIX_ENTRY_DATA, msg.data); |
50 | 932d4a42 | Alexey Kardashevskiy | table_entry[PCI_MSIX_ENTRY_VECTOR_CTRL] &= ~PCI_MSIX_ENTRY_CTRL_MASKBIT; |
51 | 932d4a42 | Alexey Kardashevskiy | } |
52 | 932d4a42 | Alexey Kardashevskiy | |
53 | 02eb84d0 | Michael S. Tsirkin | static uint8_t msix_pending_mask(int vector) |
54 | 02eb84d0 | Michael S. Tsirkin | { |
55 | 02eb84d0 | Michael S. Tsirkin | return 1 << (vector % 8); |
56 | 02eb84d0 | Michael S. Tsirkin | } |
57 | 02eb84d0 | Michael S. Tsirkin | |
58 | 02eb84d0 | Michael S. Tsirkin | static uint8_t *msix_pending_byte(PCIDevice *dev, int vector) |
59 | 02eb84d0 | Michael S. Tsirkin | { |
60 | d35e428c | Alex Williamson | return dev->msix_pba + vector / 8; |
61 | 02eb84d0 | Michael S. Tsirkin | } |
62 | 02eb84d0 | Michael S. Tsirkin | |
63 | 02eb84d0 | Michael S. Tsirkin | static int msix_is_pending(PCIDevice *dev, int vector) |
64 | 02eb84d0 | Michael S. Tsirkin | { |
65 | 02eb84d0 | Michael S. Tsirkin | return *msix_pending_byte(dev, vector) & msix_pending_mask(vector);
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66 | 02eb84d0 | Michael S. Tsirkin | } |
67 | 02eb84d0 | Michael S. Tsirkin | |
68 | 02eb84d0 | Michael S. Tsirkin | static void msix_set_pending(PCIDevice *dev, int vector) |
69 | 02eb84d0 | Michael S. Tsirkin | { |
70 | 02eb84d0 | Michael S. Tsirkin | *msix_pending_byte(dev, vector) |= msix_pending_mask(vector); |
71 | 02eb84d0 | Michael S. Tsirkin | } |
72 | 02eb84d0 | Michael S. Tsirkin | |
73 | 02eb84d0 | Michael S. Tsirkin | static void msix_clr_pending(PCIDevice *dev, int vector) |
74 | 02eb84d0 | Michael S. Tsirkin | { |
75 | 02eb84d0 | Michael S. Tsirkin | *msix_pending_byte(dev, vector) &= ~msix_pending_mask(vector); |
76 | 02eb84d0 | Michael S. Tsirkin | } |
77 | 02eb84d0 | Michael S. Tsirkin | |
78 | ae392c41 | Michael S. Tsirkin | static bool msix_vector_masked(PCIDevice *dev, int vector, bool fmask) |
79 | 02eb84d0 | Michael S. Tsirkin | { |
80 | ae392c41 | Michael S. Tsirkin | unsigned offset = vector * PCI_MSIX_ENTRY_SIZE + PCI_MSIX_ENTRY_VECTOR_CTRL;
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81 | d35e428c | Alex Williamson | return fmask || dev->msix_table[offset] & PCI_MSIX_ENTRY_CTRL_MASKBIT;
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82 | 5b5cb086 | Michael S. Tsirkin | } |
83 | 5b5cb086 | Michael S. Tsirkin | |
84 | ae392c41 | Michael S. Tsirkin | static bool msix_is_masked(PCIDevice *dev, int vector) |
85 | 5b5cb086 | Michael S. Tsirkin | { |
86 | ae392c41 | Michael S. Tsirkin | return msix_vector_masked(dev, vector, dev->msix_function_masked);
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87 | ae392c41 | Michael S. Tsirkin | } |
88 | ae392c41 | Michael S. Tsirkin | |
89 | 2cdfe53c | Jan Kiszka | static void msix_fire_vector_notifier(PCIDevice *dev, |
90 | 2cdfe53c | Jan Kiszka | unsigned int vector, bool is_masked) |
91 | 2cdfe53c | Jan Kiszka | { |
92 | 2cdfe53c | Jan Kiszka | MSIMessage msg; |
93 | 2cdfe53c | Jan Kiszka | int ret;
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94 | 2cdfe53c | Jan Kiszka | |
95 | 2cdfe53c | Jan Kiszka | if (!dev->msix_vector_use_notifier) {
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96 | 2cdfe53c | Jan Kiszka | return;
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97 | 2cdfe53c | Jan Kiszka | } |
98 | 2cdfe53c | Jan Kiszka | if (is_masked) {
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99 | 2cdfe53c | Jan Kiszka | dev->msix_vector_release_notifier(dev, vector); |
100 | 2cdfe53c | Jan Kiszka | } else {
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101 | 2cdfe53c | Jan Kiszka | msg = msix_get_message(dev, vector); |
102 | 2cdfe53c | Jan Kiszka | ret = dev->msix_vector_use_notifier(dev, vector, msg); |
103 | 2cdfe53c | Jan Kiszka | assert(ret >= 0);
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104 | 2cdfe53c | Jan Kiszka | } |
105 | 2cdfe53c | Jan Kiszka | } |
106 | 2cdfe53c | Jan Kiszka | |
107 | ae392c41 | Michael S. Tsirkin | static void msix_handle_mask_update(PCIDevice *dev, int vector, bool was_masked) |
108 | ae392c41 | Michael S. Tsirkin | { |
109 | ae392c41 | Michael S. Tsirkin | bool is_masked = msix_is_masked(dev, vector);
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110 | 2cdfe53c | Jan Kiszka | |
111 | ae392c41 | Michael S. Tsirkin | if (is_masked == was_masked) {
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112 | ae392c41 | Michael S. Tsirkin | return;
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113 | ae392c41 | Michael S. Tsirkin | } |
114 | ae392c41 | Michael S. Tsirkin | |
115 | 2cdfe53c | Jan Kiszka | msix_fire_vector_notifier(dev, vector, is_masked); |
116 | 2cdfe53c | Jan Kiszka | |
117 | ae392c41 | Michael S. Tsirkin | if (!is_masked && msix_is_pending(dev, vector)) {
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118 | 5b5cb086 | Michael S. Tsirkin | msix_clr_pending(dev, vector); |
119 | 5b5cb086 | Michael S. Tsirkin | msix_notify(dev, vector); |
120 | 5b5cb086 | Michael S. Tsirkin | } |
121 | 5b5cb086 | Michael S. Tsirkin | } |
122 | 5b5cb086 | Michael S. Tsirkin | |
123 | 50322249 | Michael S. Tsirkin | static void msix_update_function_masked(PCIDevice *dev) |
124 | 50322249 | Michael S. Tsirkin | { |
125 | 50322249 | Michael S. Tsirkin | dev->msix_function_masked = !msix_enabled(dev) || |
126 | 50322249 | Michael S. Tsirkin | (dev->config[dev->msix_cap + MSIX_CONTROL_OFFSET] & MSIX_MASKALL_MASK); |
127 | 50322249 | Michael S. Tsirkin | } |
128 | 50322249 | Michael S. Tsirkin | |
129 | 5b5cb086 | Michael S. Tsirkin | /* Handle MSI-X capability config write. */
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130 | 5b5cb086 | Michael S. Tsirkin | void msix_write_config(PCIDevice *dev, uint32_t addr,
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131 | 5b5cb086 | Michael S. Tsirkin | uint32_t val, int len)
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132 | 5b5cb086 | Michael S. Tsirkin | { |
133 | 5b5cb086 | Michael S. Tsirkin | unsigned enable_pos = dev->msix_cap + MSIX_CONTROL_OFFSET;
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134 | 5b5cb086 | Michael S. Tsirkin | int vector;
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135 | 50322249 | Michael S. Tsirkin | bool was_masked;
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136 | 5b5cb086 | Michael S. Tsirkin | |
137 | 7c9958b0 | Jan Kiszka | if (!msix_present(dev) || !range_covers_byte(addr, len, enable_pos)) {
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138 | 5b5cb086 | Michael S. Tsirkin | return;
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139 | 5b5cb086 | Michael S. Tsirkin | } |
140 | 5b5cb086 | Michael S. Tsirkin | |
141 | 50322249 | Michael S. Tsirkin | was_masked = dev->msix_function_masked; |
142 | 50322249 | Michael S. Tsirkin | msix_update_function_masked(dev); |
143 | 50322249 | Michael S. Tsirkin | |
144 | 5b5cb086 | Michael S. Tsirkin | if (!msix_enabled(dev)) {
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145 | 5b5cb086 | Michael S. Tsirkin | return;
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146 | 5b5cb086 | Michael S. Tsirkin | } |
147 | 5b5cb086 | Michael S. Tsirkin | |
148 | e407bf13 | Isaku Yamahata | pci_device_deassert_intx(dev); |
149 | 5b5cb086 | Michael S. Tsirkin | |
150 | 50322249 | Michael S. Tsirkin | if (dev->msix_function_masked == was_masked) {
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151 | 5b5cb086 | Michael S. Tsirkin | return;
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152 | 5b5cb086 | Michael S. Tsirkin | } |
153 | 5b5cb086 | Michael S. Tsirkin | |
154 | 5b5cb086 | Michael S. Tsirkin | for (vector = 0; vector < dev->msix_entries_nr; ++vector) { |
155 | ae392c41 | Michael S. Tsirkin | msix_handle_mask_update(dev, vector, |
156 | ae392c41 | Michael S. Tsirkin | msix_vector_masked(dev, vector, was_masked)); |
157 | 5b5cb086 | Michael S. Tsirkin | } |
158 | 02eb84d0 | Michael S. Tsirkin | } |
159 | 02eb84d0 | Michael S. Tsirkin | |
160 | d35e428c | Alex Williamson | static uint64_t msix_table_mmio_read(void *opaque, target_phys_addr_t addr, |
161 | d35e428c | Alex Williamson | unsigned size)
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162 | eebcb0a7 | Alex Williamson | { |
163 | eebcb0a7 | Alex Williamson | PCIDevice *dev = opaque; |
164 | eebcb0a7 | Alex Williamson | |
165 | d35e428c | Alex Williamson | return pci_get_long(dev->msix_table + addr);
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166 | eebcb0a7 | Alex Williamson | } |
167 | eebcb0a7 | Alex Williamson | |
168 | d35e428c | Alex Williamson | static void msix_table_mmio_write(void *opaque, target_phys_addr_t addr, |
169 | d35e428c | Alex Williamson | uint64_t val, unsigned size)
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170 | 02eb84d0 | Michael S. Tsirkin | { |
171 | 02eb84d0 | Michael S. Tsirkin | PCIDevice *dev = opaque; |
172 | d35e428c | Alex Williamson | int vector = addr / PCI_MSIX_ENTRY_SIZE;
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173 | ae392c41 | Michael S. Tsirkin | bool was_masked;
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174 | 9a93b617 | Michael S. Tsirkin | |
175 | ae392c41 | Michael S. Tsirkin | was_masked = msix_is_masked(dev, vector); |
176 | d35e428c | Alex Williamson | pci_set_long(dev->msix_table + addr, val); |
177 | ae392c41 | Michael S. Tsirkin | msix_handle_mask_update(dev, vector, was_masked); |
178 | 02eb84d0 | Michael S. Tsirkin | } |
179 | 02eb84d0 | Michael S. Tsirkin | |
180 | d35e428c | Alex Williamson | static const MemoryRegionOps msix_table_mmio_ops = { |
181 | d35e428c | Alex Williamson | .read = msix_table_mmio_read, |
182 | d35e428c | Alex Williamson | .write = msix_table_mmio_write, |
183 | d35e428c | Alex Williamson | /* TODO: MSIX should be LITTLE_ENDIAN. */
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184 | d35e428c | Alex Williamson | .endianness = DEVICE_NATIVE_ENDIAN, |
185 | d35e428c | Alex Williamson | .valid = { |
186 | d35e428c | Alex Williamson | .min_access_size = 4,
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187 | d35e428c | Alex Williamson | .max_access_size = 4,
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188 | d35e428c | Alex Williamson | }, |
189 | d35e428c | Alex Williamson | }; |
190 | d35e428c | Alex Williamson | |
191 | d35e428c | Alex Williamson | static uint64_t msix_pba_mmio_read(void *opaque, target_phys_addr_t addr, |
192 | d35e428c | Alex Williamson | unsigned size)
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193 | d35e428c | Alex Williamson | { |
194 | d35e428c | Alex Williamson | PCIDevice *dev = opaque; |
195 | d35e428c | Alex Williamson | |
196 | d35e428c | Alex Williamson | return pci_get_long(dev->msix_pba + addr);
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197 | d35e428c | Alex Williamson | } |
198 | d35e428c | Alex Williamson | |
199 | d35e428c | Alex Williamson | static const MemoryRegionOps msix_pba_mmio_ops = { |
200 | d35e428c | Alex Williamson | .read = msix_pba_mmio_read, |
201 | 2cf62ad7 | Alex Williamson | /* TODO: MSIX should be LITTLE_ENDIAN. */
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202 | 95524ae8 | Avi Kivity | .endianness = DEVICE_NATIVE_ENDIAN, |
203 | 95524ae8 | Avi Kivity | .valid = { |
204 | 95524ae8 | Avi Kivity | .min_access_size = 4,
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205 | 95524ae8 | Avi Kivity | .max_access_size = 4,
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206 | 95524ae8 | Avi Kivity | }, |
207 | 02eb84d0 | Michael S. Tsirkin | }; |
208 | 02eb84d0 | Michael S. Tsirkin | |
209 | ae1be0bb | Michael S. Tsirkin | static void msix_mask_all(struct PCIDevice *dev, unsigned nentries) |
210 | ae1be0bb | Michael S. Tsirkin | { |
211 | ae1be0bb | Michael S. Tsirkin | int vector;
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212 | 5b5f1330 | Jan Kiszka | |
213 | ae1be0bb | Michael S. Tsirkin | for (vector = 0; vector < nentries; ++vector) { |
214 | 01731cfb | Jan Kiszka | unsigned offset =
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215 | 01731cfb | Jan Kiszka | vector * PCI_MSIX_ENTRY_SIZE + PCI_MSIX_ENTRY_VECTOR_CTRL; |
216 | 5b5f1330 | Jan Kiszka | bool was_masked = msix_is_masked(dev, vector);
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217 | 5b5f1330 | Jan Kiszka | |
218 | d35e428c | Alex Williamson | dev->msix_table[offset] |= PCI_MSIX_ENTRY_CTRL_MASKBIT; |
219 | 5b5f1330 | Jan Kiszka | msix_handle_mask_update(dev, vector, was_masked); |
220 | ae1be0bb | Michael S. Tsirkin | } |
221 | ae1be0bb | Michael S. Tsirkin | } |
222 | ae1be0bb | Michael S. Tsirkin | |
223 | 5a2c2029 | Alex Williamson | /* Initialize the MSI-X structures */
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224 | 02eb84d0 | Michael S. Tsirkin | int msix_init(struct PCIDevice *dev, unsigned short nentries, |
225 | 5a2c2029 | Alex Williamson | MemoryRegion *table_bar, uint8_t table_bar_nr, |
226 | 5a2c2029 | Alex Williamson | unsigned table_offset, MemoryRegion *pba_bar,
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227 | 5a2c2029 | Alex Williamson | uint8_t pba_bar_nr, unsigned pba_offset, uint8_t cap_pos)
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228 | 02eb84d0 | Michael S. Tsirkin | { |
229 | 5a2c2029 | Alex Williamson | int cap;
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230 | d35e428c | Alex Williamson | unsigned table_size, pba_size;
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231 | 5a2c2029 | Alex Williamson | uint8_t *config; |
232 | 60ba3cc2 | Jan Kiszka | |
233 | 02eb84d0 | Michael S. Tsirkin | /* Nothing to do if MSI is not supported by interrupt controller */
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234 | 60ba3cc2 | Jan Kiszka | if (!msi_supported) {
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235 | 02eb84d0 | Michael S. Tsirkin | return -ENOTSUP;
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236 | 60ba3cc2 | Jan Kiszka | } |
237 | 5a2c2029 | Alex Williamson | |
238 | 5a2c2029 | Alex Williamson | if (nentries < 1 || nentries > PCI_MSIX_FLAGS_QSIZE + 1) { |
239 | 02eb84d0 | Michael S. Tsirkin | return -EINVAL;
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240 | 5a2c2029 | Alex Williamson | } |
241 | 02eb84d0 | Michael S. Tsirkin | |
242 | d35e428c | Alex Williamson | table_size = nentries * PCI_MSIX_ENTRY_SIZE; |
243 | d35e428c | Alex Williamson | pba_size = QEMU_ALIGN_UP(nentries, 64) / 8; |
244 | d35e428c | Alex Williamson | |
245 | 5a2c2029 | Alex Williamson | /* Sanity test: table & pba don't overlap, fit within BARs, min aligned */
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246 | 5a2c2029 | Alex Williamson | if ((table_bar_nr == pba_bar_nr &&
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247 | 5a2c2029 | Alex Williamson | ranges_overlap(table_offset, table_size, pba_offset, pba_size)) || |
248 | 5a2c2029 | Alex Williamson | table_offset + table_size > memory_region_size(table_bar) || |
249 | 5a2c2029 | Alex Williamson | pba_offset + pba_size > memory_region_size(pba_bar) || |
250 | 5a2c2029 | Alex Williamson | (table_offset | pba_offset) & PCI_MSIX_FLAGS_BIRMASK) { |
251 | 5a2c2029 | Alex Williamson | return -EINVAL;
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252 | 5a2c2029 | Alex Williamson | } |
253 | 5a2c2029 | Alex Williamson | |
254 | 5a2c2029 | Alex Williamson | cap = pci_add_capability(dev, PCI_CAP_ID_MSIX, cap_pos, MSIX_CAP_LENGTH); |
255 | 5a2c2029 | Alex Williamson | if (cap < 0) { |
256 | 5a2c2029 | Alex Williamson | return cap;
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257 | 5a2c2029 | Alex Williamson | } |
258 | 5a2c2029 | Alex Williamson | |
259 | 5a2c2029 | Alex Williamson | dev->msix_cap = cap; |
260 | 5a2c2029 | Alex Williamson | dev->cap_present |= QEMU_PCI_CAP_MSIX; |
261 | 5a2c2029 | Alex Williamson | config = dev->config + cap; |
262 | 5a2c2029 | Alex Williamson | |
263 | 5a2c2029 | Alex Williamson | pci_set_word(config + PCI_MSIX_FLAGS, nentries - 1);
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264 | 5a2c2029 | Alex Williamson | dev->msix_entries_nr = nentries; |
265 | 5a2c2029 | Alex Williamson | dev->msix_function_masked = true;
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266 | 5a2c2029 | Alex Williamson | |
267 | 5a2c2029 | Alex Williamson | pci_set_long(config + PCI_MSIX_TABLE, table_offset | table_bar_nr); |
268 | 5a2c2029 | Alex Williamson | pci_set_long(config + PCI_MSIX_PBA, pba_offset | pba_bar_nr); |
269 | 5a2c2029 | Alex Williamson | |
270 | 5a2c2029 | Alex Williamson | /* Make flags bit writable. */
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271 | 5a2c2029 | Alex Williamson | dev->wmask[cap + MSIX_CONTROL_OFFSET] |= MSIX_ENABLE_MASK | |
272 | 5a2c2029 | Alex Williamson | MSIX_MASKALL_MASK; |
273 | 02eb84d0 | Michael S. Tsirkin | |
274 | d35e428c | Alex Williamson | dev->msix_table = g_malloc0(table_size); |
275 | d35e428c | Alex Williamson | dev->msix_pba = g_malloc0(pba_size); |
276 | 5a2c2029 | Alex Williamson | dev->msix_entry_used = g_malloc0(nentries * sizeof *dev->msix_entry_used);
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277 | 5a2c2029 | Alex Williamson | |
278 | ae1be0bb | Michael S. Tsirkin | msix_mask_all(dev, nentries); |
279 | 02eb84d0 | Michael S. Tsirkin | |
280 | d35e428c | Alex Williamson | memory_region_init_io(&dev->msix_table_mmio, &msix_table_mmio_ops, dev, |
281 | d35e428c | Alex Williamson | "msix-table", table_size);
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282 | 5a2c2029 | Alex Williamson | memory_region_add_subregion(table_bar, table_offset, &dev->msix_table_mmio); |
283 | d35e428c | Alex Williamson | memory_region_init_io(&dev->msix_pba_mmio, &msix_pba_mmio_ops, dev, |
284 | d35e428c | Alex Williamson | "msix-pba", pba_size);
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285 | 5a2c2029 | Alex Williamson | memory_region_add_subregion(pba_bar, pba_offset, &dev->msix_pba_mmio); |
286 | 02eb84d0 | Michael S. Tsirkin | |
287 | 02eb84d0 | Michael S. Tsirkin | return 0; |
288 | 02eb84d0 | Michael S. Tsirkin | } |
289 | 02eb84d0 | Michael S. Tsirkin | |
290 | 53f94925 | Alex Williamson | int msix_init_exclusive_bar(PCIDevice *dev, unsigned short nentries, |
291 | 53f94925 | Alex Williamson | uint8_t bar_nr) |
292 | 53f94925 | Alex Williamson | { |
293 | 53f94925 | Alex Williamson | int ret;
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294 | 53f94925 | Alex Williamson | char *name;
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295 | 53f94925 | Alex Williamson | |
296 | 53f94925 | Alex Williamson | /*
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297 | 53f94925 | Alex Williamson | * Migration compatibility dictates that this remains a 4k
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298 | 53f94925 | Alex Williamson | * BAR with the vector table in the lower half and PBA in
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299 | 53f94925 | Alex Williamson | * the upper half. Do not use these elsewhere!
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300 | 53f94925 | Alex Williamson | */
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301 | 53f94925 | Alex Williamson | #define MSIX_EXCLUSIVE_BAR_SIZE 4096 |
302 | 5a2c2029 | Alex Williamson | #define MSIX_EXCLUSIVE_BAR_TABLE_OFFSET 0 |
303 | 53f94925 | Alex Williamson | #define MSIX_EXCLUSIVE_BAR_PBA_OFFSET (MSIX_EXCLUSIVE_BAR_SIZE / 2) |
304 | 5a2c2029 | Alex Williamson | #define MSIX_EXCLUSIVE_CAP_OFFSET 0 |
305 | 53f94925 | Alex Williamson | |
306 | 53f94925 | Alex Williamson | if (nentries * PCI_MSIX_ENTRY_SIZE > MSIX_EXCLUSIVE_BAR_PBA_OFFSET) {
|
307 | 53f94925 | Alex Williamson | return -EINVAL;
|
308 | 53f94925 | Alex Williamson | } |
309 | 53f94925 | Alex Williamson | |
310 | 5f893b4e | Gerd Hoffmann | name = g_strdup_printf("%s-msix", dev->name);
|
311 | 53f94925 | Alex Williamson | memory_region_init(&dev->msix_exclusive_bar, name, MSIX_EXCLUSIVE_BAR_SIZE); |
312 | 5f893b4e | Gerd Hoffmann | g_free(name); |
313 | 53f94925 | Alex Williamson | |
314 | 53f94925 | Alex Williamson | ret = msix_init(dev, nentries, &dev->msix_exclusive_bar, bar_nr, |
315 | 5a2c2029 | Alex Williamson | MSIX_EXCLUSIVE_BAR_TABLE_OFFSET, &dev->msix_exclusive_bar, |
316 | 5a2c2029 | Alex Williamson | bar_nr, MSIX_EXCLUSIVE_BAR_PBA_OFFSET, |
317 | 5a2c2029 | Alex Williamson | MSIX_EXCLUSIVE_CAP_OFFSET); |
318 | 53f94925 | Alex Williamson | if (ret) {
|
319 | 53f94925 | Alex Williamson | memory_region_destroy(&dev->msix_exclusive_bar); |
320 | 53f94925 | Alex Williamson | return ret;
|
321 | 53f94925 | Alex Williamson | } |
322 | 53f94925 | Alex Williamson | |
323 | 53f94925 | Alex Williamson | pci_register_bar(dev, bar_nr, PCI_BASE_ADDRESS_SPACE_MEMORY, |
324 | 53f94925 | Alex Williamson | &dev->msix_exclusive_bar); |
325 | 53f94925 | Alex Williamson | |
326 | 53f94925 | Alex Williamson | return 0; |
327 | 53f94925 | Alex Williamson | } |
328 | 53f94925 | Alex Williamson | |
329 | 98304c84 | Michael S. Tsirkin | static void msix_free_irq_entries(PCIDevice *dev) |
330 | 98304c84 | Michael S. Tsirkin | { |
331 | 98304c84 | Michael S. Tsirkin | int vector;
|
332 | 98304c84 | Michael S. Tsirkin | |
333 | 98304c84 | Michael S. Tsirkin | for (vector = 0; vector < dev->msix_entries_nr; ++vector) { |
334 | 98304c84 | Michael S. Tsirkin | dev->msix_entry_used[vector] = 0;
|
335 | 98304c84 | Michael S. Tsirkin | msix_clr_pending(dev, vector); |
336 | 98304c84 | Michael S. Tsirkin | } |
337 | 98304c84 | Michael S. Tsirkin | } |
338 | 98304c84 | Michael S. Tsirkin | |
339 | 3cac001e | Michael S. Tsirkin | static void msix_clear_all_vectors(PCIDevice *dev) |
340 | 3cac001e | Michael S. Tsirkin | { |
341 | 3cac001e | Michael S. Tsirkin | int vector;
|
342 | 3cac001e | Michael S. Tsirkin | |
343 | 3cac001e | Michael S. Tsirkin | for (vector = 0; vector < dev->msix_entries_nr; ++vector) { |
344 | 3cac001e | Michael S. Tsirkin | msix_clr_pending(dev, vector); |
345 | 3cac001e | Michael S. Tsirkin | } |
346 | 3cac001e | Michael S. Tsirkin | } |
347 | 3cac001e | Michael S. Tsirkin | |
348 | 02eb84d0 | Michael S. Tsirkin | /* Clean up resources for the device. */
|
349 | 572992ee | Alex Williamson | void msix_uninit(PCIDevice *dev, MemoryRegion *table_bar, MemoryRegion *pba_bar)
|
350 | 02eb84d0 | Michael S. Tsirkin | { |
351 | 44701ab7 | Jan Kiszka | if (!msix_present(dev)) {
|
352 | 572992ee | Alex Williamson | return;
|
353 | 44701ab7 | Jan Kiszka | } |
354 | 02eb84d0 | Michael S. Tsirkin | pci_del_capability(dev, PCI_CAP_ID_MSIX, MSIX_CAP_LENGTH); |
355 | 02eb84d0 | Michael S. Tsirkin | dev->msix_cap = 0;
|
356 | 02eb84d0 | Michael S. Tsirkin | msix_free_irq_entries(dev); |
357 | 02eb84d0 | Michael S. Tsirkin | dev->msix_entries_nr = 0;
|
358 | 5a2c2029 | Alex Williamson | memory_region_del_subregion(pba_bar, &dev->msix_pba_mmio); |
359 | d35e428c | Alex Williamson | memory_region_destroy(&dev->msix_pba_mmio); |
360 | d35e428c | Alex Williamson | g_free(dev->msix_pba); |
361 | d35e428c | Alex Williamson | dev->msix_pba = NULL;
|
362 | 5a2c2029 | Alex Williamson | memory_region_del_subregion(table_bar, &dev->msix_table_mmio); |
363 | d35e428c | Alex Williamson | memory_region_destroy(&dev->msix_table_mmio); |
364 | d35e428c | Alex Williamson | g_free(dev->msix_table); |
365 | d35e428c | Alex Williamson | dev->msix_table = NULL;
|
366 | 7267c094 | Anthony Liguori | g_free(dev->msix_entry_used); |
367 | 02eb84d0 | Michael S. Tsirkin | dev->msix_entry_used = NULL;
|
368 | 02eb84d0 | Michael S. Tsirkin | dev->cap_present &= ~QEMU_PCI_CAP_MSIX; |
369 | 572992ee | Alex Williamson | return;
|
370 | 02eb84d0 | Michael S. Tsirkin | } |
371 | 02eb84d0 | Michael S. Tsirkin | |
372 | 53f94925 | Alex Williamson | void msix_uninit_exclusive_bar(PCIDevice *dev)
|
373 | 53f94925 | Alex Williamson | { |
374 | 53f94925 | Alex Williamson | if (msix_present(dev)) {
|
375 | 5a2c2029 | Alex Williamson | msix_uninit(dev, &dev->msix_exclusive_bar, &dev->msix_exclusive_bar); |
376 | 53f94925 | Alex Williamson | memory_region_destroy(&dev->msix_exclusive_bar); |
377 | 53f94925 | Alex Williamson | } |
378 | 53f94925 | Alex Williamson | } |
379 | 53f94925 | Alex Williamson | |
380 | 02eb84d0 | Michael S. Tsirkin | void msix_save(PCIDevice *dev, QEMUFile *f)
|
381 | 02eb84d0 | Michael S. Tsirkin | { |
382 | 9a3e12c8 | Michael S. Tsirkin | unsigned n = dev->msix_entries_nr;
|
383 | 9a3e12c8 | Michael S. Tsirkin | |
384 | 44701ab7 | Jan Kiszka | if (!msix_present(dev)) {
|
385 | 9a3e12c8 | Michael S. Tsirkin | return;
|
386 | 72755a70 | Michael S. Tsirkin | } |
387 | 9a3e12c8 | Michael S. Tsirkin | |
388 | d35e428c | Alex Williamson | qemu_put_buffer(f, dev->msix_table, n * PCI_MSIX_ENTRY_SIZE); |
389 | d35e428c | Alex Williamson | qemu_put_buffer(f, dev->msix_pba, (n + 7) / 8); |
390 | 02eb84d0 | Michael S. Tsirkin | } |
391 | 02eb84d0 | Michael S. Tsirkin | |
392 | 02eb84d0 | Michael S. Tsirkin | /* Should be called after restoring the config space. */
|
393 | 02eb84d0 | Michael S. Tsirkin | void msix_load(PCIDevice *dev, QEMUFile *f)
|
394 | 02eb84d0 | Michael S. Tsirkin | { |
395 | 02eb84d0 | Michael S. Tsirkin | unsigned n = dev->msix_entries_nr;
|
396 | 2cdfe53c | Jan Kiszka | unsigned int vector; |
397 | 02eb84d0 | Michael S. Tsirkin | |
398 | 44701ab7 | Jan Kiszka | if (!msix_present(dev)) {
|
399 | 02eb84d0 | Michael S. Tsirkin | return;
|
400 | 98846d73 | Blue Swirl | } |
401 | 02eb84d0 | Michael S. Tsirkin | |
402 | 3cac001e | Michael S. Tsirkin | msix_clear_all_vectors(dev); |
403 | d35e428c | Alex Williamson | qemu_get_buffer(f, dev->msix_table, n * PCI_MSIX_ENTRY_SIZE); |
404 | d35e428c | Alex Williamson | qemu_get_buffer(f, dev->msix_pba, (n + 7) / 8); |
405 | 50322249 | Michael S. Tsirkin | msix_update_function_masked(dev); |
406 | 2cdfe53c | Jan Kiszka | |
407 | 2cdfe53c | Jan Kiszka | for (vector = 0; vector < n; vector++) { |
408 | 2cdfe53c | Jan Kiszka | msix_handle_mask_update(dev, vector, true);
|
409 | 2cdfe53c | Jan Kiszka | } |
410 | 02eb84d0 | Michael S. Tsirkin | } |
411 | 02eb84d0 | Michael S. Tsirkin | |
412 | 02eb84d0 | Michael S. Tsirkin | /* Does device support MSI-X? */
|
413 | 02eb84d0 | Michael S. Tsirkin | int msix_present(PCIDevice *dev)
|
414 | 02eb84d0 | Michael S. Tsirkin | { |
415 | 02eb84d0 | Michael S. Tsirkin | return dev->cap_present & QEMU_PCI_CAP_MSIX;
|
416 | 02eb84d0 | Michael S. Tsirkin | } |
417 | 02eb84d0 | Michael S. Tsirkin | |
418 | 02eb84d0 | Michael S. Tsirkin | /* Is MSI-X enabled? */
|
419 | 02eb84d0 | Michael S. Tsirkin | int msix_enabled(PCIDevice *dev)
|
420 | 02eb84d0 | Michael S. Tsirkin | { |
421 | 02eb84d0 | Michael S. Tsirkin | return (dev->cap_present & QEMU_PCI_CAP_MSIX) &&
|
422 | 2760952b | Michael S. Tsirkin | (dev->config[dev->msix_cap + MSIX_CONTROL_OFFSET] & |
423 | 02eb84d0 | Michael S. Tsirkin | MSIX_ENABLE_MASK); |
424 | 02eb84d0 | Michael S. Tsirkin | } |
425 | 02eb84d0 | Michael S. Tsirkin | |
426 | 02eb84d0 | Michael S. Tsirkin | /* Send an MSI-X message */
|
427 | 02eb84d0 | Michael S. Tsirkin | void msix_notify(PCIDevice *dev, unsigned vector) |
428 | 02eb84d0 | Michael S. Tsirkin | { |
429 | bc4caf49 | Jan Kiszka | MSIMessage msg; |
430 | 02eb84d0 | Michael S. Tsirkin | |
431 | 02eb84d0 | Michael S. Tsirkin | if (vector >= dev->msix_entries_nr || !dev->msix_entry_used[vector])
|
432 | 02eb84d0 | Michael S. Tsirkin | return;
|
433 | 02eb84d0 | Michael S. Tsirkin | if (msix_is_masked(dev, vector)) {
|
434 | 02eb84d0 | Michael S. Tsirkin | msix_set_pending(dev, vector); |
435 | 02eb84d0 | Michael S. Tsirkin | return;
|
436 | 02eb84d0 | Michael S. Tsirkin | } |
437 | 02eb84d0 | Michael S. Tsirkin | |
438 | bc4caf49 | Jan Kiszka | msg = msix_get_message(dev, vector); |
439 | bc4caf49 | Jan Kiszka | |
440 | bc4caf49 | Jan Kiszka | stl_le_phys(msg.address, msg.data); |
441 | 02eb84d0 | Michael S. Tsirkin | } |
442 | 02eb84d0 | Michael S. Tsirkin | |
443 | 02eb84d0 | Michael S. Tsirkin | void msix_reset(PCIDevice *dev)
|
444 | 02eb84d0 | Michael S. Tsirkin | { |
445 | 44701ab7 | Jan Kiszka | if (!msix_present(dev)) {
|
446 | 02eb84d0 | Michael S. Tsirkin | return;
|
447 | 44701ab7 | Jan Kiszka | } |
448 | 3cac001e | Michael S. Tsirkin | msix_clear_all_vectors(dev); |
449 | 2760952b | Michael S. Tsirkin | dev->config[dev->msix_cap + MSIX_CONTROL_OFFSET] &= |
450 | 2760952b | Michael S. Tsirkin | ~dev->wmask[dev->msix_cap + MSIX_CONTROL_OFFSET]; |
451 | d35e428c | Alex Williamson | memset(dev->msix_table, 0, dev->msix_entries_nr * PCI_MSIX_ENTRY_SIZE);
|
452 | d35e428c | Alex Williamson | memset(dev->msix_pba, 0, QEMU_ALIGN_UP(dev->msix_entries_nr, 64) / 8); |
453 | ae1be0bb | Michael S. Tsirkin | msix_mask_all(dev, dev->msix_entries_nr); |
454 | 02eb84d0 | Michael S. Tsirkin | } |
455 | 02eb84d0 | Michael S. Tsirkin | |
456 | 02eb84d0 | Michael S. Tsirkin | /* PCI spec suggests that devices make it possible for software to configure
|
457 | 02eb84d0 | Michael S. Tsirkin | * less vectors than supported by the device, but does not specify a standard
|
458 | 02eb84d0 | Michael S. Tsirkin | * mechanism for devices to do so.
|
459 | 02eb84d0 | Michael S. Tsirkin | *
|
460 | 02eb84d0 | Michael S. Tsirkin | * We support this by asking devices to declare vectors software is going to
|
461 | 02eb84d0 | Michael S. Tsirkin | * actually use, and checking this on the notification path. Devices that
|
462 | 02eb84d0 | Michael S. Tsirkin | * don't want to follow the spec suggestion can declare all vectors as used. */
|
463 | 02eb84d0 | Michael S. Tsirkin | |
464 | 02eb84d0 | Michael S. Tsirkin | /* Mark vector as used. */
|
465 | 02eb84d0 | Michael S. Tsirkin | int msix_vector_use(PCIDevice *dev, unsigned vector) |
466 | 02eb84d0 | Michael S. Tsirkin | { |
467 | 02eb84d0 | Michael S. Tsirkin | if (vector >= dev->msix_entries_nr)
|
468 | 02eb84d0 | Michael S. Tsirkin | return -EINVAL;
|
469 | 02eb84d0 | Michael S. Tsirkin | dev->msix_entry_used[vector]++; |
470 | 02eb84d0 | Michael S. Tsirkin | return 0; |
471 | 02eb84d0 | Michael S. Tsirkin | } |
472 | 02eb84d0 | Michael S. Tsirkin | |
473 | 02eb84d0 | Michael S. Tsirkin | /* Mark vector as unused. */
|
474 | 02eb84d0 | Michael S. Tsirkin | void msix_vector_unuse(PCIDevice *dev, unsigned vector) |
475 | 02eb84d0 | Michael S. Tsirkin | { |
476 | 98304c84 | Michael S. Tsirkin | if (vector >= dev->msix_entries_nr || !dev->msix_entry_used[vector]) {
|
477 | 98304c84 | Michael S. Tsirkin | return;
|
478 | 98304c84 | Michael S. Tsirkin | } |
479 | 98304c84 | Michael S. Tsirkin | if (--dev->msix_entry_used[vector]) {
|
480 | 98304c84 | Michael S. Tsirkin | return;
|
481 | 98304c84 | Michael S. Tsirkin | } |
482 | 98304c84 | Michael S. Tsirkin | msix_clr_pending(dev, vector); |
483 | 02eb84d0 | Michael S. Tsirkin | } |
484 | b5f28bca | Michael S. Tsirkin | |
485 | b5f28bca | Michael S. Tsirkin | void msix_unuse_all_vectors(PCIDevice *dev)
|
486 | b5f28bca | Michael S. Tsirkin | { |
487 | 44701ab7 | Jan Kiszka | if (!msix_present(dev)) {
|
488 | b5f28bca | Michael S. Tsirkin | return;
|
489 | 44701ab7 | Jan Kiszka | } |
490 | b5f28bca | Michael S. Tsirkin | msix_free_irq_entries(dev); |
491 | b5f28bca | Michael S. Tsirkin | } |
492 | 2cdfe53c | Jan Kiszka | |
493 | cb697aaa | Jan Kiszka | unsigned int msix_nr_vectors_allocated(const PCIDevice *dev) |
494 | cb697aaa | Jan Kiszka | { |
495 | cb697aaa | Jan Kiszka | return dev->msix_entries_nr;
|
496 | cb697aaa | Jan Kiszka | } |
497 | cb697aaa | Jan Kiszka | |
498 | 2cdfe53c | Jan Kiszka | static int msix_set_notifier_for_vector(PCIDevice *dev, unsigned int vector) |
499 | 2cdfe53c | Jan Kiszka | { |
500 | 2cdfe53c | Jan Kiszka | MSIMessage msg; |
501 | 2cdfe53c | Jan Kiszka | |
502 | 2cdfe53c | Jan Kiszka | if (msix_is_masked(dev, vector)) {
|
503 | 2cdfe53c | Jan Kiszka | return 0; |
504 | 2cdfe53c | Jan Kiszka | } |
505 | 2cdfe53c | Jan Kiszka | msg = msix_get_message(dev, vector); |
506 | 2cdfe53c | Jan Kiszka | return dev->msix_vector_use_notifier(dev, vector, msg);
|
507 | 2cdfe53c | Jan Kiszka | } |
508 | 2cdfe53c | Jan Kiszka | |
509 | 2cdfe53c | Jan Kiszka | static void msix_unset_notifier_for_vector(PCIDevice *dev, unsigned int vector) |
510 | 2cdfe53c | Jan Kiszka | { |
511 | 2cdfe53c | Jan Kiszka | if (msix_is_masked(dev, vector)) {
|
512 | 2cdfe53c | Jan Kiszka | return;
|
513 | 2cdfe53c | Jan Kiszka | } |
514 | 2cdfe53c | Jan Kiszka | dev->msix_vector_release_notifier(dev, vector); |
515 | 2cdfe53c | Jan Kiszka | } |
516 | 2cdfe53c | Jan Kiszka | |
517 | 2cdfe53c | Jan Kiszka | int msix_set_vector_notifiers(PCIDevice *dev,
|
518 | 2cdfe53c | Jan Kiszka | MSIVectorUseNotifier use_notifier, |
519 | 2cdfe53c | Jan Kiszka | MSIVectorReleaseNotifier release_notifier) |
520 | 2cdfe53c | Jan Kiszka | { |
521 | 2cdfe53c | Jan Kiszka | int vector, ret;
|
522 | 2cdfe53c | Jan Kiszka | |
523 | 2cdfe53c | Jan Kiszka | assert(use_notifier && release_notifier); |
524 | 2cdfe53c | Jan Kiszka | |
525 | 2cdfe53c | Jan Kiszka | dev->msix_vector_use_notifier = use_notifier; |
526 | 2cdfe53c | Jan Kiszka | dev->msix_vector_release_notifier = release_notifier; |
527 | 2cdfe53c | Jan Kiszka | |
528 | 2cdfe53c | Jan Kiszka | if ((dev->config[dev->msix_cap + MSIX_CONTROL_OFFSET] &
|
529 | 2cdfe53c | Jan Kiszka | (MSIX_ENABLE_MASK | MSIX_MASKALL_MASK)) == MSIX_ENABLE_MASK) { |
530 | 2cdfe53c | Jan Kiszka | for (vector = 0; vector < dev->msix_entries_nr; vector++) { |
531 | 2cdfe53c | Jan Kiszka | ret = msix_set_notifier_for_vector(dev, vector); |
532 | 2cdfe53c | Jan Kiszka | if (ret < 0) { |
533 | 2cdfe53c | Jan Kiszka | goto undo;
|
534 | 2cdfe53c | Jan Kiszka | } |
535 | 2cdfe53c | Jan Kiszka | } |
536 | 2cdfe53c | Jan Kiszka | } |
537 | 2cdfe53c | Jan Kiszka | return 0; |
538 | 2cdfe53c | Jan Kiszka | |
539 | 2cdfe53c | Jan Kiszka | undo:
|
540 | 2cdfe53c | Jan Kiszka | while (--vector >= 0) { |
541 | 2cdfe53c | Jan Kiszka | msix_unset_notifier_for_vector(dev, vector); |
542 | 2cdfe53c | Jan Kiszka | } |
543 | 2cdfe53c | Jan Kiszka | dev->msix_vector_use_notifier = NULL;
|
544 | 2cdfe53c | Jan Kiszka | dev->msix_vector_release_notifier = NULL;
|
545 | 2cdfe53c | Jan Kiszka | return ret;
|
546 | 2cdfe53c | Jan Kiszka | } |
547 | 2cdfe53c | Jan Kiszka | |
548 | 2cdfe53c | Jan Kiszka | void msix_unset_vector_notifiers(PCIDevice *dev)
|
549 | 2cdfe53c | Jan Kiszka | { |
550 | 2cdfe53c | Jan Kiszka | int vector;
|
551 | 2cdfe53c | Jan Kiszka | |
552 | 2cdfe53c | Jan Kiszka | assert(dev->msix_vector_use_notifier && |
553 | 2cdfe53c | Jan Kiszka | dev->msix_vector_release_notifier); |
554 | 2cdfe53c | Jan Kiszka | |
555 | 2cdfe53c | Jan Kiszka | if ((dev->config[dev->msix_cap + MSIX_CONTROL_OFFSET] &
|
556 | 2cdfe53c | Jan Kiszka | (MSIX_ENABLE_MASK | MSIX_MASKALL_MASK)) == MSIX_ENABLE_MASK) { |
557 | 2cdfe53c | Jan Kiszka | for (vector = 0; vector < dev->msix_entries_nr; vector++) { |
558 | 2cdfe53c | Jan Kiszka | msix_unset_notifier_for_vector(dev, vector); |
559 | 2cdfe53c | Jan Kiszka | } |
560 | 2cdfe53c | Jan Kiszka | } |
561 | 2cdfe53c | Jan Kiszka | dev->msix_vector_use_notifier = NULL;
|
562 | 2cdfe53c | Jan Kiszka | dev->msix_vector_release_notifier = NULL;
|
563 | 2cdfe53c | Jan Kiszka | } |