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/*
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* SH7750 device
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*
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* Copyright (c) 2007 Magnus Damm
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* Copyright (c) 2005 Samuel Tardieu
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include <stdio.h> |
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#include "hw.h" |
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#include "sh.h" |
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#include "sysemu.h" |
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#include "sh7750_regs.h" |
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#include "sh7750_regnames.h" |
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#include "sh_intc.h" |
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#include "cpu.h" |
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#include "exec-memory.h" |
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#define NB_DEVICES 4 |
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typedef struct SH7750State { |
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MemoryRegion iomem; |
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MemoryRegion iomem_1f0; |
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MemoryRegion iomem_ff0; |
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MemoryRegion iomem_1f8; |
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MemoryRegion iomem_ff8; |
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MemoryRegion iomem_1fc; |
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MemoryRegion iomem_ffc; |
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MemoryRegion mmct_iomem; |
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/* CPU */
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CPUSH4State *cpu; |
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/* Peripheral frequency in Hz */
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uint32_t periph_freq; |
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/* SDRAM controller */
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uint32_t bcr1; |
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uint16_t bcr2; |
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uint16_t bcr3; |
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uint32_t bcr4; |
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uint16_t rfcr; |
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/* PCMCIA controller */
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uint16_t pcr; |
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/* IO ports */
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uint16_t gpioic; |
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uint32_t pctra; |
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uint32_t pctrb; |
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uint16_t portdira; /* Cached */
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uint16_t portpullupa; /* Cached */
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uint16_t portdirb; /* Cached */
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uint16_t portpullupb; /* Cached */
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uint16_t pdtra; |
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uint16_t pdtrb; |
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uint16_t periph_pdtra; /* Imposed by the peripherals */
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uint16_t periph_portdira; /* Direction seen from the peripherals */
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uint16_t periph_pdtrb; /* Imposed by the peripherals */
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uint16_t periph_portdirb; /* Direction seen from the peripherals */
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sh7750_io_device *devices[NB_DEVICES]; /* External peripherals */
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|
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/* Cache */
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uint32_t ccr; |
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|
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struct intc_desc intc;
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} SH7750State; |
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|
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static inline int has_bcr3_and_bcr4(SH7750State * s) |
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{ |
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return (s->cpu->features & SH_FEATURE_BCR3_AND_BCR4);
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} |
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/**********************************************************************
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I/O ports
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**********************************************************************/
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|
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int sh7750_register_io_device(SH7750State * s, sh7750_io_device * device)
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{ |
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int i;
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|
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for (i = 0; i < NB_DEVICES; i++) { |
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if (s->devices[i] == NULL) { |
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s->devices[i] = device; |
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return 0; |
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} |
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} |
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return -1; |
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} |
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|
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static uint16_t portdir(uint32_t v)
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{ |
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#define EVENPORTMASK(n) ((v & (1<<((n)<<1))) >> (n)) |
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return
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EVENPORTMASK(15) | EVENPORTMASK(14) | EVENPORTMASK(13) | |
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EVENPORTMASK(12) | EVENPORTMASK(11) | EVENPORTMASK(10) | |
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EVENPORTMASK(9) | EVENPORTMASK(8) | EVENPORTMASK(7) | |
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EVENPORTMASK(6) | EVENPORTMASK(5) | EVENPORTMASK(4) | |
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EVENPORTMASK(3) | EVENPORTMASK(2) | EVENPORTMASK(1) | |
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EVENPORTMASK(0);
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} |
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|
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static uint16_t portpullup(uint32_t v)
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{ |
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#define ODDPORTMASK(n) ((v & (1<<(((n)<<1)+1))) >> (n)) |
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return
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ODDPORTMASK(15) | ODDPORTMASK(14) | ODDPORTMASK(13) | |
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ODDPORTMASK(12) | ODDPORTMASK(11) | ODDPORTMASK(10) | |
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ODDPORTMASK(9) | ODDPORTMASK(8) | ODDPORTMASK(7) | ODDPORTMASK(6) | |
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ODDPORTMASK(5) | ODDPORTMASK(4) | ODDPORTMASK(3) | ODDPORTMASK(2) | |
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ODDPORTMASK(1) | ODDPORTMASK(0); |
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} |
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|
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static uint16_t porta_lines(SH7750State * s)
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{ |
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return (s->portdira & s->pdtra) | /* CPU */ |
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(s->periph_portdira & s->periph_pdtra) | /* Peripherals */
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(~(s->portdira | s->periph_portdira) & s->portpullupa); /* Pullups */
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} |
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static uint16_t portb_lines(SH7750State * s)
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{ |
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return (s->portdirb & s->pdtrb) | /* CPU */ |
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(s->periph_portdirb & s->periph_pdtrb) | /* Peripherals */
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(~(s->portdirb | s->periph_portdirb) & s->portpullupb); /* Pullups */
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} |
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static void gen_port_interrupts(SH7750State * s) |
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{ |
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/* XXXXX interrupts not generated */
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} |
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|
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static void porta_changed(SH7750State * s, uint16_t prev) |
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{ |
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uint16_t currenta, changes; |
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int i, r = 0; |
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#if 0
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fprintf(stderr, "porta changed from 0x%04x to 0x%04x\n",
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prev, porta_lines(s));
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fprintf(stderr, "pdtra=0x%04x, pctra=0x%08x\n", s->pdtra, s->pctra);
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#endif
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currenta = porta_lines(s); |
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if (currenta == prev)
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return;
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changes = currenta ^ prev; |
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for (i = 0; i < NB_DEVICES; i++) { |
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if (s->devices[i] && (s->devices[i]->portamask_trigger & changes)) {
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r |= s->devices[i]->port_change_cb(currenta, portb_lines(s), |
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&s->periph_pdtra, |
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&s->periph_portdira, |
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&s->periph_pdtrb, |
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&s->periph_portdirb); |
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} |
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} |
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if (r)
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gen_port_interrupts(s); |
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} |
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static void portb_changed(SH7750State * s, uint16_t prev) |
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{ |
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uint16_t currentb, changes; |
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int i, r = 0; |
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currentb = portb_lines(s); |
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if (currentb == prev)
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return;
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changes = currentb ^ prev; |
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for (i = 0; i < NB_DEVICES; i++) { |
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if (s->devices[i] && (s->devices[i]->portbmask_trigger & changes)) {
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r |= s->devices[i]->port_change_cb(portb_lines(s), currentb, |
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&s->periph_pdtra, |
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&s->periph_portdira, |
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&s->periph_pdtrb, |
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&s->periph_portdirb); |
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} |
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} |
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if (r)
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gen_port_interrupts(s); |
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} |
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/**********************************************************************
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Memory
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**********************************************************************/
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static void error_access(const char *kind, target_phys_addr_t addr) |
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{ |
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fprintf(stderr, "%s to %s (0x" TARGET_FMT_plx ") not supported\n", |
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kind, regname(addr), addr); |
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} |
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static void ignore_access(const char *kind, target_phys_addr_t addr) |
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{ |
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fprintf(stderr, "%s to %s (0x" TARGET_FMT_plx ") ignored\n", |
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kind, regname(addr), addr); |
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} |
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static uint32_t sh7750_mem_readb(void *opaque, target_phys_addr_t addr) |
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{ |
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switch (addr) {
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default:
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error_access("byte read", addr);
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abort(); |
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} |
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} |
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static uint32_t sh7750_mem_readw(void *opaque, target_phys_addr_t addr) |
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{ |
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SH7750State *s = opaque; |
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switch (addr) {
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case SH7750_BCR2_A7:
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return s->bcr2;
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case SH7750_BCR3_A7:
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if(!has_bcr3_and_bcr4(s))
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error_access("word read", addr);
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return s->bcr3;
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case SH7750_FRQCR_A7:
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return 0; |
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case SH7750_PCR_A7:
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return s->pcr;
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case SH7750_RFCR_A7:
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fprintf(stderr, |
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"Read access to refresh count register, incrementing\n");
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return s->rfcr++;
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case SH7750_PDTRA_A7:
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return porta_lines(s);
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case SH7750_PDTRB_A7:
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return portb_lines(s);
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case SH7750_RTCOR_A7:
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case SH7750_RTCNT_A7:
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case SH7750_RTCSR_A7:
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ignore_access("word read", addr);
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return 0; |
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default:
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error_access("word read", addr);
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abort(); |
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} |
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} |
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static uint32_t sh7750_mem_readl(void *opaque, target_phys_addr_t addr) |
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{ |
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SH7750State *s = opaque; |
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switch (addr) {
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case SH7750_BCR1_A7:
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return s->bcr1;
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case SH7750_BCR4_A7:
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if(!has_bcr3_and_bcr4(s))
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error_access("long read", addr);
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return s->bcr4;
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case SH7750_WCR1_A7:
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case SH7750_WCR2_A7:
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case SH7750_WCR3_A7:
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case SH7750_MCR_A7:
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ignore_access("long read", addr);
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return 0; |
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case SH7750_MMUCR_A7:
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return s->cpu->mmucr;
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case SH7750_PTEH_A7:
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return s->cpu->pteh;
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case SH7750_PTEL_A7:
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return s->cpu->ptel;
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case SH7750_TTB_A7:
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return s->cpu->ttb;
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case SH7750_TEA_A7:
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return s->cpu->tea;
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case SH7750_TRA_A7:
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return s->cpu->tra;
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case SH7750_EXPEVT_A7:
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return s->cpu->expevt;
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case SH7750_INTEVT_A7:
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return s->cpu->intevt;
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case SH7750_CCR_A7:
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return s->ccr;
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case 0x1f000030: /* Processor version */ |
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return s->cpu->pvr;
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case 0x1f000040: /* Cache version */ |
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return s->cpu->cvr;
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case 0x1f000044: /* Processor revision */ |
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return s->cpu->prr;
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default:
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error_access("long read", addr);
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abort(); |
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} |
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} |
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|
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#define is_in_sdrmx(a, x) (a >= SH7750_SDMR ## x ## _A7 \ |
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&& a <= (SH7750_SDMR ## x ## _A7 + SH7750_SDMR ## x ## _REGNB)) |
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static void sh7750_mem_writeb(void *opaque, target_phys_addr_t addr, |
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uint32_t mem_value) |
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{ |
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if (is_in_sdrmx(addr, 2) || is_in_sdrmx(addr, 3)) { |
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ignore_access("byte write", addr);
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return;
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} |
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error_access("byte write", addr);
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abort(); |
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} |
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|
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static void sh7750_mem_writew(void *opaque, target_phys_addr_t addr, |
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uint32_t mem_value) |
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{ |
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SH7750State *s = opaque; |
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uint16_t temp; |
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|
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switch (addr) {
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/* SDRAM controller */
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case SH7750_BCR2_A7:
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s->bcr2 = mem_value; |
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return;
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case SH7750_BCR3_A7:
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if(!has_bcr3_and_bcr4(s))
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error_access("word write", addr);
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s->bcr3 = mem_value; |
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return;
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case SH7750_PCR_A7:
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s->pcr = mem_value; |
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return;
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case SH7750_RTCNT_A7:
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case SH7750_RTCOR_A7:
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case SH7750_RTCSR_A7:
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ignore_access("word write", addr);
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return;
|
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/* IO ports */
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case SH7750_PDTRA_A7:
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temp = porta_lines(s); |
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s->pdtra = mem_value; |
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porta_changed(s, temp); |
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return;
|
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case SH7750_PDTRB_A7:
|
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temp = portb_lines(s); |
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s->pdtrb = mem_value; |
350 |
portb_changed(s, temp); |
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return;
|
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case SH7750_RFCR_A7:
|
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fprintf(stderr, "Write access to refresh count register\n");
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s->rfcr = mem_value; |
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return;
|
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case SH7750_GPIOIC_A7:
|
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s->gpioic = mem_value; |
358 |
if (mem_value != 0) { |
359 |
fprintf(stderr, "I/O interrupts not implemented\n");
|
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abort(); |
361 |
} |
362 |
return;
|
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default:
|
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error_access("word write", addr);
|
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abort(); |
366 |
} |
367 |
} |
368 |
|
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static void sh7750_mem_writel(void *opaque, target_phys_addr_t addr, |
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uint32_t mem_value) |
371 |
{ |
372 |
SH7750State *s = opaque; |
373 |
uint16_t temp; |
374 |
|
375 |
switch (addr) {
|
376 |
/* SDRAM controller */
|
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case SH7750_BCR1_A7:
|
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s->bcr1 = mem_value; |
379 |
return;
|
380 |
case SH7750_BCR4_A7:
|
381 |
if(!has_bcr3_and_bcr4(s))
|
382 |
error_access("long write", addr);
|
383 |
s->bcr4 = mem_value; |
384 |
return;
|
385 |
case SH7750_WCR1_A7:
|
386 |
case SH7750_WCR2_A7:
|
387 |
case SH7750_WCR3_A7:
|
388 |
case SH7750_MCR_A7:
|
389 |
ignore_access("long write", addr);
|
390 |
return;
|
391 |
/* IO ports */
|
392 |
case SH7750_PCTRA_A7:
|
393 |
temp = porta_lines(s); |
394 |
s->pctra = mem_value; |
395 |
s->portdira = portdir(mem_value); |
396 |
s->portpullupa = portpullup(mem_value); |
397 |
porta_changed(s, temp); |
398 |
return;
|
399 |
case SH7750_PCTRB_A7:
|
400 |
temp = portb_lines(s); |
401 |
s->pctrb = mem_value; |
402 |
s->portdirb = portdir(mem_value); |
403 |
s->portpullupb = portpullup(mem_value); |
404 |
portb_changed(s, temp); |
405 |
return;
|
406 |
case SH7750_MMUCR_A7:
|
407 |
if (mem_value & MMUCR_TI) {
|
408 |
cpu_sh4_invalidate_tlb(s->cpu); |
409 |
} |
410 |
s->cpu->mmucr = mem_value & ~MMUCR_TI; |
411 |
return;
|
412 |
case SH7750_PTEH_A7:
|
413 |
/* If asid changes, clear all registered tlb entries. */
|
414 |
if ((s->cpu->pteh & 0xff) != (mem_value & 0xff)) |
415 |
tlb_flush(s->cpu, 1);
|
416 |
s->cpu->pteh = mem_value; |
417 |
return;
|
418 |
case SH7750_PTEL_A7:
|
419 |
s->cpu->ptel = mem_value; |
420 |
return;
|
421 |
case SH7750_PTEA_A7:
|
422 |
s->cpu->ptea = mem_value & 0x0000000f;
|
423 |
return;
|
424 |
case SH7750_TTB_A7:
|
425 |
s->cpu->ttb = mem_value; |
426 |
return;
|
427 |
case SH7750_TEA_A7:
|
428 |
s->cpu->tea = mem_value; |
429 |
return;
|
430 |
case SH7750_TRA_A7:
|
431 |
s->cpu->tra = mem_value & 0x000007ff;
|
432 |
return;
|
433 |
case SH7750_EXPEVT_A7:
|
434 |
s->cpu->expevt = mem_value & 0x000007ff;
|
435 |
return;
|
436 |
case SH7750_INTEVT_A7:
|
437 |
s->cpu->intevt = mem_value & 0x000007ff;
|
438 |
return;
|
439 |
case SH7750_CCR_A7:
|
440 |
s->ccr = mem_value; |
441 |
return;
|
442 |
default:
|
443 |
error_access("long write", addr);
|
444 |
abort(); |
445 |
} |
446 |
} |
447 |
|
448 |
static const MemoryRegionOps sh7750_mem_ops = { |
449 |
.old_mmio = { |
450 |
.read = {sh7750_mem_readb, |
451 |
sh7750_mem_readw, |
452 |
sh7750_mem_readl }, |
453 |
.write = {sh7750_mem_writeb, |
454 |
sh7750_mem_writew, |
455 |
sh7750_mem_writel }, |
456 |
}, |
457 |
.endianness = DEVICE_NATIVE_ENDIAN, |
458 |
}; |
459 |
|
460 |
/* sh775x interrupt controller tables for sh_intc.c
|
461 |
* stolen from linux/arch/sh/kernel/cpu/sh4/setup-sh7750.c
|
462 |
*/
|
463 |
|
464 |
enum {
|
465 |
UNUSED = 0,
|
466 |
|
467 |
/* interrupt sources */
|
468 |
IRL_0, IRL_1, IRL_2, IRL_3, IRL_4, IRL_5, IRL_6, IRL_7, |
469 |
IRL_8, IRL_9, IRL_A, IRL_B, IRL_C, IRL_D, IRL_E, |
470 |
IRL0, IRL1, IRL2, IRL3, |
471 |
HUDI, GPIOI, |
472 |
DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2, DMAC_DMTE3, |
473 |
DMAC_DMTE4, DMAC_DMTE5, DMAC_DMTE6, DMAC_DMTE7, |
474 |
DMAC_DMAE, |
475 |
PCIC0_PCISERR, PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON, |
476 |
PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2, PCIC1_PCIDMA3, |
477 |
TMU3, TMU4, TMU0, TMU1, TMU2_TUNI, TMU2_TICPI, |
478 |
RTC_ATI, RTC_PRI, RTC_CUI, |
479 |
SCI1_ERI, SCI1_RXI, SCI1_TXI, SCI1_TEI, |
480 |
SCIF_ERI, SCIF_RXI, SCIF_BRI, SCIF_TXI, |
481 |
WDT, |
482 |
REF_RCMI, REF_ROVI, |
483 |
|
484 |
/* interrupt groups */
|
485 |
DMAC, PCIC1, TMU2, RTC, SCI1, SCIF, REF, |
486 |
/* irl bundle */
|
487 |
IRL, |
488 |
|
489 |
NR_SOURCES, |
490 |
}; |
491 |
|
492 |
static struct intc_vect vectors[] = { |
493 |
INTC_VECT(HUDI, 0x600), INTC_VECT(GPIOI, 0x620), |
494 |
INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420), |
495 |
INTC_VECT(TMU2_TUNI, 0x440), INTC_VECT(TMU2_TICPI, 0x460), |
496 |
INTC_VECT(RTC_ATI, 0x480), INTC_VECT(RTC_PRI, 0x4a0), |
497 |
INTC_VECT(RTC_CUI, 0x4c0),
|
498 |
INTC_VECT(SCI1_ERI, 0x4e0), INTC_VECT(SCI1_RXI, 0x500), |
499 |
INTC_VECT(SCI1_TXI, 0x520), INTC_VECT(SCI1_TEI, 0x540), |
500 |
INTC_VECT(SCIF_ERI, 0x700), INTC_VECT(SCIF_RXI, 0x720), |
501 |
INTC_VECT(SCIF_BRI, 0x740), INTC_VECT(SCIF_TXI, 0x760), |
502 |
INTC_VECT(WDT, 0x560),
|
503 |
INTC_VECT(REF_RCMI, 0x580), INTC_VECT(REF_ROVI, 0x5a0), |
504 |
}; |
505 |
|
506 |
static struct intc_group groups[] = { |
507 |
INTC_GROUP(TMU2, TMU2_TUNI, TMU2_TICPI), |
508 |
INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI), |
509 |
INTC_GROUP(SCI1, SCI1_ERI, SCI1_RXI, SCI1_TXI, SCI1_TEI), |
510 |
INTC_GROUP(SCIF, SCIF_ERI, SCIF_RXI, SCIF_BRI, SCIF_TXI), |
511 |
INTC_GROUP(REF, REF_RCMI, REF_ROVI), |
512 |
}; |
513 |
|
514 |
static struct intc_prio_reg prio_registers[] = { |
515 |
{ 0xffd00004, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } }, |
516 |
{ 0xffd00008, 0, 16, 4, /* IPRB */ { WDT, REF, SCI1, 0 } }, |
517 |
{ 0xffd0000c, 0, 16, 4, /* IPRC */ { GPIOI, DMAC, SCIF, HUDI } }, |
518 |
{ 0xffd00010, 0, 16, 4, /* IPRD */ { IRL0, IRL1, IRL2, IRL3 } }, |
519 |
{ 0xfe080000, 0, 32, 4, /* INTPRI00 */ { 0, 0, 0, 0, |
520 |
TMU4, TMU3, |
521 |
PCIC1, PCIC0_PCISERR } }, |
522 |
}; |
523 |
|
524 |
/* SH7750, SH7750S, SH7751 and SH7091 all have 4-channel DMA controllers */
|
525 |
|
526 |
static struct intc_vect vectors_dma4[] = { |
527 |
INTC_VECT(DMAC_DMTE0, 0x640), INTC_VECT(DMAC_DMTE1, 0x660), |
528 |
INTC_VECT(DMAC_DMTE2, 0x680), INTC_VECT(DMAC_DMTE3, 0x6a0), |
529 |
INTC_VECT(DMAC_DMAE, 0x6c0),
|
530 |
}; |
531 |
|
532 |
static struct intc_group groups_dma4[] = { |
533 |
INTC_GROUP(DMAC, DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2, |
534 |
DMAC_DMTE3, DMAC_DMAE), |
535 |
}; |
536 |
|
537 |
/* SH7750R and SH7751R both have 8-channel DMA controllers */
|
538 |
|
539 |
static struct intc_vect vectors_dma8[] = { |
540 |
INTC_VECT(DMAC_DMTE0, 0x640), INTC_VECT(DMAC_DMTE1, 0x660), |
541 |
INTC_VECT(DMAC_DMTE2, 0x680), INTC_VECT(DMAC_DMTE3, 0x6a0), |
542 |
INTC_VECT(DMAC_DMTE4, 0x780), INTC_VECT(DMAC_DMTE5, 0x7a0), |
543 |
INTC_VECT(DMAC_DMTE6, 0x7c0), INTC_VECT(DMAC_DMTE7, 0x7e0), |
544 |
INTC_VECT(DMAC_DMAE, 0x6c0),
|
545 |
}; |
546 |
|
547 |
static struct intc_group groups_dma8[] = { |
548 |
INTC_GROUP(DMAC, DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2, |
549 |
DMAC_DMTE3, DMAC_DMTE4, DMAC_DMTE5, |
550 |
DMAC_DMTE6, DMAC_DMTE7, DMAC_DMAE), |
551 |
}; |
552 |
|
553 |
/* SH7750R, SH7751 and SH7751R all have two extra timer channels */
|
554 |
|
555 |
static struct intc_vect vectors_tmu34[] = { |
556 |
INTC_VECT(TMU3, 0xb00), INTC_VECT(TMU4, 0xb80), |
557 |
}; |
558 |
|
559 |
static struct intc_mask_reg mask_registers[] = { |
560 |
{ 0xfe080040, 0xfe080060, 32, /* INTMSK00 / INTMSKCLR00 */ |
561 |
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
562 |
0, 0, 0, 0, 0, 0, TMU4, TMU3, |
563 |
PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON, |
564 |
PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2, |
565 |
PCIC1_PCIDMA3, PCIC0_PCISERR } }, |
566 |
}; |
567 |
|
568 |
/* SH7750S, SH7750R, SH7751 and SH7751R all have IRLM priority registers */
|
569 |
|
570 |
static struct intc_vect vectors_irlm[] = { |
571 |
INTC_VECT(IRL0, 0x240), INTC_VECT(IRL1, 0x2a0), |
572 |
INTC_VECT(IRL2, 0x300), INTC_VECT(IRL3, 0x360), |
573 |
}; |
574 |
|
575 |
/* SH7751 and SH7751R both have PCI */
|
576 |
|
577 |
static struct intc_vect vectors_pci[] = { |
578 |
INTC_VECT(PCIC0_PCISERR, 0xa00), INTC_VECT(PCIC1_PCIERR, 0xae0), |
579 |
INTC_VECT(PCIC1_PCIPWDWN, 0xac0), INTC_VECT(PCIC1_PCIPWON, 0xaa0), |
580 |
INTC_VECT(PCIC1_PCIDMA0, 0xa80), INTC_VECT(PCIC1_PCIDMA1, 0xa60), |
581 |
INTC_VECT(PCIC1_PCIDMA2, 0xa40), INTC_VECT(PCIC1_PCIDMA3, 0xa20), |
582 |
}; |
583 |
|
584 |
static struct intc_group groups_pci[] = { |
585 |
INTC_GROUP(PCIC1, PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON, |
586 |
PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2, PCIC1_PCIDMA3), |
587 |
}; |
588 |
|
589 |
static struct intc_vect vectors_irl[] = { |
590 |
INTC_VECT(IRL_0, 0x200),
|
591 |
INTC_VECT(IRL_1, 0x220),
|
592 |
INTC_VECT(IRL_2, 0x240),
|
593 |
INTC_VECT(IRL_3, 0x260),
|
594 |
INTC_VECT(IRL_4, 0x280),
|
595 |
INTC_VECT(IRL_5, 0x2a0),
|
596 |
INTC_VECT(IRL_6, 0x2c0),
|
597 |
INTC_VECT(IRL_7, 0x2e0),
|
598 |
INTC_VECT(IRL_8, 0x300),
|
599 |
INTC_VECT(IRL_9, 0x320),
|
600 |
INTC_VECT(IRL_A, 0x340),
|
601 |
INTC_VECT(IRL_B, 0x360),
|
602 |
INTC_VECT(IRL_C, 0x380),
|
603 |
INTC_VECT(IRL_D, 0x3a0),
|
604 |
INTC_VECT(IRL_E, 0x3c0),
|
605 |
}; |
606 |
|
607 |
static struct intc_group groups_irl[] = { |
608 |
INTC_GROUP(IRL, IRL_0, IRL_1, IRL_2, IRL_3, IRL_4, IRL_5, IRL_6, |
609 |
IRL_7, IRL_8, IRL_9, IRL_A, IRL_B, IRL_C, IRL_D, IRL_E), |
610 |
}; |
611 |
|
612 |
/**********************************************************************
|
613 |
Memory mapped cache and TLB
|
614 |
**********************************************************************/
|
615 |
|
616 |
#define MM_REGION_MASK 0x07000000 |
617 |
#define MM_ICACHE_ADDR (0) |
618 |
#define MM_ICACHE_DATA (1) |
619 |
#define MM_ITLB_ADDR (2) |
620 |
#define MM_ITLB_DATA (3) |
621 |
#define MM_OCACHE_ADDR (4) |
622 |
#define MM_OCACHE_DATA (5) |
623 |
#define MM_UTLB_ADDR (6) |
624 |
#define MM_UTLB_DATA (7) |
625 |
#define MM_REGION_TYPE(addr) ((addr & MM_REGION_MASK) >> 24) |
626 |
|
627 |
static uint64_t invalid_read(void *opaque, target_phys_addr_t addr) |
628 |
{ |
629 |
abort(); |
630 |
|
631 |
return 0; |
632 |
} |
633 |
|
634 |
static uint64_t sh7750_mmct_read(void *opaque, target_phys_addr_t addr, |
635 |
unsigned size)
|
636 |
{ |
637 |
SH7750State *s = opaque; |
638 |
uint32_t ret = 0;
|
639 |
|
640 |
if (size != 4) { |
641 |
return invalid_read(opaque, addr);
|
642 |
} |
643 |
|
644 |
switch (MM_REGION_TYPE(addr)) {
|
645 |
case MM_ICACHE_ADDR:
|
646 |
case MM_ICACHE_DATA:
|
647 |
/* do nothing */
|
648 |
break;
|
649 |
case MM_ITLB_ADDR:
|
650 |
ret = cpu_sh4_read_mmaped_itlb_addr(s->cpu, addr); |
651 |
break;
|
652 |
case MM_ITLB_DATA:
|
653 |
ret = cpu_sh4_read_mmaped_itlb_data(s->cpu, addr); |
654 |
break;
|
655 |
case MM_OCACHE_ADDR:
|
656 |
case MM_OCACHE_DATA:
|
657 |
/* do nothing */
|
658 |
break;
|
659 |
case MM_UTLB_ADDR:
|
660 |
ret = cpu_sh4_read_mmaped_utlb_addr(s->cpu, addr); |
661 |
break;
|
662 |
case MM_UTLB_DATA:
|
663 |
ret = cpu_sh4_read_mmaped_utlb_data(s->cpu, addr); |
664 |
break;
|
665 |
default:
|
666 |
abort(); |
667 |
} |
668 |
|
669 |
return ret;
|
670 |
} |
671 |
|
672 |
static void invalid_write(void *opaque, target_phys_addr_t addr, |
673 |
uint64_t mem_value) |
674 |
{ |
675 |
abort(); |
676 |
} |
677 |
|
678 |
static void sh7750_mmct_write(void *opaque, target_phys_addr_t addr, |
679 |
uint64_t mem_value, unsigned size)
|
680 |
{ |
681 |
SH7750State *s = opaque; |
682 |
|
683 |
if (size != 4) { |
684 |
invalid_write(opaque, addr, mem_value); |
685 |
} |
686 |
|
687 |
switch (MM_REGION_TYPE(addr)) {
|
688 |
case MM_ICACHE_ADDR:
|
689 |
case MM_ICACHE_DATA:
|
690 |
/* do nothing */
|
691 |
break;
|
692 |
case MM_ITLB_ADDR:
|
693 |
cpu_sh4_write_mmaped_itlb_addr(s->cpu, addr, mem_value); |
694 |
break;
|
695 |
case MM_ITLB_DATA:
|
696 |
cpu_sh4_write_mmaped_itlb_data(s->cpu, addr, mem_value); |
697 |
abort(); |
698 |
break;
|
699 |
case MM_OCACHE_ADDR:
|
700 |
case MM_OCACHE_DATA:
|
701 |
/* do nothing */
|
702 |
break;
|
703 |
case MM_UTLB_ADDR:
|
704 |
cpu_sh4_write_mmaped_utlb_addr(s->cpu, addr, mem_value); |
705 |
break;
|
706 |
case MM_UTLB_DATA:
|
707 |
cpu_sh4_write_mmaped_utlb_data(s->cpu, addr, mem_value); |
708 |
break;
|
709 |
default:
|
710 |
abort(); |
711 |
break;
|
712 |
} |
713 |
} |
714 |
|
715 |
static const MemoryRegionOps sh7750_mmct_ops = { |
716 |
.read = sh7750_mmct_read, |
717 |
.write = sh7750_mmct_write, |
718 |
.endianness = DEVICE_NATIVE_ENDIAN, |
719 |
}; |
720 |
|
721 |
SH7750State *sh7750_init(CPUSH4State * cpu, MemoryRegion *sysmem) |
722 |
{ |
723 |
SH7750State *s; |
724 |
|
725 |
s = g_malloc0(sizeof(SH7750State));
|
726 |
s->cpu = cpu; |
727 |
s->periph_freq = 60000000; /* 60MHz */ |
728 |
memory_region_init_io(&s->iomem, &sh7750_mem_ops, s, |
729 |
"memory", 0x1fc01000); |
730 |
|
731 |
memory_region_init_alias(&s->iomem_1f0, "memory-1f0",
|
732 |
&s->iomem, 0x1f000000, 0x1000); |
733 |
memory_region_add_subregion(sysmem, 0x1f000000, &s->iomem_1f0);
|
734 |
|
735 |
memory_region_init_alias(&s->iomem_ff0, "memory-ff0",
|
736 |
&s->iomem, 0x1f000000, 0x1000); |
737 |
memory_region_add_subregion(sysmem, 0xff000000, &s->iomem_ff0);
|
738 |
|
739 |
memory_region_init_alias(&s->iomem_1f8, "memory-1f8",
|
740 |
&s->iomem, 0x1f800000, 0x1000); |
741 |
memory_region_add_subregion(sysmem, 0x1f800000, &s->iomem_1f8);
|
742 |
|
743 |
memory_region_init_alias(&s->iomem_ff8, "memory-ff8",
|
744 |
&s->iomem, 0x1f800000, 0x1000); |
745 |
memory_region_add_subregion(sysmem, 0xff800000, &s->iomem_ff8);
|
746 |
|
747 |
memory_region_init_alias(&s->iomem_1fc, "memory-1fc",
|
748 |
&s->iomem, 0x1fc00000, 0x1000); |
749 |
memory_region_add_subregion(sysmem, 0x1fc00000, &s->iomem_1fc);
|
750 |
|
751 |
memory_region_init_alias(&s->iomem_ffc, "memory-ffc",
|
752 |
&s->iomem, 0x1fc00000, 0x1000); |
753 |
memory_region_add_subregion(sysmem, 0xffc00000, &s->iomem_ffc);
|
754 |
|
755 |
memory_region_init_io(&s->mmct_iomem, &sh7750_mmct_ops, s, |
756 |
"cache-and-tlb", 0x08000000); |
757 |
memory_region_add_subregion(sysmem, 0xf0000000, &s->mmct_iomem);
|
758 |
|
759 |
sh_intc_init(sysmem, &s->intc, NR_SOURCES, |
760 |
_INTC_ARRAY(mask_registers), |
761 |
_INTC_ARRAY(prio_registers)); |
762 |
|
763 |
sh_intc_register_sources(&s->intc, |
764 |
_INTC_ARRAY(vectors), |
765 |
_INTC_ARRAY(groups)); |
766 |
|
767 |
cpu->intc_handle = &s->intc; |
768 |
|
769 |
sh_serial_init(sysmem, 0x1fe00000,
|
770 |
0, s->periph_freq, serial_hds[0], |
771 |
s->intc.irqs[SCI1_ERI], |
772 |
s->intc.irqs[SCI1_RXI], |
773 |
s->intc.irqs[SCI1_TXI], |
774 |
s->intc.irqs[SCI1_TEI], |
775 |
NULL);
|
776 |
sh_serial_init(sysmem, 0x1fe80000,
|
777 |
SH_SERIAL_FEAT_SCIF, |
778 |
s->periph_freq, serial_hds[1],
|
779 |
s->intc.irqs[SCIF_ERI], |
780 |
s->intc.irqs[SCIF_RXI], |
781 |
s->intc.irqs[SCIF_TXI], |
782 |
NULL,
|
783 |
s->intc.irqs[SCIF_BRI]); |
784 |
|
785 |
tmu012_init(sysmem, 0x1fd80000,
|
786 |
TMU012_FEAT_TOCR | TMU012_FEAT_3CHAN | TMU012_FEAT_EXTCLK, |
787 |
s->periph_freq, |
788 |
s->intc.irqs[TMU0], |
789 |
s->intc.irqs[TMU1], |
790 |
s->intc.irqs[TMU2_TUNI], |
791 |
s->intc.irqs[TMU2_TICPI]); |
792 |
|
793 |
if (cpu->id & (SH_CPU_SH7750 | SH_CPU_SH7750S | SH_CPU_SH7751)) {
|
794 |
sh_intc_register_sources(&s->intc, |
795 |
_INTC_ARRAY(vectors_dma4), |
796 |
_INTC_ARRAY(groups_dma4)); |
797 |
} |
798 |
|
799 |
if (cpu->id & (SH_CPU_SH7750R | SH_CPU_SH7751R)) {
|
800 |
sh_intc_register_sources(&s->intc, |
801 |
_INTC_ARRAY(vectors_dma8), |
802 |
_INTC_ARRAY(groups_dma8)); |
803 |
} |
804 |
|
805 |
if (cpu->id & (SH_CPU_SH7750R | SH_CPU_SH7751 | SH_CPU_SH7751R)) {
|
806 |
sh_intc_register_sources(&s->intc, |
807 |
_INTC_ARRAY(vectors_tmu34), |
808 |
NULL, 0); |
809 |
tmu012_init(sysmem, 0x1e100000, 0, s->periph_freq, |
810 |
s->intc.irqs[TMU3], |
811 |
s->intc.irqs[TMU4], |
812 |
NULL, NULL); |
813 |
} |
814 |
|
815 |
if (cpu->id & (SH_CPU_SH7751_ALL)) {
|
816 |
sh_intc_register_sources(&s->intc, |
817 |
_INTC_ARRAY(vectors_pci), |
818 |
_INTC_ARRAY(groups_pci)); |
819 |
} |
820 |
|
821 |
if (cpu->id & (SH_CPU_SH7750S | SH_CPU_SH7750R | SH_CPU_SH7751_ALL)) {
|
822 |
sh_intc_register_sources(&s->intc, |
823 |
_INTC_ARRAY(vectors_irlm), |
824 |
NULL, 0); |
825 |
} |
826 |
|
827 |
sh_intc_register_sources(&s->intc, |
828 |
_INTC_ARRAY(vectors_irl), |
829 |
_INTC_ARRAY(groups_irl)); |
830 |
return s;
|
831 |
} |
832 |
|
833 |
qemu_irq sh7750_irl(SH7750State *s) |
834 |
{ |
835 |
sh_intc_toggle_source(sh_intc_source(&s->intc, IRL), 1, 0); /* enable */ |
836 |
return qemu_allocate_irqs(sh_intc_set_irl, sh_intc_source(&s->intc, IRL),
|
837 |
1)[0]; |
838 |
} |