root / hw / usb-uhci.c @ 7165448a
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1 | bb36d470 | bellard | /*
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2 | bb36d470 | bellard | * USB UHCI controller emulation
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3 | 5fafdf24 | ths | *
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4 | bb36d470 | bellard | * Copyright (c) 2005 Fabrice Bellard
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5 | 5fafdf24 | ths | *
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6 | 54f254f9 | aliguori | * Copyright (c) 2008 Max Krasnyansky
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7 | 54f254f9 | aliguori | * Magor rewrite of the UHCI data structures parser and frame processor
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8 | 54f254f9 | aliguori | * Support for fully async operation and multiple outstanding transactions
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9 | 54f254f9 | aliguori | *
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10 | bb36d470 | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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11 | bb36d470 | bellard | * of this software and associated documentation files (the "Software"), to deal
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12 | bb36d470 | bellard | * in the Software without restriction, including without limitation the rights
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13 | bb36d470 | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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14 | bb36d470 | bellard | * copies of the Software, and to permit persons to whom the Software is
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15 | bb36d470 | bellard | * furnished to do so, subject to the following conditions:
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16 | bb36d470 | bellard | *
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17 | bb36d470 | bellard | * The above copyright notice and this permission notice shall be included in
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18 | bb36d470 | bellard | * all copies or substantial portions of the Software.
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19 | bb36d470 | bellard | *
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20 | bb36d470 | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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21 | bb36d470 | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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22 | bb36d470 | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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23 | bb36d470 | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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24 | bb36d470 | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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25 | bb36d470 | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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26 | bb36d470 | bellard | * THE SOFTWARE.
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27 | bb36d470 | bellard | */
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28 | 87ecb68b | pbrook | #include "hw.h" |
29 | 87ecb68b | pbrook | #include "usb.h" |
30 | 87ecb68b | pbrook | #include "pci.h" |
31 | 87ecb68b | pbrook | #include "qemu-timer.h" |
32 | 18e08a55 | Michael S. Tsirkin | #include "usb-uhci.h" |
33 | bb36d470 | bellard | |
34 | bb36d470 | bellard | //#define DEBUG
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35 | 54f254f9 | aliguori | //#define DEBUG_DUMP_DATA
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36 | bb36d470 | bellard | |
37 | 96217e31 | ths | #define UHCI_CMD_FGR (1 << 4) |
38 | 96217e31 | ths | #define UHCI_CMD_EGSM (1 << 3) |
39 | bb36d470 | bellard | #define UHCI_CMD_GRESET (1 << 2) |
40 | bb36d470 | bellard | #define UHCI_CMD_HCRESET (1 << 1) |
41 | bb36d470 | bellard | #define UHCI_CMD_RS (1 << 0) |
42 | bb36d470 | bellard | |
43 | bb36d470 | bellard | #define UHCI_STS_HCHALTED (1 << 5) |
44 | bb36d470 | bellard | #define UHCI_STS_HCPERR (1 << 4) |
45 | bb36d470 | bellard | #define UHCI_STS_HSERR (1 << 3) |
46 | bb36d470 | bellard | #define UHCI_STS_RD (1 << 2) |
47 | bb36d470 | bellard | #define UHCI_STS_USBERR (1 << 1) |
48 | bb36d470 | bellard | #define UHCI_STS_USBINT (1 << 0) |
49 | bb36d470 | bellard | |
50 | bb36d470 | bellard | #define TD_CTRL_SPD (1 << 29) |
51 | bb36d470 | bellard | #define TD_CTRL_ERROR_SHIFT 27 |
52 | bb36d470 | bellard | #define TD_CTRL_IOS (1 << 25) |
53 | bb36d470 | bellard | #define TD_CTRL_IOC (1 << 24) |
54 | bb36d470 | bellard | #define TD_CTRL_ACTIVE (1 << 23) |
55 | bb36d470 | bellard | #define TD_CTRL_STALL (1 << 22) |
56 | bb36d470 | bellard | #define TD_CTRL_BABBLE (1 << 20) |
57 | bb36d470 | bellard | #define TD_CTRL_NAK (1 << 19) |
58 | bb36d470 | bellard | #define TD_CTRL_TIMEOUT (1 << 18) |
59 | bb36d470 | bellard | |
60 | 9159f679 | Gerd Hoffmann | #define UHCI_PORT_SUSPEND (1 << 12) |
61 | bb36d470 | bellard | #define UHCI_PORT_RESET (1 << 9) |
62 | bb36d470 | bellard | #define UHCI_PORT_LSDA (1 << 8) |
63 | 9159f679 | Gerd Hoffmann | #define UHCI_PORT_RD (1 << 6) |
64 | bb36d470 | bellard | #define UHCI_PORT_ENC (1 << 3) |
65 | bb36d470 | bellard | #define UHCI_PORT_EN (1 << 2) |
66 | bb36d470 | bellard | #define UHCI_PORT_CSC (1 << 1) |
67 | bb36d470 | bellard | #define UHCI_PORT_CCS (1 << 0) |
68 | bb36d470 | bellard | |
69 | 9159f679 | Gerd Hoffmann | #define UHCI_PORT_READ_ONLY (0x1bb) |
70 | 9159f679 | Gerd Hoffmann | #define UHCI_PORT_WRITE_CLEAR (UHCI_PORT_CSC | UHCI_PORT_ENC)
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71 | 9159f679 | Gerd Hoffmann | |
72 | bb36d470 | bellard | #define FRAME_TIMER_FREQ 1000 |
73 | bb36d470 | bellard | |
74 | bb36d470 | bellard | #define FRAME_MAX_LOOPS 100 |
75 | bb36d470 | bellard | |
76 | bb36d470 | bellard | #define NB_PORTS 2 |
77 | bb36d470 | bellard | |
78 | 54f254f9 | aliguori | #ifdef DEBUG
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79 | d0f2c4c6 | malc | #define DPRINTF printf
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80 | 54f254f9 | aliguori | |
81 | 0bf9e31a | Blue Swirl | static const char *pid2str(int pid) |
82 | 54f254f9 | aliguori | { |
83 | 54f254f9 | aliguori | switch (pid) {
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84 | 54f254f9 | aliguori | case USB_TOKEN_SETUP: return "SETUP"; |
85 | 54f254f9 | aliguori | case USB_TOKEN_IN: return "IN"; |
86 | 54f254f9 | aliguori | case USB_TOKEN_OUT: return "OUT"; |
87 | 54f254f9 | aliguori | } |
88 | 54f254f9 | aliguori | return "?"; |
89 | 54f254f9 | aliguori | } |
90 | 54f254f9 | aliguori | |
91 | 54f254f9 | aliguori | #else
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92 | d0f2c4c6 | malc | #define DPRINTF(...)
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93 | 54f254f9 | aliguori | #endif
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94 | 54f254f9 | aliguori | |
95 | 54f254f9 | aliguori | #ifdef DEBUG_DUMP_DATA
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96 | 54f254f9 | aliguori | static void dump_data(const uint8_t *data, int len) |
97 | 54f254f9 | aliguori | { |
98 | 54f254f9 | aliguori | int i;
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99 | 54f254f9 | aliguori | |
100 | 54f254f9 | aliguori | printf("uhci: data: ");
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101 | 54f254f9 | aliguori | for(i = 0; i < len; i++) |
102 | 54f254f9 | aliguori | printf(" %02x", data[i]);
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103 | 54f254f9 | aliguori | printf("\n");
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104 | 54f254f9 | aliguori | } |
105 | 54f254f9 | aliguori | #else
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106 | 54f254f9 | aliguori | static void dump_data(const uint8_t *data, int len) {} |
107 | 54f254f9 | aliguori | #endif
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108 | 54f254f9 | aliguori | |
109 | 54f254f9 | aliguori | /*
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110 | 54f254f9 | aliguori | * Pending async transaction.
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111 | 54f254f9 | aliguori | * 'packet' must be the first field because completion
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112 | 54f254f9 | aliguori | * handler does "(UHCIAsync *) pkt" cast.
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113 | 54f254f9 | aliguori | */
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114 | 54f254f9 | aliguori | typedef struct UHCIAsync { |
115 | 54f254f9 | aliguori | USBPacket packet; |
116 | 54f254f9 | aliguori | struct UHCIAsync *next;
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117 | 54f254f9 | aliguori | uint32_t td; |
118 | 54f254f9 | aliguori | uint32_t token; |
119 | 54f254f9 | aliguori | int8_t valid; |
120 | 8e65b7c0 | David S. Ahern | uint8_t isoc; |
121 | 54f254f9 | aliguori | uint8_t done; |
122 | 54f254f9 | aliguori | uint8_t buffer[2048];
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123 | 54f254f9 | aliguori | } UHCIAsync; |
124 | 54f254f9 | aliguori | |
125 | bb36d470 | bellard | typedef struct UHCIPort { |
126 | bb36d470 | bellard | USBPort port; |
127 | bb36d470 | bellard | uint16_t ctrl; |
128 | bb36d470 | bellard | } UHCIPort; |
129 | bb36d470 | bellard | |
130 | bb36d470 | bellard | typedef struct UHCIState { |
131 | bb36d470 | bellard | PCIDevice dev; |
132 | b2317837 | Gerd Hoffmann | USBBus bus; |
133 | bb36d470 | bellard | uint16_t cmd; /* cmd register */
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134 | bb36d470 | bellard | uint16_t status; |
135 | bb36d470 | bellard | uint16_t intr; /* interrupt enable register */
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136 | bb36d470 | bellard | uint16_t frnum; /* frame number */
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137 | bb36d470 | bellard | uint32_t fl_base_addr; /* frame list base address */
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138 | bb36d470 | bellard | uint8_t sof_timing; |
139 | bb36d470 | bellard | uint8_t status2; /* bit 0 and 1 are used to generate UHCI_STS_USBINT */
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140 | 8e65b7c0 | David S. Ahern | int64_t expire_time; |
141 | bb36d470 | bellard | QEMUTimer *frame_timer; |
142 | bb36d470 | bellard | UHCIPort ports[NB_PORTS]; |
143 | 4d611c9a | pbrook | |
144 | 4d611c9a | pbrook | /* Interrupts that should be raised at the end of the current frame. */
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145 | 4d611c9a | pbrook | uint32_t pending_int_mask; |
146 | 54f254f9 | aliguori | |
147 | 54f254f9 | aliguori | /* Active packets */
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148 | 54f254f9 | aliguori | UHCIAsync *async_pending; |
149 | 54f254f9 | aliguori | UHCIAsync *async_pool; |
150 | 64e58fe5 | Juan Quintela | uint8_t num_ports_vmstate; |
151 | bb36d470 | bellard | } UHCIState; |
152 | bb36d470 | bellard | |
153 | bb36d470 | bellard | typedef struct UHCI_TD { |
154 | bb36d470 | bellard | uint32_t link; |
155 | bb36d470 | bellard | uint32_t ctrl; /* see TD_CTRL_xxx */
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156 | bb36d470 | bellard | uint32_t token; |
157 | bb36d470 | bellard | uint32_t buffer; |
158 | bb36d470 | bellard | } UHCI_TD; |
159 | bb36d470 | bellard | |
160 | bb36d470 | bellard | typedef struct UHCI_QH { |
161 | bb36d470 | bellard | uint32_t link; |
162 | bb36d470 | bellard | uint32_t el_link; |
163 | bb36d470 | bellard | } UHCI_QH; |
164 | bb36d470 | bellard | |
165 | 54f254f9 | aliguori | static UHCIAsync *uhci_async_alloc(UHCIState *s)
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166 | 54f254f9 | aliguori | { |
167 | 54f254f9 | aliguori | UHCIAsync *async = qemu_malloc(sizeof(UHCIAsync));
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168 | 487414f1 | aliguori | |
169 | 487414f1 | aliguori | memset(&async->packet, 0, sizeof(async->packet)); |
170 | 487414f1 | aliguori | async->valid = 0;
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171 | 487414f1 | aliguori | async->td = 0;
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172 | 487414f1 | aliguori | async->token = 0;
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173 | 487414f1 | aliguori | async->done = 0;
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174 | 8e65b7c0 | David S. Ahern | async->isoc = 0;
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175 | 487414f1 | aliguori | async->next = NULL;
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176 | 54f254f9 | aliguori | |
177 | 54f254f9 | aliguori | return async;
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178 | 54f254f9 | aliguori | } |
179 | 54f254f9 | aliguori | |
180 | 54f254f9 | aliguori | static void uhci_async_free(UHCIState *s, UHCIAsync *async) |
181 | 54f254f9 | aliguori | { |
182 | 54f254f9 | aliguori | qemu_free(async); |
183 | 54f254f9 | aliguori | } |
184 | 54f254f9 | aliguori | |
185 | 54f254f9 | aliguori | static void uhci_async_link(UHCIState *s, UHCIAsync *async) |
186 | 54f254f9 | aliguori | { |
187 | 54f254f9 | aliguori | async->next = s->async_pending; |
188 | 54f254f9 | aliguori | s->async_pending = async; |
189 | 54f254f9 | aliguori | } |
190 | 54f254f9 | aliguori | |
191 | 54f254f9 | aliguori | static void uhci_async_unlink(UHCIState *s, UHCIAsync *async) |
192 | 54f254f9 | aliguori | { |
193 | 54f254f9 | aliguori | UHCIAsync *curr = s->async_pending; |
194 | 54f254f9 | aliguori | UHCIAsync **prev = &s->async_pending; |
195 | 54f254f9 | aliguori | |
196 | 54f254f9 | aliguori | while (curr) {
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197 | 54f254f9 | aliguori | if (curr == async) {
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198 | 54f254f9 | aliguori | *prev = curr->next; |
199 | 54f254f9 | aliguori | return;
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200 | 54f254f9 | aliguori | } |
201 | 54f254f9 | aliguori | |
202 | 54f254f9 | aliguori | prev = &curr->next; |
203 | 54f254f9 | aliguori | curr = curr->next; |
204 | 54f254f9 | aliguori | } |
205 | 54f254f9 | aliguori | } |
206 | 54f254f9 | aliguori | |
207 | 54f254f9 | aliguori | static void uhci_async_cancel(UHCIState *s, UHCIAsync *async) |
208 | 54f254f9 | aliguori | { |
209 | d0f2c4c6 | malc | DPRINTF("uhci: cancel td 0x%x token 0x%x done %u\n",
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210 | 54f254f9 | aliguori | async->td, async->token, async->done); |
211 | 54f254f9 | aliguori | |
212 | 54f254f9 | aliguori | if (!async->done)
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213 | 54f254f9 | aliguori | usb_cancel_packet(&async->packet); |
214 | 54f254f9 | aliguori | uhci_async_free(s, async); |
215 | 54f254f9 | aliguori | } |
216 | 54f254f9 | aliguori | |
217 | 54f254f9 | aliguori | /*
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218 | 54f254f9 | aliguori | * Mark all outstanding async packets as invalid.
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219 | 54f254f9 | aliguori | * This is used for canceling them when TDs are removed by the HCD.
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220 | 54f254f9 | aliguori | */
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221 | 54f254f9 | aliguori | static UHCIAsync *uhci_async_validate_begin(UHCIState *s)
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222 | 54f254f9 | aliguori | { |
223 | 54f254f9 | aliguori | UHCIAsync *async = s->async_pending; |
224 | 54f254f9 | aliguori | |
225 | 54f254f9 | aliguori | while (async) {
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226 | 54f254f9 | aliguori | async->valid--; |
227 | 54f254f9 | aliguori | async = async->next; |
228 | 54f254f9 | aliguori | } |
229 | 54f254f9 | aliguori | return NULL; |
230 | 54f254f9 | aliguori | } |
231 | 54f254f9 | aliguori | |
232 | 54f254f9 | aliguori | /*
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233 | 54f254f9 | aliguori | * Cancel async packets that are no longer valid
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234 | 54f254f9 | aliguori | */
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235 | 54f254f9 | aliguori | static void uhci_async_validate_end(UHCIState *s) |
236 | 54f254f9 | aliguori | { |
237 | 54f254f9 | aliguori | UHCIAsync *curr = s->async_pending; |
238 | 54f254f9 | aliguori | UHCIAsync **prev = &s->async_pending; |
239 | 54f254f9 | aliguori | UHCIAsync *next; |
240 | 54f254f9 | aliguori | |
241 | 54f254f9 | aliguori | while (curr) {
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242 | 54f254f9 | aliguori | if (curr->valid > 0) { |
243 | 54f254f9 | aliguori | prev = &curr->next; |
244 | 54f254f9 | aliguori | curr = curr->next; |
245 | 54f254f9 | aliguori | continue;
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246 | 54f254f9 | aliguori | } |
247 | 54f254f9 | aliguori | |
248 | 54f254f9 | aliguori | next = curr->next; |
249 | 54f254f9 | aliguori | |
250 | 54f254f9 | aliguori | /* Unlink */
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251 | 54f254f9 | aliguori | *prev = next; |
252 | 54f254f9 | aliguori | |
253 | 54f254f9 | aliguori | uhci_async_cancel(s, curr); |
254 | 54f254f9 | aliguori | |
255 | 54f254f9 | aliguori | curr = next; |
256 | 54f254f9 | aliguori | } |
257 | 54f254f9 | aliguori | } |
258 | 54f254f9 | aliguori | |
259 | 54f254f9 | aliguori | static void uhci_async_cancel_all(UHCIState *s) |
260 | 54f254f9 | aliguori | { |
261 | 54f254f9 | aliguori | UHCIAsync *curr = s->async_pending; |
262 | 54f254f9 | aliguori | UHCIAsync *next; |
263 | 54f254f9 | aliguori | |
264 | 54f254f9 | aliguori | while (curr) {
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265 | 54f254f9 | aliguori | next = curr->next; |
266 | 54f254f9 | aliguori | |
267 | 54f254f9 | aliguori | uhci_async_cancel(s, curr); |
268 | 54f254f9 | aliguori | |
269 | 54f254f9 | aliguori | curr = next; |
270 | 54f254f9 | aliguori | } |
271 | 54f254f9 | aliguori | |
272 | 54f254f9 | aliguori | s->async_pending = NULL;
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273 | 54f254f9 | aliguori | } |
274 | 54f254f9 | aliguori | |
275 | 54f254f9 | aliguori | static UHCIAsync *uhci_async_find_td(UHCIState *s, uint32_t addr, uint32_t token)
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276 | 54f254f9 | aliguori | { |
277 | 54f254f9 | aliguori | UHCIAsync *async = s->async_pending; |
278 | e8ee3c72 | aurel32 | UHCIAsync *match = NULL;
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279 | e8ee3c72 | aurel32 | int count = 0; |
280 | e8ee3c72 | aurel32 | |
281 | e8ee3c72 | aurel32 | /*
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282 | e8ee3c72 | aurel32 | * We're looking for the best match here. ie both td addr and token.
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283 | e8ee3c72 | aurel32 | * Otherwise we return last good match. ie just token.
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284 | e8ee3c72 | aurel32 | * It's ok to match just token because it identifies the transaction
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285 | e8ee3c72 | aurel32 | * rather well, token includes: device addr, endpoint, size, etc.
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286 | e8ee3c72 | aurel32 | *
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287 | e8ee3c72 | aurel32 | * Also since we queue async transactions in reverse order by returning
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288 | e8ee3c72 | aurel32 | * last good match we restores the order.
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289 | e8ee3c72 | aurel32 | *
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290 | e8ee3c72 | aurel32 | * It's expected that we wont have a ton of outstanding transactions.
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291 | e8ee3c72 | aurel32 | * If we ever do we'd want to optimize this algorithm.
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292 | e8ee3c72 | aurel32 | */
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293 | 54f254f9 | aliguori | |
294 | 54f254f9 | aliguori | while (async) {
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295 | e8ee3c72 | aurel32 | if (async->token == token) {
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296 | e8ee3c72 | aurel32 | /* Good match */
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297 | e8ee3c72 | aurel32 | match = async; |
298 | e8ee3c72 | aurel32 | |
299 | e8ee3c72 | aurel32 | if (async->td == addr) {
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300 | e8ee3c72 | aurel32 | /* Best match */
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301 | e8ee3c72 | aurel32 | break;
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302 | 54f254f9 | aliguori | } |
303 | 54f254f9 | aliguori | } |
304 | 54f254f9 | aliguori | |
305 | 54f254f9 | aliguori | async = async->next; |
306 | e8ee3c72 | aurel32 | count++; |
307 | 54f254f9 | aliguori | } |
308 | e8ee3c72 | aurel32 | |
309 | e8ee3c72 | aurel32 | if (count > 64) |
310 | e8ee3c72 | aurel32 | fprintf(stderr, "uhci: warning lots of async transactions\n");
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311 | e8ee3c72 | aurel32 | |
312 | e8ee3c72 | aurel32 | return match;
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313 | 54f254f9 | aliguori | } |
314 | 54f254f9 | aliguori | |
315 | bb36d470 | bellard | static void uhci_update_irq(UHCIState *s) |
316 | bb36d470 | bellard | { |
317 | bb36d470 | bellard | int level;
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318 | bb36d470 | bellard | if (((s->status2 & 1) && (s->intr & (1 << 2))) || |
319 | bb36d470 | bellard | ((s->status2 & 2) && (s->intr & (1 << 3))) || |
320 | bb36d470 | bellard | ((s->status & UHCI_STS_USBERR) && (s->intr & (1 << 0))) || |
321 | bb36d470 | bellard | ((s->status & UHCI_STS_RD) && (s->intr & (1 << 1))) || |
322 | bb36d470 | bellard | (s->status & UHCI_STS_HSERR) || |
323 | bb36d470 | bellard | (s->status & UHCI_STS_HCPERR)) { |
324 | bb36d470 | bellard | level = 1;
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325 | bb36d470 | bellard | } else {
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326 | bb36d470 | bellard | level = 0;
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327 | bb36d470 | bellard | } |
328 | d537cf6c | pbrook | qemu_set_irq(s->dev.irq[3], level);
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329 | bb36d470 | bellard | } |
330 | bb36d470 | bellard | |
331 | c8075ac3 | Gleb Natapov | static void uhci_reset(void *opaque) |
332 | bb36d470 | bellard | { |
333 | c8075ac3 | Gleb Natapov | UHCIState *s = opaque; |
334 | bb36d470 | bellard | uint8_t *pci_conf; |
335 | bb36d470 | bellard | int i;
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336 | bb36d470 | bellard | UHCIPort *port; |
337 | bb36d470 | bellard | |
338 | d0f2c4c6 | malc | DPRINTF("uhci: full reset\n");
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339 | 6f382b5e | aliguori | |
340 | bb36d470 | bellard | pci_conf = s->dev.config; |
341 | bb36d470 | bellard | |
342 | bb36d470 | bellard | pci_conf[0x6a] = 0x01; /* usb clock */ |
343 | bb36d470 | bellard | pci_conf[0x6b] = 0x00; |
344 | bb36d470 | bellard | s->cmd = 0;
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345 | bb36d470 | bellard | s->status = 0;
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346 | bb36d470 | bellard | s->status2 = 0;
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347 | bb36d470 | bellard | s->intr = 0;
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348 | bb36d470 | bellard | s->fl_base_addr = 0;
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349 | bb36d470 | bellard | s->sof_timing = 64;
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350 | 54f254f9 | aliguori | |
351 | bb36d470 | bellard | for(i = 0; i < NB_PORTS; i++) { |
352 | bb36d470 | bellard | port = &s->ports[i]; |
353 | bb36d470 | bellard | port->ctrl = 0x0080;
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354 | 618c169b | Gerd Hoffmann | if (port->port.dev) {
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355 | 618c169b | Gerd Hoffmann | usb_attach(&port->port, port->port.dev); |
356 | 618c169b | Gerd Hoffmann | } |
357 | bb36d470 | bellard | } |
358 | 54f254f9 | aliguori | |
359 | 54f254f9 | aliguori | uhci_async_cancel_all(s); |
360 | bb36d470 | bellard | } |
361 | bb36d470 | bellard | |
362 | 817afc61 | Juan Quintela | static void uhci_pre_save(void *opaque) |
363 | b9dc033c | balrog | { |
364 | b9dc033c | balrog | UHCIState *s = opaque; |
365 | b9dc033c | balrog | |
366 | 6f382b5e | aliguori | uhci_async_cancel_all(s); |
367 | b9dc033c | balrog | } |
368 | b9dc033c | balrog | |
369 | 817afc61 | Juan Quintela | static const VMStateDescription vmstate_uhci_port = { |
370 | 817afc61 | Juan Quintela | .name = "uhci port",
|
371 | 817afc61 | Juan Quintela | .version_id = 1,
|
372 | 817afc61 | Juan Quintela | .minimum_version_id = 1,
|
373 | 817afc61 | Juan Quintela | .minimum_version_id_old = 1,
|
374 | 817afc61 | Juan Quintela | .fields = (VMStateField []) { |
375 | 817afc61 | Juan Quintela | VMSTATE_UINT16(ctrl, UHCIPort), |
376 | 817afc61 | Juan Quintela | VMSTATE_END_OF_LIST() |
377 | 817afc61 | Juan Quintela | } |
378 | 817afc61 | Juan Quintela | }; |
379 | 817afc61 | Juan Quintela | |
380 | 817afc61 | Juan Quintela | static const VMStateDescription vmstate_uhci = { |
381 | 817afc61 | Juan Quintela | .name = "uhci",
|
382 | 6881dd5f | TeLeMan | .version_id = 2,
|
383 | 817afc61 | Juan Quintela | .minimum_version_id = 1,
|
384 | 817afc61 | Juan Quintela | .minimum_version_id_old = 1,
|
385 | 817afc61 | Juan Quintela | .pre_save = uhci_pre_save, |
386 | 817afc61 | Juan Quintela | .fields = (VMStateField []) { |
387 | 817afc61 | Juan Quintela | VMSTATE_PCI_DEVICE(dev, UHCIState), |
388 | 817afc61 | Juan Quintela | VMSTATE_UINT8_EQUAL(num_ports_vmstate, UHCIState), |
389 | 817afc61 | Juan Quintela | VMSTATE_STRUCT_ARRAY(ports, UHCIState, NB_PORTS, 1,
|
390 | 817afc61 | Juan Quintela | vmstate_uhci_port, UHCIPort), |
391 | 817afc61 | Juan Quintela | VMSTATE_UINT16(cmd, UHCIState), |
392 | 817afc61 | Juan Quintela | VMSTATE_UINT16(status, UHCIState), |
393 | 817afc61 | Juan Quintela | VMSTATE_UINT16(intr, UHCIState), |
394 | 817afc61 | Juan Quintela | VMSTATE_UINT16(frnum, UHCIState), |
395 | 817afc61 | Juan Quintela | VMSTATE_UINT32(fl_base_addr, UHCIState), |
396 | 817afc61 | Juan Quintela | VMSTATE_UINT8(sof_timing, UHCIState), |
397 | 817afc61 | Juan Quintela | VMSTATE_UINT8(status2, UHCIState), |
398 | 817afc61 | Juan Quintela | VMSTATE_TIMER(frame_timer, UHCIState), |
399 | 6881dd5f | TeLeMan | VMSTATE_INT64_V(expire_time, UHCIState, 2),
|
400 | 817afc61 | Juan Quintela | VMSTATE_END_OF_LIST() |
401 | 817afc61 | Juan Quintela | } |
402 | 817afc61 | Juan Quintela | }; |
403 | b9dc033c | balrog | |
404 | bb36d470 | bellard | static void uhci_ioport_writeb(void *opaque, uint32_t addr, uint32_t val) |
405 | bb36d470 | bellard | { |
406 | bb36d470 | bellard | UHCIState *s = opaque; |
407 | 3b46e624 | ths | |
408 | bb36d470 | bellard | addr &= 0x1f;
|
409 | bb36d470 | bellard | switch(addr) {
|
410 | bb36d470 | bellard | case 0x0c: |
411 | bb36d470 | bellard | s->sof_timing = val; |
412 | bb36d470 | bellard | break;
|
413 | bb36d470 | bellard | } |
414 | bb36d470 | bellard | } |
415 | bb36d470 | bellard | |
416 | bb36d470 | bellard | static uint32_t uhci_ioport_readb(void *opaque, uint32_t addr) |
417 | bb36d470 | bellard | { |
418 | bb36d470 | bellard | UHCIState *s = opaque; |
419 | bb36d470 | bellard | uint32_t val; |
420 | bb36d470 | bellard | |
421 | bb36d470 | bellard | addr &= 0x1f;
|
422 | bb36d470 | bellard | switch(addr) {
|
423 | bb36d470 | bellard | case 0x0c: |
424 | bb36d470 | bellard | val = s->sof_timing; |
425 | d80cfb3f | pbrook | break;
|
426 | bb36d470 | bellard | default:
|
427 | bb36d470 | bellard | val = 0xff;
|
428 | bb36d470 | bellard | break;
|
429 | bb36d470 | bellard | } |
430 | bb36d470 | bellard | return val;
|
431 | bb36d470 | bellard | } |
432 | bb36d470 | bellard | |
433 | bb36d470 | bellard | static void uhci_ioport_writew(void *opaque, uint32_t addr, uint32_t val) |
434 | bb36d470 | bellard | { |
435 | bb36d470 | bellard | UHCIState *s = opaque; |
436 | 3b46e624 | ths | |
437 | bb36d470 | bellard | addr &= 0x1f;
|
438 | d0f2c4c6 | malc | DPRINTF("uhci: writew port=0x%04x val=0x%04x\n", addr, val);
|
439 | 54f254f9 | aliguori | |
440 | bb36d470 | bellard | switch(addr) {
|
441 | bb36d470 | bellard | case 0x00: |
442 | bb36d470 | bellard | if ((val & UHCI_CMD_RS) && !(s->cmd & UHCI_CMD_RS)) {
|
443 | bb36d470 | bellard | /* start frame processing */
|
444 | bb36d470 | bellard | qemu_mod_timer(s->frame_timer, qemu_get_clock(vm_clock)); |
445 | 52328140 | bellard | s->status &= ~UHCI_STS_HCHALTED; |
446 | 467d409f | bellard | } else if (!(val & UHCI_CMD_RS)) { |
447 | 52328140 | bellard | s->status |= UHCI_STS_HCHALTED; |
448 | bb36d470 | bellard | } |
449 | bb36d470 | bellard | if (val & UHCI_CMD_GRESET) {
|
450 | bb36d470 | bellard | UHCIPort *port; |
451 | bb36d470 | bellard | USBDevice *dev; |
452 | bb36d470 | bellard | int i;
|
453 | bb36d470 | bellard | |
454 | bb36d470 | bellard | /* send reset on the USB bus */
|
455 | bb36d470 | bellard | for(i = 0; i < NB_PORTS; i++) { |
456 | bb36d470 | bellard | port = &s->ports[i]; |
457 | a594cfbf | bellard | dev = port->port.dev; |
458 | bb36d470 | bellard | if (dev) {
|
459 | 4d611c9a | pbrook | usb_send_msg(dev, USB_MSG_RESET); |
460 | bb36d470 | bellard | } |
461 | bb36d470 | bellard | } |
462 | bb36d470 | bellard | uhci_reset(s); |
463 | bb36d470 | bellard | return;
|
464 | bb36d470 | bellard | } |
465 | 5e9ab4c4 | bellard | if (val & UHCI_CMD_HCRESET) {
|
466 | bb36d470 | bellard | uhci_reset(s); |
467 | bb36d470 | bellard | return;
|
468 | bb36d470 | bellard | } |
469 | bb36d470 | bellard | s->cmd = val; |
470 | bb36d470 | bellard | break;
|
471 | bb36d470 | bellard | case 0x02: |
472 | bb36d470 | bellard | s->status &= ~val; |
473 | bb36d470 | bellard | /* XXX: the chip spec is not coherent, so we add a hidden
|
474 | bb36d470 | bellard | register to distinguish between IOC and SPD */
|
475 | bb36d470 | bellard | if (val & UHCI_STS_USBINT)
|
476 | bb36d470 | bellard | s->status2 = 0;
|
477 | bb36d470 | bellard | uhci_update_irq(s); |
478 | bb36d470 | bellard | break;
|
479 | bb36d470 | bellard | case 0x04: |
480 | bb36d470 | bellard | s->intr = val; |
481 | bb36d470 | bellard | uhci_update_irq(s); |
482 | bb36d470 | bellard | break;
|
483 | bb36d470 | bellard | case 0x06: |
484 | bb36d470 | bellard | if (s->status & UHCI_STS_HCHALTED)
|
485 | bb36d470 | bellard | s->frnum = val & 0x7ff;
|
486 | bb36d470 | bellard | break;
|
487 | bb36d470 | bellard | case 0x10 ... 0x1f: |
488 | bb36d470 | bellard | { |
489 | bb36d470 | bellard | UHCIPort *port; |
490 | bb36d470 | bellard | USBDevice *dev; |
491 | bb36d470 | bellard | int n;
|
492 | bb36d470 | bellard | |
493 | bb36d470 | bellard | n = (addr >> 1) & 7; |
494 | bb36d470 | bellard | if (n >= NB_PORTS)
|
495 | bb36d470 | bellard | return;
|
496 | bb36d470 | bellard | port = &s->ports[n]; |
497 | a594cfbf | bellard | dev = port->port.dev; |
498 | bb36d470 | bellard | if (dev) {
|
499 | bb36d470 | bellard | /* port reset */
|
500 | 5fafdf24 | ths | if ( (val & UHCI_PORT_RESET) &&
|
501 | bb36d470 | bellard | !(port->ctrl & UHCI_PORT_RESET) ) { |
502 | 4d611c9a | pbrook | usb_send_msg(dev, USB_MSG_RESET); |
503 | bb36d470 | bellard | } |
504 | bb36d470 | bellard | } |
505 | 9159f679 | Gerd Hoffmann | port->ctrl &= UHCI_PORT_READ_ONLY; |
506 | 9159f679 | Gerd Hoffmann | port->ctrl |= (val & ~UHCI_PORT_READ_ONLY); |
507 | bb36d470 | bellard | /* some bits are reset when a '1' is written to them */
|
508 | 9159f679 | Gerd Hoffmann | port->ctrl &= ~(val & UHCI_PORT_WRITE_CLEAR); |
509 | bb36d470 | bellard | } |
510 | bb36d470 | bellard | break;
|
511 | bb36d470 | bellard | } |
512 | bb36d470 | bellard | } |
513 | bb36d470 | bellard | |
514 | bb36d470 | bellard | static uint32_t uhci_ioport_readw(void *opaque, uint32_t addr) |
515 | bb36d470 | bellard | { |
516 | bb36d470 | bellard | UHCIState *s = opaque; |
517 | bb36d470 | bellard | uint32_t val; |
518 | bb36d470 | bellard | |
519 | bb36d470 | bellard | addr &= 0x1f;
|
520 | bb36d470 | bellard | switch(addr) {
|
521 | bb36d470 | bellard | case 0x00: |
522 | bb36d470 | bellard | val = s->cmd; |
523 | bb36d470 | bellard | break;
|
524 | bb36d470 | bellard | case 0x02: |
525 | bb36d470 | bellard | val = s->status; |
526 | bb36d470 | bellard | break;
|
527 | bb36d470 | bellard | case 0x04: |
528 | bb36d470 | bellard | val = s->intr; |
529 | bb36d470 | bellard | break;
|
530 | bb36d470 | bellard | case 0x06: |
531 | bb36d470 | bellard | val = s->frnum; |
532 | bb36d470 | bellard | break;
|
533 | bb36d470 | bellard | case 0x10 ... 0x1f: |
534 | bb36d470 | bellard | { |
535 | bb36d470 | bellard | UHCIPort *port; |
536 | bb36d470 | bellard | int n;
|
537 | bb36d470 | bellard | n = (addr >> 1) & 7; |
538 | 5fafdf24 | ths | if (n >= NB_PORTS)
|
539 | bb36d470 | bellard | goto read_default;
|
540 | bb36d470 | bellard | port = &s->ports[n]; |
541 | bb36d470 | bellard | val = port->ctrl; |
542 | bb36d470 | bellard | } |
543 | bb36d470 | bellard | break;
|
544 | bb36d470 | bellard | default:
|
545 | bb36d470 | bellard | read_default:
|
546 | bb36d470 | bellard | val = 0xff7f; /* disabled port */ |
547 | bb36d470 | bellard | break;
|
548 | bb36d470 | bellard | } |
549 | 54f254f9 | aliguori | |
550 | d0f2c4c6 | malc | DPRINTF("uhci: readw port=0x%04x val=0x%04x\n", addr, val);
|
551 | 54f254f9 | aliguori | |
552 | bb36d470 | bellard | return val;
|
553 | bb36d470 | bellard | } |
554 | bb36d470 | bellard | |
555 | bb36d470 | bellard | static void uhci_ioport_writel(void *opaque, uint32_t addr, uint32_t val) |
556 | bb36d470 | bellard | { |
557 | bb36d470 | bellard | UHCIState *s = opaque; |
558 | bb36d470 | bellard | |
559 | bb36d470 | bellard | addr &= 0x1f;
|
560 | d0f2c4c6 | malc | DPRINTF("uhci: writel port=0x%04x val=0x%08x\n", addr, val);
|
561 | 54f254f9 | aliguori | |
562 | bb36d470 | bellard | switch(addr) {
|
563 | bb36d470 | bellard | case 0x08: |
564 | bb36d470 | bellard | s->fl_base_addr = val & ~0xfff;
|
565 | bb36d470 | bellard | break;
|
566 | bb36d470 | bellard | } |
567 | bb36d470 | bellard | } |
568 | bb36d470 | bellard | |
569 | bb36d470 | bellard | static uint32_t uhci_ioport_readl(void *opaque, uint32_t addr) |
570 | bb36d470 | bellard | { |
571 | bb36d470 | bellard | UHCIState *s = opaque; |
572 | bb36d470 | bellard | uint32_t val; |
573 | bb36d470 | bellard | |
574 | bb36d470 | bellard | addr &= 0x1f;
|
575 | bb36d470 | bellard | switch(addr) {
|
576 | bb36d470 | bellard | case 0x08: |
577 | bb36d470 | bellard | val = s->fl_base_addr; |
578 | bb36d470 | bellard | break;
|
579 | bb36d470 | bellard | default:
|
580 | bb36d470 | bellard | val = 0xffffffff;
|
581 | bb36d470 | bellard | break;
|
582 | bb36d470 | bellard | } |
583 | bb36d470 | bellard | return val;
|
584 | bb36d470 | bellard | } |
585 | bb36d470 | bellard | |
586 | 96217e31 | ths | /* signal resume if controller suspended */
|
587 | 96217e31 | ths | static void uhci_resume (void *opaque) |
588 | 96217e31 | ths | { |
589 | 96217e31 | ths | UHCIState *s = (UHCIState *)opaque; |
590 | 96217e31 | ths | |
591 | 96217e31 | ths | if (!s)
|
592 | 96217e31 | ths | return;
|
593 | 96217e31 | ths | |
594 | 96217e31 | ths | if (s->cmd & UHCI_CMD_EGSM) {
|
595 | 96217e31 | ths | s->cmd |= UHCI_CMD_FGR; |
596 | 96217e31 | ths | s->status |= UHCI_STS_RD; |
597 | 96217e31 | ths | uhci_update_irq(s); |
598 | 96217e31 | ths | } |
599 | 96217e31 | ths | } |
600 | 96217e31 | ths | |
601 | 618c169b | Gerd Hoffmann | static void uhci_attach(USBPort *port1) |
602 | bb36d470 | bellard | { |
603 | bb36d470 | bellard | UHCIState *s = port1->opaque; |
604 | bb36d470 | bellard | UHCIPort *port = &s->ports[port1->index]; |
605 | bb36d470 | bellard | |
606 | 618c169b | Gerd Hoffmann | /* set connect status */
|
607 | 618c169b | Gerd Hoffmann | port->ctrl |= UHCI_PORT_CCS | UHCI_PORT_CSC; |
608 | 61064870 | pbrook | |
609 | 618c169b | Gerd Hoffmann | /* update speed */
|
610 | 618c169b | Gerd Hoffmann | if (port->port.dev->speed == USB_SPEED_LOW) {
|
611 | 618c169b | Gerd Hoffmann | port->ctrl |= UHCI_PORT_LSDA; |
612 | bb36d470 | bellard | } else {
|
613 | 618c169b | Gerd Hoffmann | port->ctrl &= ~UHCI_PORT_LSDA; |
614 | 618c169b | Gerd Hoffmann | } |
615 | 96217e31 | ths | |
616 | 618c169b | Gerd Hoffmann | uhci_resume(s); |
617 | 618c169b | Gerd Hoffmann | } |
618 | 96217e31 | ths | |
619 | 618c169b | Gerd Hoffmann | static void uhci_detach(USBPort *port1) |
620 | 618c169b | Gerd Hoffmann | { |
621 | 618c169b | Gerd Hoffmann | UHCIState *s = port1->opaque; |
622 | 618c169b | Gerd Hoffmann | UHCIPort *port = &s->ports[port1->index]; |
623 | 618c169b | Gerd Hoffmann | |
624 | 618c169b | Gerd Hoffmann | /* set connect status */
|
625 | 618c169b | Gerd Hoffmann | if (port->ctrl & UHCI_PORT_CCS) {
|
626 | 618c169b | Gerd Hoffmann | port->ctrl &= ~UHCI_PORT_CCS; |
627 | 618c169b | Gerd Hoffmann | port->ctrl |= UHCI_PORT_CSC; |
628 | bb36d470 | bellard | } |
629 | 618c169b | Gerd Hoffmann | /* disable port */
|
630 | 618c169b | Gerd Hoffmann | if (port->ctrl & UHCI_PORT_EN) {
|
631 | 618c169b | Gerd Hoffmann | port->ctrl &= ~UHCI_PORT_EN; |
632 | 618c169b | Gerd Hoffmann | port->ctrl |= UHCI_PORT_ENC; |
633 | 618c169b | Gerd Hoffmann | } |
634 | 618c169b | Gerd Hoffmann | |
635 | 618c169b | Gerd Hoffmann | uhci_resume(s); |
636 | bb36d470 | bellard | } |
637 | bb36d470 | bellard | |
638 | 9159f679 | Gerd Hoffmann | static void uhci_wakeup(USBDevice *dev) |
639 | 9159f679 | Gerd Hoffmann | { |
640 | 9159f679 | Gerd Hoffmann | USBBus *bus = usb_bus_from_device(dev); |
641 | 9159f679 | Gerd Hoffmann | UHCIState *s = container_of(bus, UHCIState, bus); |
642 | 9159f679 | Gerd Hoffmann | UHCIPort *port = s->ports + dev->port->index; |
643 | 9159f679 | Gerd Hoffmann | |
644 | 9159f679 | Gerd Hoffmann | if (port->ctrl & UHCI_PORT_SUSPEND && !(port->ctrl & UHCI_PORT_RD)) {
|
645 | 9159f679 | Gerd Hoffmann | port->ctrl |= UHCI_PORT_RD; |
646 | 9159f679 | Gerd Hoffmann | uhci_resume(s); |
647 | 9159f679 | Gerd Hoffmann | } |
648 | 9159f679 | Gerd Hoffmann | } |
649 | 9159f679 | Gerd Hoffmann | |
650 | 4d611c9a | pbrook | static int uhci_broadcast_packet(UHCIState *s, USBPacket *p) |
651 | bb36d470 | bellard | { |
652 | bb36d470 | bellard | int i, ret;
|
653 | bb36d470 | bellard | |
654 | d0f2c4c6 | malc | DPRINTF("uhci: packet enter. pid %s addr 0x%02x ep %d len %d\n",
|
655 | 54f254f9 | aliguori | pid2str(p->pid), p->devaddr, p->devep, p->len); |
656 | 5d808245 | aurel32 | if (p->pid == USB_TOKEN_OUT || p->pid == USB_TOKEN_SETUP)
|
657 | 54f254f9 | aliguori | dump_data(p->data, p->len); |
658 | 54f254f9 | aliguori | |
659 | 54f254f9 | aliguori | ret = USB_RET_NODEV; |
660 | 54f254f9 | aliguori | for (i = 0; i < NB_PORTS && ret == USB_RET_NODEV; i++) { |
661 | 54f254f9 | aliguori | UHCIPort *port = &s->ports[i]; |
662 | 54f254f9 | aliguori | USBDevice *dev = port->port.dev; |
663 | 54f254f9 | aliguori | |
664 | 54f254f9 | aliguori | if (dev && (port->ctrl & UHCI_PORT_EN))
|
665 | 806b6024 | Gerd Hoffmann | ret = dev->info->handle_packet(dev, p); |
666 | bb36d470 | bellard | } |
667 | 54f254f9 | aliguori | |
668 | d0f2c4c6 | malc | DPRINTF("uhci: packet exit. ret %d len %d\n", ret, p->len);
|
669 | 54f254f9 | aliguori | if (p->pid == USB_TOKEN_IN && ret > 0) |
670 | 54f254f9 | aliguori | dump_data(p->data, ret); |
671 | 54f254f9 | aliguori | |
672 | 54f254f9 | aliguori | return ret;
|
673 | bb36d470 | bellard | } |
674 | bb36d470 | bellard | |
675 | 54f254f9 | aliguori | static void uhci_async_complete(USBPacket * packet, void *opaque); |
676 | 54f254f9 | aliguori | static void uhci_process_frame(UHCIState *s); |
677 | 4d611c9a | pbrook | |
678 | bb36d470 | bellard | /* return -1 if fatal error (frame must be stopped)
|
679 | bb36d470 | bellard | 0 if TD successful
|
680 | bb36d470 | bellard | 1 if TD unsuccessful or inactive
|
681 | bb36d470 | bellard | */
|
682 | 54f254f9 | aliguori | static int uhci_complete_td(UHCIState *s, UHCI_TD *td, UHCIAsync *async, uint32_t *int_mask) |
683 | bb36d470 | bellard | { |
684 | 54f254f9 | aliguori | int len = 0, max_len, err, ret; |
685 | bb36d470 | bellard | uint8_t pid; |
686 | bb36d470 | bellard | |
687 | 54f254f9 | aliguori | max_len = ((td->token >> 21) + 1) & 0x7ff; |
688 | 54f254f9 | aliguori | pid = td->token & 0xff;
|
689 | 54f254f9 | aliguori | |
690 | 54f254f9 | aliguori | ret = async->packet.len; |
691 | 54f254f9 | aliguori | |
692 | 54f254f9 | aliguori | if (td->ctrl & TD_CTRL_IOS)
|
693 | 54f254f9 | aliguori | td->ctrl &= ~TD_CTRL_ACTIVE; |
694 | bb36d470 | bellard | |
695 | 54f254f9 | aliguori | if (ret < 0) |
696 | 54f254f9 | aliguori | goto out;
|
697 | b9dc033c | balrog | |
698 | 54f254f9 | aliguori | len = async->packet.len; |
699 | 54f254f9 | aliguori | td->ctrl = (td->ctrl & ~0x7ff) | ((len - 1) & 0x7ff); |
700 | 54f254f9 | aliguori | |
701 | 54f254f9 | aliguori | /* The NAK bit may have been set by a previous frame, so clear it
|
702 | 54f254f9 | aliguori | here. The docs are somewhat unclear, but win2k relies on this
|
703 | 54f254f9 | aliguori | behavior. */
|
704 | 54f254f9 | aliguori | td->ctrl &= ~(TD_CTRL_ACTIVE | TD_CTRL_NAK); |
705 | 5bd2c0d7 | Paul Brook | if (td->ctrl & TD_CTRL_IOC)
|
706 | 5bd2c0d7 | Paul Brook | *int_mask |= 0x01;
|
707 | 54f254f9 | aliguori | |
708 | 54f254f9 | aliguori | if (pid == USB_TOKEN_IN) {
|
709 | 54f254f9 | aliguori | if (len > max_len) {
|
710 | 54f254f9 | aliguori | ret = USB_RET_BABBLE; |
711 | 54f254f9 | aliguori | goto out;
|
712 | 4d611c9a | pbrook | } |
713 | b9dc033c | balrog | |
714 | 54f254f9 | aliguori | if (len > 0) { |
715 | 54f254f9 | aliguori | /* write the data back */
|
716 | 54f254f9 | aliguori | cpu_physical_memory_write(td->buffer, async->buffer, len); |
717 | 54f254f9 | aliguori | } |
718 | 54f254f9 | aliguori | |
719 | 54f254f9 | aliguori | if ((td->ctrl & TD_CTRL_SPD) && len < max_len) {
|
720 | bb36d470 | bellard | *int_mask |= 0x02;
|
721 | bb36d470 | bellard | /* short packet: do not update QH */
|
722 | d0f2c4c6 | malc | DPRINTF("uhci: short packet. td 0x%x token 0x%x\n", async->td, async->token);
|
723 | bb36d470 | bellard | return 1; |
724 | bb36d470 | bellard | } |
725 | 54f254f9 | aliguori | } |
726 | 54f254f9 | aliguori | |
727 | 54f254f9 | aliguori | /* success */
|
728 | 54f254f9 | aliguori | return 0; |
729 | 54f254f9 | aliguori | |
730 | 54f254f9 | aliguori | out:
|
731 | 54f254f9 | aliguori | switch(ret) {
|
732 | 54f254f9 | aliguori | case USB_RET_STALL:
|
733 | 54f254f9 | aliguori | td->ctrl |= TD_CTRL_STALL; |
734 | 54f254f9 | aliguori | td->ctrl &= ~TD_CTRL_ACTIVE; |
735 | 54f254f9 | aliguori | return 1; |
736 | 54f254f9 | aliguori | |
737 | 54f254f9 | aliguori | case USB_RET_BABBLE:
|
738 | 54f254f9 | aliguori | td->ctrl |= TD_CTRL_BABBLE | TD_CTRL_STALL; |
739 | 54f254f9 | aliguori | td->ctrl &= ~TD_CTRL_ACTIVE; |
740 | 54f254f9 | aliguori | /* frame interrupted */
|
741 | 54f254f9 | aliguori | return -1; |
742 | 54f254f9 | aliguori | |
743 | 54f254f9 | aliguori | case USB_RET_NAK:
|
744 | 54f254f9 | aliguori | td->ctrl |= TD_CTRL_NAK; |
745 | 54f254f9 | aliguori | if (pid == USB_TOKEN_SETUP)
|
746 | 54f254f9 | aliguori | break;
|
747 | 54f254f9 | aliguori | return 1; |
748 | 54f254f9 | aliguori | |
749 | 54f254f9 | aliguori | case USB_RET_NODEV:
|
750 | 54f254f9 | aliguori | default:
|
751 | 54f254f9 | aliguori | break;
|
752 | 54f254f9 | aliguori | } |
753 | 54f254f9 | aliguori | |
754 | 54f254f9 | aliguori | /* Retry the TD if error count is not zero */
|
755 | 54f254f9 | aliguori | |
756 | 54f254f9 | aliguori | td->ctrl |= TD_CTRL_TIMEOUT; |
757 | 54f254f9 | aliguori | err = (td->ctrl >> TD_CTRL_ERROR_SHIFT) & 3;
|
758 | 54f254f9 | aliguori | if (err != 0) { |
759 | 54f254f9 | aliguori | err--; |
760 | 54f254f9 | aliguori | if (err == 0) { |
761 | bb36d470 | bellard | td->ctrl &= ~TD_CTRL_ACTIVE; |
762 | 54f254f9 | aliguori | s->status |= UHCI_STS_USBERR; |
763 | 5bd2c0d7 | Paul Brook | if (td->ctrl & TD_CTRL_IOC)
|
764 | 5bd2c0d7 | Paul Brook | *int_mask |= 0x01;
|
765 | 54f254f9 | aliguori | uhci_update_irq(s); |
766 | bb36d470 | bellard | } |
767 | bb36d470 | bellard | } |
768 | 54f254f9 | aliguori | td->ctrl = (td->ctrl & ~(3 << TD_CTRL_ERROR_SHIFT)) |
|
769 | 54f254f9 | aliguori | (err << TD_CTRL_ERROR_SHIFT); |
770 | 54f254f9 | aliguori | return 1; |
771 | bb36d470 | bellard | } |
772 | bb36d470 | bellard | |
773 | 54f254f9 | aliguori | static int uhci_handle_td(UHCIState *s, uint32_t addr, UHCI_TD *td, uint32_t *int_mask) |
774 | 54f254f9 | aliguori | { |
775 | 54f254f9 | aliguori | UHCIAsync *async; |
776 | 5d808245 | aurel32 | int len = 0, max_len; |
777 | 8e65b7c0 | David S. Ahern | uint8_t pid, isoc; |
778 | 8e65b7c0 | David S. Ahern | uint32_t token; |
779 | 54f254f9 | aliguori | |
780 | 54f254f9 | aliguori | /* Is active ? */
|
781 | 54f254f9 | aliguori | if (!(td->ctrl & TD_CTRL_ACTIVE))
|
782 | 54f254f9 | aliguori | return 1; |
783 | 54f254f9 | aliguori | |
784 | 8e65b7c0 | David S. Ahern | /* token field is not unique for isochronous requests,
|
785 | 8e65b7c0 | David S. Ahern | * so use the destination buffer
|
786 | 8e65b7c0 | David S. Ahern | */
|
787 | 8e65b7c0 | David S. Ahern | if (td->ctrl & TD_CTRL_IOS) {
|
788 | 8e65b7c0 | David S. Ahern | token = td->buffer; |
789 | 8e65b7c0 | David S. Ahern | isoc = 1;
|
790 | 8e65b7c0 | David S. Ahern | } else {
|
791 | 8e65b7c0 | David S. Ahern | token = td->token; |
792 | 8e65b7c0 | David S. Ahern | isoc = 0;
|
793 | 8e65b7c0 | David S. Ahern | } |
794 | 8e65b7c0 | David S. Ahern | |
795 | 8e65b7c0 | David S. Ahern | async = uhci_async_find_td(s, addr, token); |
796 | 54f254f9 | aliguori | if (async) {
|
797 | 54f254f9 | aliguori | /* Already submitted */
|
798 | a145ea51 | aliguori | async->valid = 32;
|
799 | 54f254f9 | aliguori | |
800 | 54f254f9 | aliguori | if (!async->done)
|
801 | 54f254f9 | aliguori | return 1; |
802 | 54f254f9 | aliguori | |
803 | 54f254f9 | aliguori | uhci_async_unlink(s, async); |
804 | 54f254f9 | aliguori | goto done;
|
805 | 54f254f9 | aliguori | } |
806 | 54f254f9 | aliguori | |
807 | 54f254f9 | aliguori | /* Allocate new packet */
|
808 | 54f254f9 | aliguori | async = uhci_async_alloc(s); |
809 | 54f254f9 | aliguori | if (!async)
|
810 | 54f254f9 | aliguori | return 1; |
811 | 54f254f9 | aliguori | |
812 | 8e65b7c0 | David S. Ahern | /* valid needs to be large enough to handle 10 frame delay
|
813 | 8e65b7c0 | David S. Ahern | * for initial isochronous requests
|
814 | 8e65b7c0 | David S. Ahern | */
|
815 | 8e65b7c0 | David S. Ahern | async->valid = 32;
|
816 | 54f254f9 | aliguori | async->td = addr; |
817 | 8e65b7c0 | David S. Ahern | async->token = token; |
818 | 8e65b7c0 | David S. Ahern | async->isoc = isoc; |
819 | 54f254f9 | aliguori | |
820 | 54f254f9 | aliguori | max_len = ((td->token >> 21) + 1) & 0x7ff; |
821 | 54f254f9 | aliguori | pid = td->token & 0xff;
|
822 | 54f254f9 | aliguori | |
823 | 54f254f9 | aliguori | async->packet.pid = pid; |
824 | 54f254f9 | aliguori | async->packet.devaddr = (td->token >> 8) & 0x7f; |
825 | 54f254f9 | aliguori | async->packet.devep = (td->token >> 15) & 0xf; |
826 | 54f254f9 | aliguori | async->packet.data = async->buffer; |
827 | 54f254f9 | aliguori | async->packet.len = max_len; |
828 | 54f254f9 | aliguori | async->packet.complete_cb = uhci_async_complete; |
829 | 54f254f9 | aliguori | async->packet.complete_opaque = s; |
830 | 54f254f9 | aliguori | |
831 | 54f254f9 | aliguori | switch(pid) {
|
832 | 54f254f9 | aliguori | case USB_TOKEN_OUT:
|
833 | 54f254f9 | aliguori | case USB_TOKEN_SETUP:
|
834 | 54f254f9 | aliguori | cpu_physical_memory_read(td->buffer, async->buffer, max_len); |
835 | 5d808245 | aurel32 | len = uhci_broadcast_packet(s, &async->packet); |
836 | 5d808245 | aurel32 | if (len >= 0) |
837 | 5d808245 | aurel32 | len = max_len; |
838 | 54f254f9 | aliguori | break;
|
839 | 54f254f9 | aliguori | |
840 | 54f254f9 | aliguori | case USB_TOKEN_IN:
|
841 | 5d808245 | aurel32 | len = uhci_broadcast_packet(s, &async->packet); |
842 | 54f254f9 | aliguori | break;
|
843 | 54f254f9 | aliguori | |
844 | 54f254f9 | aliguori | default:
|
845 | 54f254f9 | aliguori | /* invalid pid : frame interrupted */
|
846 | 54f254f9 | aliguori | uhci_async_free(s, async); |
847 | 54f254f9 | aliguori | s->status |= UHCI_STS_HCPERR; |
848 | 54f254f9 | aliguori | uhci_update_irq(s); |
849 | 54f254f9 | aliguori | return -1; |
850 | 54f254f9 | aliguori | } |
851 | 54f254f9 | aliguori | |
852 | 5d808245 | aurel32 | if (len == USB_RET_ASYNC) {
|
853 | 54f254f9 | aliguori | uhci_async_link(s, async); |
854 | 54f254f9 | aliguori | return 2; |
855 | 54f254f9 | aliguori | } |
856 | 54f254f9 | aliguori | |
857 | 5d808245 | aurel32 | async->packet.len = len; |
858 | 54f254f9 | aliguori | |
859 | 54f254f9 | aliguori | done:
|
860 | 5d808245 | aurel32 | len = uhci_complete_td(s, td, async, int_mask); |
861 | 54f254f9 | aliguori | uhci_async_free(s, async); |
862 | 5d808245 | aurel32 | return len;
|
863 | 54f254f9 | aliguori | } |
864 | 54f254f9 | aliguori | |
865 | 54f254f9 | aliguori | static void uhci_async_complete(USBPacket *packet, void *opaque) |
866 | 4d611c9a | pbrook | { |
867 | 4d611c9a | pbrook | UHCIState *s = opaque; |
868 | 54f254f9 | aliguori | UHCIAsync *async = (UHCIAsync *) packet; |
869 | 54f254f9 | aliguori | |
870 | d0f2c4c6 | malc | DPRINTF("uhci: async complete. td 0x%x token 0x%x\n", async->td, async->token);
|
871 | 54f254f9 | aliguori | |
872 | 8e65b7c0 | David S. Ahern | if (async->isoc) {
|
873 | 8e65b7c0 | David S. Ahern | UHCI_TD td; |
874 | 8e65b7c0 | David S. Ahern | uint32_t link = async->td; |
875 | 8e65b7c0 | David S. Ahern | uint32_t int_mask = 0, val;
|
876 | d4c4e6fd | Blue Swirl | |
877 | 8e65b7c0 | David S. Ahern | cpu_physical_memory_read(link & ~0xf, (uint8_t *) &td, sizeof(td)); |
878 | 8e65b7c0 | David S. Ahern | le32_to_cpus(&td.link); |
879 | 8e65b7c0 | David S. Ahern | le32_to_cpus(&td.ctrl); |
880 | 8e65b7c0 | David S. Ahern | le32_to_cpus(&td.token); |
881 | 8e65b7c0 | David S. Ahern | le32_to_cpus(&td.buffer); |
882 | 8e65b7c0 | David S. Ahern | |
883 | 8e65b7c0 | David S. Ahern | uhci_async_unlink(s, async); |
884 | d4c4e6fd | Blue Swirl | uhci_complete_td(s, &td, async, &int_mask); |
885 | 8e65b7c0 | David S. Ahern | s->pending_int_mask |= int_mask; |
886 | 54f254f9 | aliguori | |
887 | 8e65b7c0 | David S. Ahern | /* update the status bits of the TD */
|
888 | 8e65b7c0 | David S. Ahern | val = cpu_to_le32(td.ctrl); |
889 | 8e65b7c0 | David S. Ahern | cpu_physical_memory_write((link & ~0xf) + 4, |
890 | 8e65b7c0 | David S. Ahern | (const uint8_t *)&val, sizeof(val)); |
891 | 8e65b7c0 | David S. Ahern | uhci_async_free(s, async); |
892 | 8e65b7c0 | David S. Ahern | } else {
|
893 | 8e65b7c0 | David S. Ahern | async->done = 1;
|
894 | 8e65b7c0 | David S. Ahern | uhci_process_frame(s); |
895 | 8e65b7c0 | David S. Ahern | } |
896 | 54f254f9 | aliguori | } |
897 | 54f254f9 | aliguori | |
898 | 54f254f9 | aliguori | static int is_valid(uint32_t link) |
899 | 54f254f9 | aliguori | { |
900 | 54f254f9 | aliguori | return (link & 1) == 0; |
901 | 54f254f9 | aliguori | } |
902 | 54f254f9 | aliguori | |
903 | 54f254f9 | aliguori | static int is_qh(uint32_t link) |
904 | 54f254f9 | aliguori | { |
905 | 54f254f9 | aliguori | return (link & 2) != 0; |
906 | 54f254f9 | aliguori | } |
907 | 54f254f9 | aliguori | |
908 | 54f254f9 | aliguori | static int depth_first(uint32_t link) |
909 | 54f254f9 | aliguori | { |
910 | 54f254f9 | aliguori | return (link & 4) != 0; |
911 | 54f254f9 | aliguori | } |
912 | 54f254f9 | aliguori | |
913 | 54f254f9 | aliguori | /* QH DB used for detecting QH loops */
|
914 | 54f254f9 | aliguori | #define UHCI_MAX_QUEUES 128 |
915 | 54f254f9 | aliguori | typedef struct { |
916 | 54f254f9 | aliguori | uint32_t addr[UHCI_MAX_QUEUES]; |
917 | 54f254f9 | aliguori | int count;
|
918 | 54f254f9 | aliguori | } QhDb; |
919 | 54f254f9 | aliguori | |
920 | 54f254f9 | aliguori | static void qhdb_reset(QhDb *db) |
921 | 54f254f9 | aliguori | { |
922 | 54f254f9 | aliguori | db->count = 0;
|
923 | 54f254f9 | aliguori | } |
924 | 54f254f9 | aliguori | |
925 | 54f254f9 | aliguori | /* Add QH to DB. Returns 1 if already present or DB is full. */
|
926 | 54f254f9 | aliguori | static int qhdb_insert(QhDb *db, uint32_t addr) |
927 | 54f254f9 | aliguori | { |
928 | 54f254f9 | aliguori | int i;
|
929 | 54f254f9 | aliguori | for (i = 0; i < db->count; i++) |
930 | 54f254f9 | aliguori | if (db->addr[i] == addr)
|
931 | 54f254f9 | aliguori | return 1; |
932 | 54f254f9 | aliguori | |
933 | 54f254f9 | aliguori | if (db->count >= UHCI_MAX_QUEUES)
|
934 | 54f254f9 | aliguori | return 1; |
935 | 54f254f9 | aliguori | |
936 | 54f254f9 | aliguori | db->addr[db->count++] = addr; |
937 | 54f254f9 | aliguori | return 0; |
938 | 54f254f9 | aliguori | } |
939 | 54f254f9 | aliguori | |
940 | 54f254f9 | aliguori | static void uhci_process_frame(UHCIState *s) |
941 | 54f254f9 | aliguori | { |
942 | 54f254f9 | aliguori | uint32_t frame_addr, link, old_td_ctrl, val, int_mask; |
943 | 54f254f9 | aliguori | uint32_t curr_qh; |
944 | 54f254f9 | aliguori | int cnt, ret;
|
945 | 4d611c9a | pbrook | UHCI_TD td; |
946 | 54f254f9 | aliguori | UHCI_QH qh; |
947 | 54f254f9 | aliguori | QhDb qhdb; |
948 | 4d611c9a | pbrook | |
949 | 54f254f9 | aliguori | frame_addr = s->fl_base_addr + ((s->frnum & 0x3ff) << 2); |
950 | 54f254f9 | aliguori | |
951 | d0f2c4c6 | malc | DPRINTF("uhci: processing frame %d addr 0x%x\n" , s->frnum, frame_addr);
|
952 | 54f254f9 | aliguori | |
953 | 54f254f9 | aliguori | cpu_physical_memory_read(frame_addr, (uint8_t *)&link, 4);
|
954 | 54f254f9 | aliguori | le32_to_cpus(&link); |
955 | b9dc033c | balrog | |
956 | 54f254f9 | aliguori | int_mask = 0;
|
957 | 54f254f9 | aliguori | curr_qh = 0;
|
958 | 54f254f9 | aliguori | |
959 | 54f254f9 | aliguori | qhdb_reset(&qhdb); |
960 | 54f254f9 | aliguori | |
961 | 54f254f9 | aliguori | for (cnt = FRAME_MAX_LOOPS; is_valid(link) && cnt; cnt--) {
|
962 | 54f254f9 | aliguori | if (is_qh(link)) {
|
963 | 54f254f9 | aliguori | /* QH */
|
964 | 54f254f9 | aliguori | |
965 | 54f254f9 | aliguori | if (qhdb_insert(&qhdb, link)) {
|
966 | 54f254f9 | aliguori | /*
|
967 | 54f254f9 | aliguori | * We're going in circles. Which is not a bug because
|
968 | 54f254f9 | aliguori | * HCD is allowed to do that as part of the BW management.
|
969 | 54f254f9 | aliguori | * In our case though it makes no sense to spin here. Sync transations
|
970 | 54f254f9 | aliguori | * are already done, and async completion handler will re-process
|
971 | 54f254f9 | aliguori | * the frame when something is ready.
|
972 | 54f254f9 | aliguori | */
|
973 | d0f2c4c6 | malc | DPRINTF("uhci: detected loop. qh 0x%x\n", link);
|
974 | 54f254f9 | aliguori | break;
|
975 | 54f254f9 | aliguori | } |
976 | 54f254f9 | aliguori | |
977 | 54f254f9 | aliguori | cpu_physical_memory_read(link & ~0xf, (uint8_t *) &qh, sizeof(qh)); |
978 | 54f254f9 | aliguori | le32_to_cpus(&qh.link); |
979 | 54f254f9 | aliguori | le32_to_cpus(&qh.el_link); |
980 | 54f254f9 | aliguori | |
981 | d0f2c4c6 | malc | DPRINTF("uhci: QH 0x%x load. link 0x%x elink 0x%x\n",
|
982 | 54f254f9 | aliguori | link, qh.link, qh.el_link); |
983 | 54f254f9 | aliguori | |
984 | 54f254f9 | aliguori | if (!is_valid(qh.el_link)) {
|
985 | 54f254f9 | aliguori | /* QH w/o elements */
|
986 | 54f254f9 | aliguori | curr_qh = 0;
|
987 | 54f254f9 | aliguori | link = qh.link; |
988 | 54f254f9 | aliguori | } else {
|
989 | 54f254f9 | aliguori | /* QH with elements */
|
990 | 54f254f9 | aliguori | curr_qh = link; |
991 | 54f254f9 | aliguori | link = qh.el_link; |
992 | 54f254f9 | aliguori | } |
993 | 54f254f9 | aliguori | continue;
|
994 | 54f254f9 | aliguori | } |
995 | 54f254f9 | aliguori | |
996 | 54f254f9 | aliguori | /* TD */
|
997 | 54f254f9 | aliguori | cpu_physical_memory_read(link & ~0xf, (uint8_t *) &td, sizeof(td)); |
998 | b9dc033c | balrog | le32_to_cpus(&td.link); |
999 | b9dc033c | balrog | le32_to_cpus(&td.ctrl); |
1000 | b9dc033c | balrog | le32_to_cpus(&td.token); |
1001 | b9dc033c | balrog | le32_to_cpus(&td.buffer); |
1002 | b9dc033c | balrog | |
1003 | d0f2c4c6 | malc | DPRINTF("uhci: TD 0x%x load. link 0x%x ctrl 0x%x token 0x%x qh 0x%x\n",
|
1004 | 54f254f9 | aliguori | link, td.link, td.ctrl, td.token, curr_qh); |
1005 | 54f254f9 | aliguori | |
1006 | 54f254f9 | aliguori | old_td_ctrl = td.ctrl; |
1007 | 54f254f9 | aliguori | ret = uhci_handle_td(s, link, &td, &int_mask); |
1008 | b9dc033c | balrog | if (old_td_ctrl != td.ctrl) {
|
1009 | 54f254f9 | aliguori | /* update the status bits of the TD */
|
1010 | b9dc033c | balrog | val = cpu_to_le32(td.ctrl); |
1011 | b9dc033c | balrog | cpu_physical_memory_write((link & ~0xf) + 4, |
1012 | 54f254f9 | aliguori | (const uint8_t *)&val, sizeof(val)); |
1013 | b9dc033c | balrog | } |
1014 | 54f254f9 | aliguori | |
1015 | 54f254f9 | aliguori | if (ret < 0) { |
1016 | 54f254f9 | aliguori | /* interrupted frame */
|
1017 | 54f254f9 | aliguori | break;
|
1018 | b9dc033c | balrog | } |
1019 | b9dc033c | balrog | |
1020 | 54f254f9 | aliguori | if (ret == 2 || ret == 1) { |
1021 | d0f2c4c6 | malc | DPRINTF("uhci: TD 0x%x %s. link 0x%x ctrl 0x%x token 0x%x qh 0x%x\n",
|
1022 | 54f254f9 | aliguori | link, ret == 2 ? "pend" : "skip", |
1023 | 54f254f9 | aliguori | td.link, td.ctrl, td.token, curr_qh); |
1024 | b9dc033c | balrog | |
1025 | 54f254f9 | aliguori | link = curr_qh ? qh.link : td.link; |
1026 | 54f254f9 | aliguori | continue;
|
1027 | 4d611c9a | pbrook | } |
1028 | 54f254f9 | aliguori | |
1029 | 54f254f9 | aliguori | /* completed TD */
|
1030 | 54f254f9 | aliguori | |
1031 | d0f2c4c6 | malc | DPRINTF("uhci: TD 0x%x done. link 0x%x ctrl 0x%x token 0x%x qh 0x%x\n",
|
1032 | 54f254f9 | aliguori | link, td.link, td.ctrl, td.token, curr_qh); |
1033 | 54f254f9 | aliguori | |
1034 | 54f254f9 | aliguori | link = td.link; |
1035 | 54f254f9 | aliguori | |
1036 | 54f254f9 | aliguori | if (curr_qh) {
|
1037 | 54f254f9 | aliguori | /* update QH element link */
|
1038 | 54f254f9 | aliguori | qh.el_link = link; |
1039 | 4d611c9a | pbrook | val = cpu_to_le32(qh.el_link); |
1040 | 54f254f9 | aliguori | cpu_physical_memory_write((curr_qh & ~0xf) + 4, |
1041 | 54f254f9 | aliguori | (const uint8_t *)&val, sizeof(val)); |
1042 | 54f254f9 | aliguori | |
1043 | 54f254f9 | aliguori | if (!depth_first(link)) {
|
1044 | 54f254f9 | aliguori | /* done with this QH */
|
1045 | 54f254f9 | aliguori | |
1046 | d0f2c4c6 | malc | DPRINTF("uhci: QH 0x%x done. link 0x%x elink 0x%x\n",
|
1047 | 54f254f9 | aliguori | curr_qh, qh.link, qh.el_link); |
1048 | 54f254f9 | aliguori | |
1049 | 54f254f9 | aliguori | curr_qh = 0;
|
1050 | 54f254f9 | aliguori | link = qh.link; |
1051 | 54f254f9 | aliguori | } |
1052 | 4d611c9a | pbrook | } |
1053 | 54f254f9 | aliguori | |
1054 | 54f254f9 | aliguori | /* go to the next entry */
|
1055 | 4d611c9a | pbrook | } |
1056 | 54f254f9 | aliguori | |
1057 | 8e65b7c0 | David S. Ahern | s->pending_int_mask |= int_mask; |
1058 | 4d611c9a | pbrook | } |
1059 | 4d611c9a | pbrook | |
1060 | bb36d470 | bellard | static void uhci_frame_timer(void *opaque) |
1061 | bb36d470 | bellard | { |
1062 | bb36d470 | bellard | UHCIState *s = opaque; |
1063 | 8e65b7c0 | David S. Ahern | |
1064 | 8e65b7c0 | David S. Ahern | /* prepare the timer for the next frame */
|
1065 | 8e65b7c0 | David S. Ahern | s->expire_time += (get_ticks_per_sec() / FRAME_TIMER_FREQ); |
1066 | bb36d470 | bellard | |
1067 | bb36d470 | bellard | if (!(s->cmd & UHCI_CMD_RS)) {
|
1068 | 54f254f9 | aliguori | /* Full stop */
|
1069 | bb36d470 | bellard | qemu_del_timer(s->frame_timer); |
1070 | 52328140 | bellard | /* set hchalted bit in status - UHCI11D 2.1.2 */
|
1071 | 52328140 | bellard | s->status |= UHCI_STS_HCHALTED; |
1072 | 6f382b5e | aliguori | |
1073 | d0f2c4c6 | malc | DPRINTF("uhci: halted\n");
|
1074 | bb36d470 | bellard | return;
|
1075 | bb36d470 | bellard | } |
1076 | 54f254f9 | aliguori | |
1077 | 54f254f9 | aliguori | /* Complete the previous frame */
|
1078 | 4d611c9a | pbrook | if (s->pending_int_mask) {
|
1079 | 4d611c9a | pbrook | s->status2 |= s->pending_int_mask; |
1080 | 54f254f9 | aliguori | s->status |= UHCI_STS_USBINT; |
1081 | 4d611c9a | pbrook | uhci_update_irq(s); |
1082 | 4d611c9a | pbrook | } |
1083 | 8e65b7c0 | David S. Ahern | s->pending_int_mask = 0;
|
1084 | b9dc033c | balrog | |
1085 | 54f254f9 | aliguori | /* Start new frame */
|
1086 | 54f254f9 | aliguori | s->frnum = (s->frnum + 1) & 0x7ff; |
1087 | 54f254f9 | aliguori | |
1088 | d0f2c4c6 | malc | DPRINTF("uhci: new frame #%u\n" , s->frnum);
|
1089 | 54f254f9 | aliguori | |
1090 | 54f254f9 | aliguori | uhci_async_validate_begin(s); |
1091 | 54f254f9 | aliguori | |
1092 | 54f254f9 | aliguori | uhci_process_frame(s); |
1093 | 54f254f9 | aliguori | |
1094 | 54f254f9 | aliguori | uhci_async_validate_end(s); |
1095 | b9dc033c | balrog | |
1096 | 8e65b7c0 | David S. Ahern | qemu_mod_timer(s->frame_timer, s->expire_time); |
1097 | bb36d470 | bellard | } |
1098 | bb36d470 | bellard | |
1099 | 5fafdf24 | ths | static void uhci_map(PCIDevice *pci_dev, int region_num, |
1100 | 6e355d90 | Isaku Yamahata | pcibus_t addr, pcibus_t size, int type)
|
1101 | bb36d470 | bellard | { |
1102 | bb36d470 | bellard | UHCIState *s = (UHCIState *)pci_dev; |
1103 | bb36d470 | bellard | |
1104 | bb36d470 | bellard | register_ioport_write(addr, 32, 2, uhci_ioport_writew, s); |
1105 | bb36d470 | bellard | register_ioport_read(addr, 32, 2, uhci_ioport_readw, s); |
1106 | bb36d470 | bellard | register_ioport_write(addr, 32, 4, uhci_ioport_writel, s); |
1107 | bb36d470 | bellard | register_ioport_read(addr, 32, 4, uhci_ioport_readl, s); |
1108 | bb36d470 | bellard | register_ioport_write(addr, 32, 1, uhci_ioport_writeb, s); |
1109 | bb36d470 | bellard | register_ioport_read(addr, 32, 1, uhci_ioport_readb, s); |
1110 | bb36d470 | bellard | } |
1111 | bb36d470 | bellard | |
1112 | 0d86d2be | Gerd Hoffmann | static USBPortOps uhci_port_ops = {
|
1113 | 0d86d2be | Gerd Hoffmann | .attach = uhci_attach, |
1114 | 618c169b | Gerd Hoffmann | .detach = uhci_detach, |
1115 | 9159f679 | Gerd Hoffmann | .wakeup = uhci_wakeup, |
1116 | 0d86d2be | Gerd Hoffmann | }; |
1117 | 0d86d2be | Gerd Hoffmann | |
1118 | 6cf9b6f1 | Gerd Hoffmann | static int usb_uhci_common_initfn(UHCIState *s) |
1119 | bb36d470 | bellard | { |
1120 | 6cf9b6f1 | Gerd Hoffmann | uint8_t *pci_conf = s->dev.config; |
1121 | bb36d470 | bellard | int i;
|
1122 | bb36d470 | bellard | |
1123 | db579e9e | Michael S. Tsirkin | pci_conf[PCI_REVISION_ID] = 0x01; // revision number |
1124 | db579e9e | Michael S. Tsirkin | pci_conf[PCI_CLASS_PROG] = 0x00;
|
1125 | 173a543b | blueswir1 | pci_config_set_class(pci_conf, PCI_CLASS_SERIAL_USB); |
1126 | db579e9e | Michael S. Tsirkin | /* TODO: reset value should be 0. */
|
1127 | db579e9e | Michael S. Tsirkin | pci_conf[PCI_INTERRUPT_PIN] = 4; // interrupt pin 3 |
1128 | 38ca0f6d | pbrook | pci_conf[0x60] = 0x10; // release number |
1129 | 3b46e624 | ths | |
1130 | b2317837 | Gerd Hoffmann | usb_bus_new(&s->bus, &s->dev.qdev); |
1131 | bb36d470 | bellard | for(i = 0; i < NB_PORTS; i++) { |
1132 | ace1318b | Gerd Hoffmann | usb_register_port(&s->bus, &s->ports[i].port, s, i, &uhci_port_ops, |
1133 | 843d4e0c | Gerd Hoffmann | USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL); |
1134 | c7a2196a | Gerd Hoffmann | usb_port_location(&s->ports[i].port, NULL, i+1); |
1135 | bb36d470 | bellard | } |
1136 | bb36d470 | bellard | s->frame_timer = qemu_new_timer(vm_clock, uhci_frame_timer, s); |
1137 | 8e65b7c0 | David S. Ahern | s->expire_time = qemu_get_clock(vm_clock) + |
1138 | 8e65b7c0 | David S. Ahern | (get_ticks_per_sec() / FRAME_TIMER_FREQ); |
1139 | 64e58fe5 | Juan Quintela | s->num_ports_vmstate = NB_PORTS; |
1140 | bb36d470 | bellard | |
1141 | a08d4367 | Jan Kiszka | qemu_register_reset(uhci_reset, s); |
1142 | bb36d470 | bellard | |
1143 | 38ca0f6d | pbrook | /* Use region 4 for consistency with real hardware. BSD guests seem
|
1144 | 38ca0f6d | pbrook | to rely on this. */
|
1145 | 28c2c264 | Avi Kivity | pci_register_bar(&s->dev, 4, 0x20, |
1146 | 0392a017 | Isaku Yamahata | PCI_BASE_ADDRESS_SPACE_IO, uhci_map); |
1147 | 6f382b5e | aliguori | |
1148 | 6cf9b6f1 | Gerd Hoffmann | return 0; |
1149 | bb36d470 | bellard | } |
1150 | afcc3cdf | ths | |
1151 | 6cf9b6f1 | Gerd Hoffmann | static int usb_uhci_piix3_initfn(PCIDevice *dev) |
1152 | afcc3cdf | ths | { |
1153 | 6cf9b6f1 | Gerd Hoffmann | UHCIState *s = DO_UPCAST(UHCIState, dev, dev); |
1154 | 6cf9b6f1 | Gerd Hoffmann | uint8_t *pci_conf = s->dev.config; |
1155 | 6cf9b6f1 | Gerd Hoffmann | |
1156 | 6cf9b6f1 | Gerd Hoffmann | pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL); |
1157 | 6cf9b6f1 | Gerd Hoffmann | pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82371SB_2); |
1158 | 6cf9b6f1 | Gerd Hoffmann | return usb_uhci_common_initfn(s);
|
1159 | 6cf9b6f1 | Gerd Hoffmann | } |
1160 | 6cf9b6f1 | Gerd Hoffmann | |
1161 | 6cf9b6f1 | Gerd Hoffmann | static int usb_uhci_piix4_initfn(PCIDevice *dev) |
1162 | 6cf9b6f1 | Gerd Hoffmann | { |
1163 | 6cf9b6f1 | Gerd Hoffmann | UHCIState *s = DO_UPCAST(UHCIState, dev, dev); |
1164 | 6cf9b6f1 | Gerd Hoffmann | uint8_t *pci_conf = s->dev.config; |
1165 | afcc3cdf | ths | |
1166 | deb54399 | aliguori | pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL); |
1167 | deb54399 | aliguori | pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82371AB_2); |
1168 | 6cf9b6f1 | Gerd Hoffmann | return usb_uhci_common_initfn(s);
|
1169 | 6cf9b6f1 | Gerd Hoffmann | } |
1170 | afcc3cdf | ths | |
1171 | 30235a54 | Huacai Chen | static int usb_uhci_vt82c686b_initfn(PCIDevice *dev) |
1172 | 30235a54 | Huacai Chen | { |
1173 | 30235a54 | Huacai Chen | UHCIState *s = DO_UPCAST(UHCIState, dev, dev); |
1174 | 30235a54 | Huacai Chen | uint8_t *pci_conf = s->dev.config; |
1175 | 30235a54 | Huacai Chen | |
1176 | 30235a54 | Huacai Chen | pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_VIA); |
1177 | 30235a54 | Huacai Chen | pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_VIA_UHCI); |
1178 | 30235a54 | Huacai Chen | |
1179 | 30235a54 | Huacai Chen | /* USB misc control 1/2 */
|
1180 | 30235a54 | Huacai Chen | pci_set_long(pci_conf + 0x40,0x00001000); |
1181 | 30235a54 | Huacai Chen | /* PM capability */
|
1182 | 30235a54 | Huacai Chen | pci_set_long(pci_conf + 0x80,0x00020001); |
1183 | 30235a54 | Huacai Chen | /* USB legacy support */
|
1184 | 30235a54 | Huacai Chen | pci_set_long(pci_conf + 0xc0,0x00002000); |
1185 | 30235a54 | Huacai Chen | |
1186 | 30235a54 | Huacai Chen | return usb_uhci_common_initfn(s);
|
1187 | 30235a54 | Huacai Chen | } |
1188 | 30235a54 | Huacai Chen | |
1189 | 6cf9b6f1 | Gerd Hoffmann | static PCIDeviceInfo uhci_info[] = {
|
1190 | 6cf9b6f1 | Gerd Hoffmann | { |
1191 | 556cd098 | Markus Armbruster | .qdev.name = "piix3-usb-uhci",
|
1192 | 6cf9b6f1 | Gerd Hoffmann | .qdev.size = sizeof(UHCIState),
|
1193 | be73cfe2 | Juan Quintela | .qdev.vmsd = &vmstate_uhci, |
1194 | 6cf9b6f1 | Gerd Hoffmann | .init = usb_uhci_piix3_initfn, |
1195 | 6cf9b6f1 | Gerd Hoffmann | },{ |
1196 | 556cd098 | Markus Armbruster | .qdev.name = "piix4-usb-uhci",
|
1197 | 6cf9b6f1 | Gerd Hoffmann | .qdev.size = sizeof(UHCIState),
|
1198 | be73cfe2 | Juan Quintela | .qdev.vmsd = &vmstate_uhci, |
1199 | 6cf9b6f1 | Gerd Hoffmann | .init = usb_uhci_piix4_initfn, |
1200 | 6cf9b6f1 | Gerd Hoffmann | },{ |
1201 | 30235a54 | Huacai Chen | .qdev.name = "vt82c686b-usb-uhci",
|
1202 | 30235a54 | Huacai Chen | .qdev.size = sizeof(UHCIState),
|
1203 | 30235a54 | Huacai Chen | .qdev.vmsd = &vmstate_uhci, |
1204 | 30235a54 | Huacai Chen | .init = usb_uhci_vt82c686b_initfn, |
1205 | 30235a54 | Huacai Chen | },{ |
1206 | 6cf9b6f1 | Gerd Hoffmann | /* end of list */
|
1207 | afcc3cdf | ths | } |
1208 | 6cf9b6f1 | Gerd Hoffmann | }; |
1209 | afcc3cdf | ths | |
1210 | 6cf9b6f1 | Gerd Hoffmann | static void uhci_register(void) |
1211 | 6cf9b6f1 | Gerd Hoffmann | { |
1212 | 6cf9b6f1 | Gerd Hoffmann | pci_qdev_register_many(uhci_info); |
1213 | 6cf9b6f1 | Gerd Hoffmann | } |
1214 | 6cf9b6f1 | Gerd Hoffmann | device_init(uhci_register); |
1215 | afcc3cdf | ths | |
1216 | 6cf9b6f1 | Gerd Hoffmann | void usb_uhci_piix3_init(PCIBus *bus, int devfn) |
1217 | 6cf9b6f1 | Gerd Hoffmann | { |
1218 | 556cd098 | Markus Armbruster | pci_create_simple(bus, devfn, "piix3-usb-uhci");
|
1219 | 6cf9b6f1 | Gerd Hoffmann | } |
1220 | 54f254f9 | aliguori | |
1221 | 6cf9b6f1 | Gerd Hoffmann | void usb_uhci_piix4_init(PCIBus *bus, int devfn) |
1222 | 6cf9b6f1 | Gerd Hoffmann | { |
1223 | 556cd098 | Markus Armbruster | pci_create_simple(bus, devfn, "piix4-usb-uhci");
|
1224 | afcc3cdf | ths | } |
1225 | 30235a54 | Huacai Chen | |
1226 | 30235a54 | Huacai Chen | void usb_uhci_vt82c686b_init(PCIBus *bus, int devfn) |
1227 | 30235a54 | Huacai Chen | { |
1228 | 30235a54 | Huacai Chen | pci_create_simple(bus, devfn, "vt82c686b-usb-uhci");
|
1229 | 30235a54 | Huacai Chen | } |