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1 | dbda808a | bellard | /*
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2 | dbda808a | bellard | * OpenPIC emulation
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3 | dbda808a | bellard | *
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4 | dbda808a | bellard | * Copyright (c) 2004 Jocelyn Mayer
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5 | dbda808a | bellard | *
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6 | dbda808a | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | dbda808a | bellard | * of this software and associated documentation files (the "Software"), to deal
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8 | dbda808a | bellard | * in the Software without restriction, including without limitation the rights
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9 | dbda808a | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | dbda808a | bellard | * copies of the Software, and to permit persons to whom the Software is
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11 | dbda808a | bellard | * furnished to do so, subject to the following conditions:
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12 | dbda808a | bellard | *
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13 | dbda808a | bellard | * The above copyright notice and this permission notice shall be included in
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14 | dbda808a | bellard | * all copies or substantial portions of the Software.
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15 | dbda808a | bellard | *
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16 | dbda808a | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | dbda808a | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | dbda808a | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | dbda808a | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | dbda808a | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | dbda808a | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | dbda808a | bellard | * THE SOFTWARE.
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23 | dbda808a | bellard | */
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24 | dbda808a | bellard | /*
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25 | dbda808a | bellard | *
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26 | dbda808a | bellard | * Based on OpenPic implementations:
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27 | dbda808a | bellard | * - Intel GW80314 I/O compagnion chip developper's manual
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28 | dbda808a | bellard | * - Motorola MPC8245 & MPC8540 user manuals.
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29 | dbda808a | bellard | * - Motorola MCP750 (aka Raven) programmer manual.
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30 | dbda808a | bellard | * - Motorola Harrier programmer manuel
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31 | dbda808a | bellard | *
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32 | dbda808a | bellard | * Serial interrupts, as implemented in Raven chipset are not supported yet.
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33 | dbda808a | bellard | *
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34 | dbda808a | bellard | */
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35 | dbda808a | bellard | #include "vl.h" |
36 | dbda808a | bellard | |
37 | 611493d9 | bellard | //#define DEBUG_OPENPIC
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38 | dbda808a | bellard | |
39 | dbda808a | bellard | #ifdef DEBUG_OPENPIC
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40 | dbda808a | bellard | #define DPRINTF(fmt, args...) do { printf(fmt , ##args); } while (0) |
41 | dbda808a | bellard | #else
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42 | dbda808a | bellard | #define DPRINTF(fmt, args...) do { } while (0) |
43 | dbda808a | bellard | #endif
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44 | dbda808a | bellard | #define ERROR(fmr, args...) do { printf("ERROR: " fmr , ##args); } while (0) |
45 | dbda808a | bellard | |
46 | dbda808a | bellard | #define USE_MPCxxx /* Intel model is broken, for now */ |
47 | dbda808a | bellard | |
48 | dbda808a | bellard | #if defined (USE_INTEL_GW80314)
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49 | dbda808a | bellard | /* Intel GW80314 I/O Companion chip */
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50 | dbda808a | bellard | |
51 | dbda808a | bellard | #define MAX_CPU 4 |
52 | dbda808a | bellard | #define MAX_IRQ 32 |
53 | dbda808a | bellard | #define MAX_DBL 4 |
54 | dbda808a | bellard | #define MAX_MBX 4 |
55 | dbda808a | bellard | #define MAX_TMR 4 |
56 | dbda808a | bellard | #define VECTOR_BITS 8 |
57 | dbda808a | bellard | #define MAX_IPI 0 |
58 | dbda808a | bellard | |
59 | dbda808a | bellard | #define VID (0x00000000) |
60 | dbda808a | bellard | |
61 | dbda808a | bellard | #define OPENPIC_LITTLE_ENDIAN 1 |
62 | dbda808a | bellard | #define OPENPIC_BIG_ENDIAN 0 |
63 | dbda808a | bellard | |
64 | dbda808a | bellard | #elif defined(USE_MPCxxx)
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65 | dbda808a | bellard | |
66 | dbda808a | bellard | #define MAX_CPU 2 |
67 | dbda808a | bellard | #define MAX_IRQ 64 |
68 | 611493d9 | bellard | #define EXT_IRQ 48 |
69 | dbda808a | bellard | #define MAX_DBL 0 |
70 | dbda808a | bellard | #define MAX_MBX 0 |
71 | dbda808a | bellard | #define MAX_TMR 4 |
72 | dbda808a | bellard | #define VECTOR_BITS 8 |
73 | dbda808a | bellard | #define MAX_IPI 4 |
74 | dbda808a | bellard | #define VID 0x03 /* MPIC version ID */ |
75 | dbda808a | bellard | #define VENI 0x00000000 /* Vendor ID */ |
76 | dbda808a | bellard | |
77 | dbda808a | bellard | enum {
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78 | dbda808a | bellard | IRQ_IPVP = 0,
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79 | dbda808a | bellard | IRQ_IDE, |
80 | dbda808a | bellard | }; |
81 | dbda808a | bellard | |
82 | dbda808a | bellard | #define OPENPIC_LITTLE_ENDIAN 1 |
83 | dbda808a | bellard | #define OPENPIC_BIG_ENDIAN 0 |
84 | dbda808a | bellard | |
85 | dbda808a | bellard | #else
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86 | dbda808a | bellard | #error "Please select which OpenPic implementation is to be emulated" |
87 | dbda808a | bellard | #endif
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88 | dbda808a | bellard | |
89 | dbda808a | bellard | #if (OPENPIC_BIG_ENDIAN && !TARGET_WORDS_BIGENDIAN) || \
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90 | dbda808a | bellard | (OPENPIC_LITTLE_ENDIAN && TARGET_WORDS_BIGENDIAN) |
91 | dbda808a | bellard | #define OPENPIC_SWAP
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92 | dbda808a | bellard | #endif
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93 | dbda808a | bellard | |
94 | dbda808a | bellard | /* Interrupt definitions */
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95 | dbda808a | bellard | #define IRQ_FE (EXT_IRQ) /* Internal functional IRQ */ |
96 | dbda808a | bellard | #define IRQ_ERR (EXT_IRQ + 1) /* Error IRQ */ |
97 | dbda808a | bellard | #define IRQ_TIM0 (EXT_IRQ + 2) /* First timer IRQ */ |
98 | dbda808a | bellard | #if MAX_IPI > 0 |
99 | dbda808a | bellard | #define IRQ_IPI0 (IRQ_TIM0 + MAX_TMR) /* First IPI IRQ */ |
100 | dbda808a | bellard | #define IRQ_DBL0 (IRQ_IPI0 + (MAX_CPU * MAX_IPI)) /* First doorbell IRQ */ |
101 | dbda808a | bellard | #else
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102 | dbda808a | bellard | #define IRQ_DBL0 (IRQ_TIM0 + MAX_TMR) /* First doorbell IRQ */ |
103 | dbda808a | bellard | #define IRQ_MBX0 (IRQ_DBL0 + MAX_DBL) /* First mailbox IRQ */ |
104 | dbda808a | bellard | #endif
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105 | dbda808a | bellard | |
106 | dbda808a | bellard | #define BF_WIDTH(_bits_) \
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107 | dbda808a | bellard | (((_bits_) + (sizeof(uint32_t) * 8) - 1) / (sizeof(uint32_t) * 8)) |
108 | dbda808a | bellard | |
109 | dbda808a | bellard | static inline void set_bit (uint32_t *field, int bit) |
110 | dbda808a | bellard | { |
111 | dbda808a | bellard | field[bit >> 5] |= 1 << (bit & 0x1F); |
112 | dbda808a | bellard | } |
113 | dbda808a | bellard | |
114 | dbda808a | bellard | static inline void reset_bit (uint32_t *field, int bit) |
115 | dbda808a | bellard | { |
116 | dbda808a | bellard | field[bit >> 5] &= ~(1 << (bit & 0x1F)); |
117 | dbda808a | bellard | } |
118 | dbda808a | bellard | |
119 | dbda808a | bellard | static inline int test_bit (uint32_t *field, int bit) |
120 | dbda808a | bellard | { |
121 | dbda808a | bellard | return (field[bit >> 5] & 1 << (bit & 0x1F)) != 0; |
122 | dbda808a | bellard | } |
123 | dbda808a | bellard | |
124 | dbda808a | bellard | enum {
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125 | dbda808a | bellard | IRQ_EXTERNAL = 0x01,
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126 | dbda808a | bellard | IRQ_INTERNAL = 0x02,
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127 | dbda808a | bellard | IRQ_TIMER = 0x04,
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128 | dbda808a | bellard | IRQ_SPECIAL = 0x08,
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129 | dbda808a | bellard | } IRQ_src_type; |
130 | dbda808a | bellard | |
131 | dbda808a | bellard | typedef struct IRQ_queue_t { |
132 | dbda808a | bellard | uint32_t queue[BF_WIDTH(MAX_IRQ)]; |
133 | dbda808a | bellard | int next;
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134 | dbda808a | bellard | int priority;
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135 | dbda808a | bellard | } IRQ_queue_t; |
136 | dbda808a | bellard | |
137 | dbda808a | bellard | typedef struct IRQ_src_t { |
138 | dbda808a | bellard | uint32_t ipvp; /* IRQ vector/priority register */
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139 | dbda808a | bellard | uint32_t ide; /* IRQ destination register */
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140 | dbda808a | bellard | int type;
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141 | dbda808a | bellard | int last_cpu;
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142 | 611493d9 | bellard | int pending; /* TRUE if IRQ is pending */ |
143 | dbda808a | bellard | } IRQ_src_t; |
144 | dbda808a | bellard | |
145 | dbda808a | bellard | enum IPVP_bits {
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146 | dbda808a | bellard | IPVP_MASK = 31,
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147 | dbda808a | bellard | IPVP_ACTIVITY = 30,
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148 | dbda808a | bellard | IPVP_MODE = 29,
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149 | dbda808a | bellard | IPVP_POLARITY = 23,
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150 | dbda808a | bellard | IPVP_SENSE = 22,
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151 | dbda808a | bellard | }; |
152 | dbda808a | bellard | #define IPVP_PRIORITY_MASK (0x1F << 16) |
153 | 611493d9 | bellard | #define IPVP_PRIORITY(_ipvpr_) ((int)(((_ipvpr_) & IPVP_PRIORITY_MASK) >> 16)) |
154 | dbda808a | bellard | #define IPVP_VECTOR_MASK ((1 << VECTOR_BITS) - 1) |
155 | dbda808a | bellard | #define IPVP_VECTOR(_ipvpr_) ((_ipvpr_) & IPVP_VECTOR_MASK)
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156 | dbda808a | bellard | |
157 | dbda808a | bellard | typedef struct IRQ_dst_t { |
158 | dbda808a | bellard | uint32_t pctp; /* CPU current task priority */
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159 | dbda808a | bellard | uint32_t pcsr; /* CPU sensitivity register */
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160 | dbda808a | bellard | IRQ_queue_t raised; |
161 | dbda808a | bellard | IRQ_queue_t servicing; |
162 | dbda808a | bellard | CPUState *env; /* Needed if we did SMP */
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163 | dbda808a | bellard | } IRQ_dst_t; |
164 | dbda808a | bellard | |
165 | 611493d9 | bellard | struct openpic_t {
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166 | dbda808a | bellard | PCIDevice pci_dev; |
167 | 91d848eb | bellard | int mem_index;
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168 | dbda808a | bellard | /* Global registers */
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169 | dbda808a | bellard | uint32_t frep; /* Feature reporting register */
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170 | dbda808a | bellard | uint32_t glbc; /* Global configuration register */
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171 | dbda808a | bellard | uint32_t micr; /* MPIC interrupt configuration register */
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172 | dbda808a | bellard | uint32_t veni; /* Vendor identification register */
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173 | dbda808a | bellard | uint32_t spve; /* Spurious vector register */
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174 | dbda808a | bellard | uint32_t tifr; /* Timer frequency reporting register */
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175 | dbda808a | bellard | /* Source registers */
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176 | dbda808a | bellard | IRQ_src_t src[MAX_IRQ]; |
177 | dbda808a | bellard | /* Local registers per output pin */
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178 | dbda808a | bellard | IRQ_dst_t dst[MAX_CPU]; |
179 | dbda808a | bellard | int nb_cpus;
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180 | dbda808a | bellard | /* Timer registers */
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181 | dbda808a | bellard | struct {
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182 | dbda808a | bellard | uint32_t ticc; /* Global timer current count register */
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183 | dbda808a | bellard | uint32_t tibc; /* Global timer base count register */
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184 | dbda808a | bellard | } timers[MAX_TMR]; |
185 | dbda808a | bellard | #if MAX_DBL > 0 |
186 | dbda808a | bellard | /* Doorbell registers */
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187 | dbda808a | bellard | uint32_t dar; /* Doorbell activate register */
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188 | dbda808a | bellard | struct {
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189 | dbda808a | bellard | uint32_t dmr; /* Doorbell messaging register */
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190 | dbda808a | bellard | } doorbells[MAX_DBL]; |
191 | dbda808a | bellard | #endif
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192 | dbda808a | bellard | #if MAX_MBX > 0 |
193 | dbda808a | bellard | /* Mailbox registers */
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194 | dbda808a | bellard | struct {
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195 | dbda808a | bellard | uint32_t mbr; /* Mailbox register */
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196 | dbda808a | bellard | } mailboxes[MAX_MAILBOXES]; |
197 | dbda808a | bellard | #endif
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198 | 611493d9 | bellard | }; |
199 | dbda808a | bellard | |
200 | dbda808a | bellard | static inline void IRQ_setbit (IRQ_queue_t *q, int n_IRQ) |
201 | dbda808a | bellard | { |
202 | dbda808a | bellard | set_bit(q->queue, n_IRQ); |
203 | dbda808a | bellard | } |
204 | dbda808a | bellard | |
205 | dbda808a | bellard | static inline void IRQ_resetbit (IRQ_queue_t *q, int n_IRQ) |
206 | dbda808a | bellard | { |
207 | dbda808a | bellard | reset_bit(q->queue, n_IRQ); |
208 | dbda808a | bellard | } |
209 | dbda808a | bellard | |
210 | dbda808a | bellard | static inline int IRQ_testbit (IRQ_queue_t *q, int n_IRQ) |
211 | dbda808a | bellard | { |
212 | dbda808a | bellard | return test_bit(q->queue, n_IRQ);
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213 | dbda808a | bellard | } |
214 | dbda808a | bellard | |
215 | dbda808a | bellard | static void IRQ_check (openpic_t *opp, IRQ_queue_t *q) |
216 | dbda808a | bellard | { |
217 | dbda808a | bellard | int next, i;
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218 | dbda808a | bellard | int priority;
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219 | dbda808a | bellard | |
220 | dbda808a | bellard | next = -1;
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221 | dbda808a | bellard | priority = -1;
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222 | dbda808a | bellard | for (i = 0; i < MAX_IRQ; i++) { |
223 | dbda808a | bellard | if (IRQ_testbit(q, i)) {
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224 | 611493d9 | bellard | DPRINTF("IRQ_check: irq %d set ipvp_pr=%d pr=%d\n",
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225 | 611493d9 | bellard | i, IPVP_PRIORITY(opp->src[i].ipvp), priority); |
226 | dbda808a | bellard | if (IPVP_PRIORITY(opp->src[i].ipvp) > priority) {
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227 | dbda808a | bellard | next = i; |
228 | dbda808a | bellard | priority = IPVP_PRIORITY(opp->src[i].ipvp); |
229 | dbda808a | bellard | } |
230 | dbda808a | bellard | } |
231 | dbda808a | bellard | } |
232 | dbda808a | bellard | q->next = next; |
233 | dbda808a | bellard | q->priority = priority; |
234 | dbda808a | bellard | } |
235 | dbda808a | bellard | |
236 | dbda808a | bellard | static int IRQ_get_next (openpic_t *opp, IRQ_queue_t *q) |
237 | dbda808a | bellard | { |
238 | dbda808a | bellard | if (q->next == -1) { |
239 | 611493d9 | bellard | /* XXX: optimize */
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240 | dbda808a | bellard | IRQ_check(opp, q); |
241 | dbda808a | bellard | } |
242 | dbda808a | bellard | |
243 | dbda808a | bellard | return q->next;
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244 | dbda808a | bellard | } |
245 | dbda808a | bellard | |
246 | dbda808a | bellard | static void IRQ_local_pipe (openpic_t *opp, int n_CPU, int n_IRQ) |
247 | dbda808a | bellard | { |
248 | dbda808a | bellard | IRQ_dst_t *dst; |
249 | dbda808a | bellard | IRQ_src_t *src; |
250 | dbda808a | bellard | int priority;
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251 | dbda808a | bellard | |
252 | dbda808a | bellard | dst = &opp->dst[n_CPU]; |
253 | dbda808a | bellard | src = &opp->src[n_IRQ]; |
254 | dbda808a | bellard | priority = IPVP_PRIORITY(src->ipvp); |
255 | dbda808a | bellard | if (priority <= dst->pctp) {
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256 | dbda808a | bellard | /* Too low priority */
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257 | dbda808a | bellard | return;
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258 | dbda808a | bellard | } |
259 | dbda808a | bellard | if (IRQ_testbit(&dst->raised, n_IRQ)) {
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260 | dbda808a | bellard | /* Interrupt miss */
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261 | dbda808a | bellard | return;
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262 | dbda808a | bellard | } |
263 | dbda808a | bellard | set_bit(&src->ipvp, IPVP_ACTIVITY); |
264 | dbda808a | bellard | IRQ_setbit(&dst->raised, n_IRQ); |
265 | dbda808a | bellard | if (priority > dst->raised.priority) {
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266 | dbda808a | bellard | IRQ_get_next(opp, &dst->raised); |
267 | dbda808a | bellard | DPRINTF("Raise CPU IRQ\n");
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268 | dbda808a | bellard | cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HARD); |
269 | dbda808a | bellard | } |
270 | dbda808a | bellard | } |
271 | dbda808a | bellard | |
272 | 611493d9 | bellard | /* update pic state because registers for n_IRQ have changed value */
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273 | 611493d9 | bellard | static void openpic_update_irq(openpic_t *opp, int n_IRQ) |
274 | dbda808a | bellard | { |
275 | dbda808a | bellard | IRQ_src_t *src; |
276 | dbda808a | bellard | int i;
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277 | dbda808a | bellard | |
278 | dbda808a | bellard | src = &opp->src[n_IRQ]; |
279 | 611493d9 | bellard | |
280 | 611493d9 | bellard | if (!src->pending) {
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281 | 611493d9 | bellard | /* no irq pending */
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282 | 611493d9 | bellard | return;
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283 | 611493d9 | bellard | } |
284 | 611493d9 | bellard | if (test_bit(&src->ipvp, IPVP_MASK)) {
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285 | dbda808a | bellard | /* Interrupt source is disabled */
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286 | dbda808a | bellard | return;
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287 | dbda808a | bellard | } |
288 | dbda808a | bellard | if (IPVP_PRIORITY(src->ipvp) == 0) { |
289 | dbda808a | bellard | /* Priority set to zero */
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290 | dbda808a | bellard | return;
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291 | dbda808a | bellard | } |
292 | 611493d9 | bellard | if (test_bit(&src->ipvp, IPVP_ACTIVITY)) {
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293 | 611493d9 | bellard | /* IRQ already active */
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294 | 611493d9 | bellard | return;
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295 | 611493d9 | bellard | } |
296 | dbda808a | bellard | if (src->ide == 0x00000000) { |
297 | dbda808a | bellard | /* No target */
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298 | dbda808a | bellard | return;
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299 | dbda808a | bellard | } |
300 | 611493d9 | bellard | |
301 | 611493d9 | bellard | if (!test_bit(&src->ipvp, IPVP_MODE) ||
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302 | 611493d9 | bellard | src->ide == (1 << src->last_cpu)) {
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303 | 611493d9 | bellard | /* Directed delivery mode */
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304 | 611493d9 | bellard | for (i = 0; i < opp->nb_cpus; i++) { |
305 | 611493d9 | bellard | if (test_bit(&src->ide, i))
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306 | 611493d9 | bellard | IRQ_local_pipe(opp, i, n_IRQ); |
307 | 611493d9 | bellard | } |
308 | dbda808a | bellard | } else {
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309 | 611493d9 | bellard | /* Distributed delivery mode */
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310 | 611493d9 | bellard | /* XXX: incorrect code */
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311 | 611493d9 | bellard | for (i = src->last_cpu; i < src->last_cpu; i++) {
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312 | 611493d9 | bellard | if (i == MAX_IRQ)
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313 | 611493d9 | bellard | i = 0;
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314 | 611493d9 | bellard | if (test_bit(&src->ide, i)) {
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315 | 611493d9 | bellard | IRQ_local_pipe(opp, i, n_IRQ); |
316 | 611493d9 | bellard | src->last_cpu = i; |
317 | 611493d9 | bellard | break;
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318 | 611493d9 | bellard | } |
319 | 611493d9 | bellard | } |
320 | 611493d9 | bellard | } |
321 | 611493d9 | bellard | } |
322 | 611493d9 | bellard | |
323 | 611493d9 | bellard | void openpic_set_irq(openpic_t *opp, int n_IRQ, int level) |
324 | 611493d9 | bellard | { |
325 | 611493d9 | bellard | IRQ_src_t *src; |
326 | 611493d9 | bellard | |
327 | 611493d9 | bellard | src = &opp->src[n_IRQ]; |
328 | 611493d9 | bellard | DPRINTF("openpic: set irq %d = %d ipvp=%08x\n",
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329 | 611493d9 | bellard | n_IRQ, level, src->ipvp); |
330 | 611493d9 | bellard | if (test_bit(&src->ipvp, IPVP_SENSE)) {
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331 | 611493d9 | bellard | /* level-sensitive irq */
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332 | 611493d9 | bellard | src->pending = level; |
333 | 611493d9 | bellard | if (!level)
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334 | 611493d9 | bellard | reset_bit(&src->ipvp, IPVP_ACTIVITY); |
335 | 611493d9 | bellard | } else {
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336 | 611493d9 | bellard | /* edge-sensitive irq */
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337 | 611493d9 | bellard | if (level)
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338 | 611493d9 | bellard | src->pending = 1;
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339 | dbda808a | bellard | } |
340 | 611493d9 | bellard | openpic_update_irq(opp, n_IRQ); |
341 | dbda808a | bellard | } |
342 | dbda808a | bellard | |
343 | dbda808a | bellard | static void openpic_reset (openpic_t *opp) |
344 | dbda808a | bellard | { |
345 | dbda808a | bellard | int i;
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346 | dbda808a | bellard | |
347 | dbda808a | bellard | opp->glbc = 0x80000000;
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348 | f8407028 | bellard | /* Initialise controller registers */
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349 | dbda808a | bellard | opp->frep = ((EXT_IRQ - 1) << 16) | ((MAX_CPU - 1) << 8) | VID; |
350 | dbda808a | bellard | opp->veni = VENI; |
351 | dbda808a | bellard | opp->spve = 0x000000FF;
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352 | dbda808a | bellard | opp->tifr = 0x003F7A00;
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353 | dbda808a | bellard | /* ? */
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354 | dbda808a | bellard | opp->micr = 0x00000000;
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355 | dbda808a | bellard | /* Initialise IRQ sources */
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356 | dbda808a | bellard | for (i = 0; i < MAX_IRQ; i++) { |
357 | dbda808a | bellard | opp->src[i].ipvp = 0xA0000000;
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358 | dbda808a | bellard | opp->src[i].ide = 0x00000000;
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359 | dbda808a | bellard | } |
360 | dbda808a | bellard | /* Initialise IRQ destinations */
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361 | dbda808a | bellard | for (i = 0; i < opp->nb_cpus; i++) { |
362 | dbda808a | bellard | opp->dst[i].pctp = 0x0000000F;
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363 | dbda808a | bellard | opp->dst[i].pcsr = 0x00000000;
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364 | dbda808a | bellard | memset(&opp->dst[i].raised, 0, sizeof(IRQ_queue_t)); |
365 | dbda808a | bellard | memset(&opp->dst[i].servicing, 0, sizeof(IRQ_queue_t)); |
366 | dbda808a | bellard | } |
367 | dbda808a | bellard | /* Initialise timers */
|
368 | dbda808a | bellard | for (i = 0; i < MAX_TMR; i++) { |
369 | dbda808a | bellard | opp->timers[i].ticc = 0x00000000;
|
370 | dbda808a | bellard | opp->timers[i].tibc = 0x80000000;
|
371 | dbda808a | bellard | } |
372 | dbda808a | bellard | /* Initialise doorbells */
|
373 | dbda808a | bellard | #if MAX_DBL > 0 |
374 | dbda808a | bellard | opp->dar = 0x00000000;
|
375 | dbda808a | bellard | for (i = 0; i < MAX_DBL; i++) { |
376 | dbda808a | bellard | opp->doorbells[i].dmr = 0x00000000;
|
377 | dbda808a | bellard | } |
378 | dbda808a | bellard | #endif
|
379 | dbda808a | bellard | /* Initialise mailboxes */
|
380 | dbda808a | bellard | #if MAX_MBX > 0 |
381 | dbda808a | bellard | for (i = 0; i < MAX_MBX; i++) { /* ? */ |
382 | dbda808a | bellard | opp->mailboxes[i].mbr = 0x00000000;
|
383 | dbda808a | bellard | } |
384 | dbda808a | bellard | #endif
|
385 | dbda808a | bellard | /* Go out of RESET state */
|
386 | dbda808a | bellard | opp->glbc = 0x00000000;
|
387 | dbda808a | bellard | } |
388 | dbda808a | bellard | |
389 | dbda808a | bellard | static inline uint32_t read_IRQreg (openpic_t *opp, int n_IRQ, uint32_t reg) |
390 | dbda808a | bellard | { |
391 | dbda808a | bellard | uint32_t retval; |
392 | dbda808a | bellard | |
393 | dbda808a | bellard | switch (reg) {
|
394 | dbda808a | bellard | case IRQ_IPVP:
|
395 | dbda808a | bellard | retval = opp->src[n_IRQ].ipvp; |
396 | dbda808a | bellard | break;
|
397 | dbda808a | bellard | case IRQ_IDE:
|
398 | dbda808a | bellard | retval = opp->src[n_IRQ].ide; |
399 | dbda808a | bellard | break;
|
400 | dbda808a | bellard | } |
401 | dbda808a | bellard | |
402 | dbda808a | bellard | return retval;
|
403 | dbda808a | bellard | } |
404 | dbda808a | bellard | |
405 | dbda808a | bellard | static inline void write_IRQreg (openpic_t *opp, int n_IRQ, |
406 | dbda808a | bellard | uint32_t reg, uint32_t val) |
407 | dbda808a | bellard | { |
408 | dbda808a | bellard | uint32_t tmp; |
409 | dbda808a | bellard | |
410 | dbda808a | bellard | switch (reg) {
|
411 | dbda808a | bellard | case IRQ_IPVP:
|
412 | 611493d9 | bellard | /* NOTE: not fully accurate for special IRQs, but simple and
|
413 | 611493d9 | bellard | sufficient */
|
414 | 611493d9 | bellard | /* ACTIVITY bit is read-only */
|
415 | 611493d9 | bellard | opp->src[n_IRQ].ipvp = |
416 | 611493d9 | bellard | (opp->src[n_IRQ].ipvp & 0x40000000) |
|
417 | 611493d9 | bellard | (val & 0x800F00FF);
|
418 | 611493d9 | bellard | openpic_update_irq(opp, n_IRQ); |
419 | 611493d9 | bellard | DPRINTF("Set IPVP %d to 0x%08x -> 0x%08x\n",
|
420 | 611493d9 | bellard | n_IRQ, val, opp->src[n_IRQ].ipvp); |
421 | dbda808a | bellard | break;
|
422 | dbda808a | bellard | case IRQ_IDE:
|
423 | dbda808a | bellard | tmp = val & 0xC0000000;
|
424 | dbda808a | bellard | tmp |= val & ((1 << MAX_CPU) - 1); |
425 | dbda808a | bellard | opp->src[n_IRQ].ide = tmp; |
426 | dbda808a | bellard | DPRINTF("Set IDE %d to 0x%08x\n", n_IRQ, opp->src[n_IRQ].ide);
|
427 | dbda808a | bellard | break;
|
428 | dbda808a | bellard | } |
429 | dbda808a | bellard | } |
430 | dbda808a | bellard | |
431 | dbda808a | bellard | #if 0 // Code provision for Intel model
|
432 | dbda808a | bellard | #if MAX_DBL > 0
|
433 | dbda808a | bellard | static uint32_t read_doorbell_register (openpic_t *opp,
|
434 | dbda808a | bellard | int n_dbl, uint32_t offset)
|
435 | dbda808a | bellard | {
|
436 | dbda808a | bellard | uint32_t retval;
|
437 | dbda808a | bellard | |
438 | dbda808a | bellard | switch (offset) {
|
439 | dbda808a | bellard | case DBL_IPVP_OFFSET:
|
440 | dbda808a | bellard | retval = read_IRQreg(opp, IRQ_DBL0 + n_dbl, IRQ_IPVP);
|
441 | dbda808a | bellard | break;
|
442 | dbda808a | bellard | case DBL_IDE_OFFSET:
|
443 | dbda808a | bellard | retval = read_IRQreg(opp, IRQ_DBL0 + n_dbl, IRQ_IDE);
|
444 | dbda808a | bellard | break;
|
445 | dbda808a | bellard | case DBL_DMR_OFFSET:
|
446 | dbda808a | bellard | retval = opp->doorbells[n_dbl].dmr;
|
447 | dbda808a | bellard | break;
|
448 | dbda808a | bellard | }
|
449 | dbda808a | bellard | |
450 | dbda808a | bellard | return retval;
|
451 | dbda808a | bellard | }
|
452 | dbda808a | bellard |
|
453 | dbda808a | bellard | static void write_doorbell_register (penpic_t *opp, int n_dbl,
|
454 | dbda808a | bellard | uint32_t offset, uint32_t value)
|
455 | dbda808a | bellard | {
|
456 | dbda808a | bellard | switch (offset) {
|
457 | dbda808a | bellard | case DBL_IVPR_OFFSET:
|
458 | dbda808a | bellard | write_IRQreg(opp, IRQ_DBL0 + n_dbl, IRQ_IPVP, value);
|
459 | dbda808a | bellard | break;
|
460 | dbda808a | bellard | case DBL_IDE_OFFSET:
|
461 | dbda808a | bellard | write_IRQreg(opp, IRQ_DBL0 + n_dbl, IRQ_IDE, value);
|
462 | dbda808a | bellard | break;
|
463 | dbda808a | bellard | case DBL_DMR_OFFSET:
|
464 | dbda808a | bellard | opp->doorbells[n_dbl].dmr = value;
|
465 | dbda808a | bellard | break;
|
466 | dbda808a | bellard | }
|
467 | dbda808a | bellard | }
|
468 | dbda808a | bellard | #endif
|
469 | dbda808a | bellard | |
470 | dbda808a | bellard | #if MAX_MBX > 0 |
471 | dbda808a | bellard | static uint32_t read_mailbox_register (openpic_t *opp,
|
472 | dbda808a | bellard | int n_mbx, uint32_t offset)
|
473 | dbda808a | bellard | { |
474 | dbda808a | bellard | uint32_t retval; |
475 | dbda808a | bellard | |
476 | dbda808a | bellard | switch (offset) {
|
477 | dbda808a | bellard | case MBX_MBR_OFFSET:
|
478 | dbda808a | bellard | retval = opp->mailboxes[n_mbx].mbr; |
479 | dbda808a | bellard | break;
|
480 | dbda808a | bellard | case MBX_IVPR_OFFSET:
|
481 | dbda808a | bellard | retval = read_IRQreg(opp, IRQ_MBX0 + n_mbx, IRQ_IPVP); |
482 | dbda808a | bellard | break;
|
483 | dbda808a | bellard | case MBX_DMR_OFFSET:
|
484 | dbda808a | bellard | retval = read_IRQreg(opp, IRQ_MBX0 + n_mbx, IRQ_IDE); |
485 | dbda808a | bellard | break;
|
486 | dbda808a | bellard | } |
487 | dbda808a | bellard | |
488 | dbda808a | bellard | return retval;
|
489 | dbda808a | bellard | } |
490 | dbda808a | bellard | |
491 | dbda808a | bellard | static void write_mailbox_register (openpic_t *opp, int n_mbx, |
492 | dbda808a | bellard | uint32_t address, uint32_t value) |
493 | dbda808a | bellard | { |
494 | dbda808a | bellard | switch (offset) {
|
495 | dbda808a | bellard | case MBX_MBR_OFFSET:
|
496 | dbda808a | bellard | opp->mailboxes[n_mbx].mbr = value; |
497 | dbda808a | bellard | break;
|
498 | dbda808a | bellard | case MBX_IVPR_OFFSET:
|
499 | dbda808a | bellard | write_IRQreg(opp, IRQ_MBX0 + n_mbx, IRQ_IPVP, value); |
500 | dbda808a | bellard | break;
|
501 | dbda808a | bellard | case MBX_DMR_OFFSET:
|
502 | dbda808a | bellard | write_IRQreg(opp, IRQ_MBX0 + n_mbx, IRQ_IDE, value); |
503 | dbda808a | bellard | break;
|
504 | dbda808a | bellard | } |
505 | dbda808a | bellard | } |
506 | dbda808a | bellard | #endif
|
507 | dbda808a | bellard | #endif /* 0 : Code provision for Intel model */ |
508 | dbda808a | bellard | |
509 | dbda808a | bellard | static void openpic_gbl_write (void *opaque, uint32_t addr, uint32_t val) |
510 | dbda808a | bellard | { |
511 | dbda808a | bellard | openpic_t *opp = opaque; |
512 | dbda808a | bellard | |
513 | dbda808a | bellard | DPRINTF("%s: addr %08x <= %08x\n", __func__, addr, val);
|
514 | dbda808a | bellard | if (addr & 0xF) |
515 | dbda808a | bellard | return;
|
516 | dbda808a | bellard | #if defined OPENPIC_SWAP
|
517 | dbda808a | bellard | val = bswap32(val); |
518 | dbda808a | bellard | #endif
|
519 | dbda808a | bellard | addr &= 0xFF;
|
520 | dbda808a | bellard | switch (addr) {
|
521 | dbda808a | bellard | case 0x00: /* FREP */ |
522 | dbda808a | bellard | break;
|
523 | dbda808a | bellard | case 0x20: /* GLBC */ |
524 | dbda808a | bellard | if (val & 0x80000000) |
525 | dbda808a | bellard | openpic_reset(opp); |
526 | dbda808a | bellard | opp->glbc = val & ~0x80000000;
|
527 | dbda808a | bellard | break;
|
528 | dbda808a | bellard | case 0x80: /* VENI */ |
529 | dbda808a | bellard | break;
|
530 | dbda808a | bellard | case 0x90: /* PINT */ |
531 | dbda808a | bellard | /* XXX: Should be able to reset any CPU */
|
532 | dbda808a | bellard | if (val & 1) { |
533 | dbda808a | bellard | DPRINTF("Reset CPU IRQ\n");
|
534 | dbda808a | bellard | // cpu_interrupt(cpu_single_env, CPU_INTERRUPT_RESET);
|
535 | dbda808a | bellard | } |
536 | dbda808a | bellard | break;
|
537 | dbda808a | bellard | #if MAX_IPI > 0 |
538 | dbda808a | bellard | case 0xA0: /* IPI_IPVP */ |
539 | dbda808a | bellard | case 0xB0: |
540 | dbda808a | bellard | case 0xC0: |
541 | dbda808a | bellard | case 0xD0: |
542 | dbda808a | bellard | { |
543 | dbda808a | bellard | int idx;
|
544 | dbda808a | bellard | idx = (addr - 0xA0) >> 4; |
545 | dbda808a | bellard | write_IRQreg(opp, IRQ_IPI0 + idx, IRQ_IPVP, val); |
546 | dbda808a | bellard | } |
547 | dbda808a | bellard | break;
|
548 | dbda808a | bellard | #endif
|
549 | dbda808a | bellard | case 0xE0: /* SPVE */ |
550 | dbda808a | bellard | opp->spve = val & 0x000000FF;
|
551 | dbda808a | bellard | break;
|
552 | dbda808a | bellard | case 0xF0: /* TIFR */ |
553 | dbda808a | bellard | opp->tifr = val; |
554 | dbda808a | bellard | break;
|
555 | dbda808a | bellard | default:
|
556 | dbda808a | bellard | break;
|
557 | dbda808a | bellard | } |
558 | dbda808a | bellard | } |
559 | dbda808a | bellard | |
560 | dbda808a | bellard | static uint32_t openpic_gbl_read (void *opaque, uint32_t addr) |
561 | dbda808a | bellard | { |
562 | dbda808a | bellard | openpic_t *opp = opaque; |
563 | dbda808a | bellard | uint32_t retval; |
564 | dbda808a | bellard | |
565 | dbda808a | bellard | DPRINTF("%s: addr %08x\n", __func__, addr);
|
566 | dbda808a | bellard | retval = 0xFFFFFFFF;
|
567 | dbda808a | bellard | if (addr & 0xF) |
568 | dbda808a | bellard | return retval;
|
569 | dbda808a | bellard | addr &= 0xFF;
|
570 | dbda808a | bellard | switch (addr) {
|
571 | dbda808a | bellard | case 0x00: /* FREP */ |
572 | dbda808a | bellard | retval = opp->frep; |
573 | dbda808a | bellard | break;
|
574 | dbda808a | bellard | case 0x20: /* GLBC */ |
575 | dbda808a | bellard | retval = opp->glbc; |
576 | dbda808a | bellard | break;
|
577 | dbda808a | bellard | case 0x80: /* VENI */ |
578 | dbda808a | bellard | retval = opp->veni; |
579 | dbda808a | bellard | break;
|
580 | dbda808a | bellard | case 0x90: /* PINT */ |
581 | dbda808a | bellard | retval = 0x00000000;
|
582 | dbda808a | bellard | break;
|
583 | dbda808a | bellard | #if MAX_IPI > 0 |
584 | dbda808a | bellard | case 0xA0: /* IPI_IPVP */ |
585 | dbda808a | bellard | case 0xB0: |
586 | dbda808a | bellard | case 0xC0: |
587 | dbda808a | bellard | case 0xD0: |
588 | dbda808a | bellard | { |
589 | dbda808a | bellard | int idx;
|
590 | dbda808a | bellard | idx = (addr - 0xA0) >> 4; |
591 | dbda808a | bellard | retval = read_IRQreg(opp, IRQ_IPI0 + idx, IRQ_IPVP); |
592 | dbda808a | bellard | } |
593 | dbda808a | bellard | break;
|
594 | dbda808a | bellard | #endif
|
595 | dbda808a | bellard | case 0xE0: /* SPVE */ |
596 | dbda808a | bellard | retval = opp->spve; |
597 | dbda808a | bellard | break;
|
598 | dbda808a | bellard | case 0xF0: /* TIFR */ |
599 | dbda808a | bellard | retval = opp->tifr; |
600 | dbda808a | bellard | break;
|
601 | dbda808a | bellard | default:
|
602 | dbda808a | bellard | break;
|
603 | dbda808a | bellard | } |
604 | dbda808a | bellard | DPRINTF("%s: => %08x\n", __func__, retval);
|
605 | dbda808a | bellard | #if defined OPENPIC_SWAP
|
606 | dbda808a | bellard | retval = bswap32(retval); |
607 | dbda808a | bellard | #endif
|
608 | dbda808a | bellard | |
609 | dbda808a | bellard | return retval;
|
610 | dbda808a | bellard | } |
611 | dbda808a | bellard | |
612 | dbda808a | bellard | static void openpic_timer_write (void *opaque, uint32_t addr, uint32_t val) |
613 | dbda808a | bellard | { |
614 | dbda808a | bellard | openpic_t *opp = opaque; |
615 | dbda808a | bellard | int idx;
|
616 | dbda808a | bellard | |
617 | dbda808a | bellard | DPRINTF("%s: addr %08x <= %08x\n", __func__, addr, val);
|
618 | dbda808a | bellard | if (addr & 0xF) |
619 | dbda808a | bellard | return;
|
620 | dbda808a | bellard | #if defined OPENPIC_SWAP
|
621 | dbda808a | bellard | val = bswap32(val); |
622 | dbda808a | bellard | #endif
|
623 | dbda808a | bellard | addr -= 0x1100;
|
624 | dbda808a | bellard | addr &= 0xFFFF;
|
625 | dbda808a | bellard | idx = (addr & 0xFFF0) >> 6; |
626 | dbda808a | bellard | addr = addr & 0x30;
|
627 | dbda808a | bellard | switch (addr) {
|
628 | dbda808a | bellard | case 0x00: /* TICC */ |
629 | dbda808a | bellard | break;
|
630 | dbda808a | bellard | case 0x10: /* TIBC */ |
631 | dbda808a | bellard | if ((opp->timers[idx].ticc & 0x80000000) != 0 && |
632 | 8adbc566 | bellard | (val & 0x80000000) == 0 && |
633 | dbda808a | bellard | (opp->timers[idx].tibc & 0x80000000) != 0) |
634 | dbda808a | bellard | opp->timers[idx].ticc &= ~0x80000000;
|
635 | dbda808a | bellard | opp->timers[idx].tibc = val; |
636 | dbda808a | bellard | break;
|
637 | dbda808a | bellard | case 0x20: /* TIVP */ |
638 | dbda808a | bellard | write_IRQreg(opp, IRQ_TIM0 + idx, IRQ_IPVP, val); |
639 | dbda808a | bellard | break;
|
640 | dbda808a | bellard | case 0x30: /* TIDE */ |
641 | dbda808a | bellard | write_IRQreg(opp, IRQ_TIM0 + idx, IRQ_IDE, val); |
642 | dbda808a | bellard | break;
|
643 | dbda808a | bellard | } |
644 | dbda808a | bellard | } |
645 | dbda808a | bellard | |
646 | dbda808a | bellard | static uint32_t openpic_timer_read (void *opaque, uint32_t addr) |
647 | dbda808a | bellard | { |
648 | dbda808a | bellard | openpic_t *opp = opaque; |
649 | dbda808a | bellard | uint32_t retval; |
650 | dbda808a | bellard | int idx;
|
651 | dbda808a | bellard | |
652 | dbda808a | bellard | DPRINTF("%s: addr %08x\n", __func__, addr);
|
653 | dbda808a | bellard | retval = 0xFFFFFFFF;
|
654 | dbda808a | bellard | if (addr & 0xF) |
655 | dbda808a | bellard | return retval;
|
656 | dbda808a | bellard | addr -= 0x1100;
|
657 | dbda808a | bellard | addr &= 0xFFFF;
|
658 | dbda808a | bellard | idx = (addr & 0xFFF0) >> 6; |
659 | dbda808a | bellard | addr = addr & 0x30;
|
660 | dbda808a | bellard | switch (addr) {
|
661 | dbda808a | bellard | case 0x00: /* TICC */ |
662 | dbda808a | bellard | retval = opp->timers[idx].ticc; |
663 | dbda808a | bellard | break;
|
664 | dbda808a | bellard | case 0x10: /* TIBC */ |
665 | dbda808a | bellard | retval = opp->timers[idx].tibc; |
666 | dbda808a | bellard | break;
|
667 | dbda808a | bellard | case 0x20: /* TIPV */ |
668 | dbda808a | bellard | retval = read_IRQreg(opp, IRQ_TIM0 + idx, IRQ_IPVP); |
669 | dbda808a | bellard | break;
|
670 | dbda808a | bellard | case 0x30: /* TIDE */ |
671 | dbda808a | bellard | retval = read_IRQreg(opp, IRQ_TIM0 + idx, IRQ_IDE); |
672 | dbda808a | bellard | break;
|
673 | dbda808a | bellard | } |
674 | dbda808a | bellard | DPRINTF("%s: => %08x\n", __func__, retval);
|
675 | dbda808a | bellard | #if defined OPENPIC_SWAP
|
676 | dbda808a | bellard | retval = bswap32(retval); |
677 | dbda808a | bellard | #endif
|
678 | dbda808a | bellard | |
679 | dbda808a | bellard | return retval;
|
680 | dbda808a | bellard | } |
681 | dbda808a | bellard | |
682 | dbda808a | bellard | static void openpic_src_write (void *opaque, uint32_t addr, uint32_t val) |
683 | dbda808a | bellard | { |
684 | dbda808a | bellard | openpic_t *opp = opaque; |
685 | dbda808a | bellard | int idx;
|
686 | dbda808a | bellard | |
687 | dbda808a | bellard | DPRINTF("%s: addr %08x <= %08x\n", __func__, addr, val);
|
688 | dbda808a | bellard | if (addr & 0xF) |
689 | dbda808a | bellard | return;
|
690 | dbda808a | bellard | #if defined OPENPIC_SWAP
|
691 | dbda808a | bellard | val = tswap32(val); |
692 | dbda808a | bellard | #endif
|
693 | dbda808a | bellard | addr = addr & 0xFFF0;
|
694 | dbda808a | bellard | idx = addr >> 5;
|
695 | dbda808a | bellard | if (addr & 0x10) { |
696 | dbda808a | bellard | /* EXDE / IFEDE / IEEDE */
|
697 | dbda808a | bellard | write_IRQreg(opp, idx, IRQ_IDE, val); |
698 | dbda808a | bellard | } else {
|
699 | dbda808a | bellard | /* EXVP / IFEVP / IEEVP */
|
700 | dbda808a | bellard | write_IRQreg(opp, idx, IRQ_IPVP, val); |
701 | dbda808a | bellard | } |
702 | dbda808a | bellard | } |
703 | dbda808a | bellard | |
704 | dbda808a | bellard | static uint32_t openpic_src_read (void *opaque, uint32_t addr) |
705 | dbda808a | bellard | { |
706 | dbda808a | bellard | openpic_t *opp = opaque; |
707 | dbda808a | bellard | uint32_t retval; |
708 | dbda808a | bellard | int idx;
|
709 | dbda808a | bellard | |
710 | dbda808a | bellard | DPRINTF("%s: addr %08x\n", __func__, addr);
|
711 | dbda808a | bellard | retval = 0xFFFFFFFF;
|
712 | dbda808a | bellard | if (addr & 0xF) |
713 | dbda808a | bellard | return retval;
|
714 | dbda808a | bellard | addr = addr & 0xFFF0;
|
715 | dbda808a | bellard | idx = addr >> 5;
|
716 | dbda808a | bellard | if (addr & 0x10) { |
717 | dbda808a | bellard | /* EXDE / IFEDE / IEEDE */
|
718 | dbda808a | bellard | retval = read_IRQreg(opp, idx, IRQ_IDE); |
719 | dbda808a | bellard | } else {
|
720 | dbda808a | bellard | /* EXVP / IFEVP / IEEVP */
|
721 | dbda808a | bellard | retval = read_IRQreg(opp, idx, IRQ_IPVP); |
722 | dbda808a | bellard | } |
723 | dbda808a | bellard | DPRINTF("%s: => %08x\n", __func__, retval);
|
724 | dbda808a | bellard | #if defined OPENPIC_SWAP
|
725 | dbda808a | bellard | retval = tswap32(retval); |
726 | dbda808a | bellard | #endif
|
727 | dbda808a | bellard | |
728 | dbda808a | bellard | return retval;
|
729 | dbda808a | bellard | } |
730 | dbda808a | bellard | |
731 | dbda808a | bellard | static void openpic_cpu_write (void *opaque, uint32_t addr, uint32_t val) |
732 | dbda808a | bellard | { |
733 | dbda808a | bellard | openpic_t *opp = opaque; |
734 | dbda808a | bellard | IRQ_src_t *src; |
735 | dbda808a | bellard | IRQ_dst_t *dst; |
736 | dbda808a | bellard | int idx, n_IRQ;
|
737 | dbda808a | bellard | |
738 | dbda808a | bellard | DPRINTF("%s: addr %08x <= %08x\n", __func__, addr, val);
|
739 | dbda808a | bellard | if (addr & 0xF) |
740 | dbda808a | bellard | return;
|
741 | dbda808a | bellard | #if defined OPENPIC_SWAP
|
742 | dbda808a | bellard | val = bswap32(val); |
743 | dbda808a | bellard | #endif
|
744 | dbda808a | bellard | addr &= 0x1FFF0;
|
745 | dbda808a | bellard | idx = addr / 0x1000;
|
746 | dbda808a | bellard | dst = &opp->dst[idx]; |
747 | dbda808a | bellard | addr &= 0xFF0;
|
748 | dbda808a | bellard | switch (addr) {
|
749 | dbda808a | bellard | #if MAX_IPI > 0 |
750 | dbda808a | bellard | case 0x40: /* PIPD */ |
751 | dbda808a | bellard | case 0x50: |
752 | dbda808a | bellard | case 0x60: |
753 | dbda808a | bellard | case 0x70: |
754 | dbda808a | bellard | idx = (addr - 0x40) >> 4; |
755 | dbda808a | bellard | write_IRQreg(opp, IRQ_IPI0 + idx, IRQ_IDE, val); |
756 | 611493d9 | bellard | openpic_set_irq(opp, IRQ_IPI0 + idx, 1);
|
757 | 611493d9 | bellard | openpic_set_irq(opp, IRQ_IPI0 + idx, 0);
|
758 | dbda808a | bellard | break;
|
759 | dbda808a | bellard | #endif
|
760 | dbda808a | bellard | case 0x80: /* PCTP */ |
761 | dbda808a | bellard | dst->pctp = val & 0x0000000F;
|
762 | dbda808a | bellard | break;
|
763 | dbda808a | bellard | case 0x90: /* WHOAMI */ |
764 | dbda808a | bellard | /* Read-only register */
|
765 | dbda808a | bellard | break;
|
766 | dbda808a | bellard | case 0xA0: /* PIAC */ |
767 | dbda808a | bellard | /* Read-only register */
|
768 | dbda808a | bellard | break;
|
769 | dbda808a | bellard | case 0xB0: /* PEOI */ |
770 | dbda808a | bellard | DPRINTF("PEOI\n");
|
771 | dbda808a | bellard | n_IRQ = IRQ_get_next(opp, &dst->servicing); |
772 | dbda808a | bellard | IRQ_resetbit(&dst->servicing, n_IRQ); |
773 | dbda808a | bellard | dst->servicing.next = -1;
|
774 | dbda808a | bellard | src = &opp->src[n_IRQ]; |
775 | dbda808a | bellard | /* Set up next servicing IRQ */
|
776 | dbda808a | bellard | IRQ_get_next(opp, &dst->servicing); |
777 | dbda808a | bellard | /* Check queued interrupts. */
|
778 | dbda808a | bellard | n_IRQ = IRQ_get_next(opp, &dst->raised); |
779 | dbda808a | bellard | if (n_IRQ != -1) { |
780 | dbda808a | bellard | src = &opp->src[n_IRQ]; |
781 | dbda808a | bellard | if (IPVP_PRIORITY(src->ipvp) > dst->servicing.priority) {
|
782 | dbda808a | bellard | DPRINTF("Raise CPU IRQ\n");
|
783 | dbda808a | bellard | cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HARD); |
784 | dbda808a | bellard | } |
785 | dbda808a | bellard | } |
786 | dbda808a | bellard | break;
|
787 | dbda808a | bellard | default:
|
788 | dbda808a | bellard | break;
|
789 | dbda808a | bellard | } |
790 | dbda808a | bellard | } |
791 | dbda808a | bellard | |
792 | dbda808a | bellard | static uint32_t openpic_cpu_read (void *opaque, uint32_t addr) |
793 | dbda808a | bellard | { |
794 | dbda808a | bellard | openpic_t *opp = opaque; |
795 | dbda808a | bellard | IRQ_src_t *src; |
796 | dbda808a | bellard | IRQ_dst_t *dst; |
797 | dbda808a | bellard | uint32_t retval; |
798 | dbda808a | bellard | int idx, n_IRQ;
|
799 | dbda808a | bellard | |
800 | dbda808a | bellard | DPRINTF("%s: addr %08x\n", __func__, addr);
|
801 | dbda808a | bellard | retval = 0xFFFFFFFF;
|
802 | dbda808a | bellard | if (addr & 0xF) |
803 | dbda808a | bellard | return retval;
|
804 | dbda808a | bellard | addr &= 0x1FFF0;
|
805 | dbda808a | bellard | idx = addr / 0x1000;
|
806 | dbda808a | bellard | dst = &opp->dst[idx]; |
807 | dbda808a | bellard | addr &= 0xFF0;
|
808 | dbda808a | bellard | switch (addr) {
|
809 | dbda808a | bellard | case 0x80: /* PCTP */ |
810 | dbda808a | bellard | retval = dst->pctp; |
811 | dbda808a | bellard | break;
|
812 | dbda808a | bellard | case 0x90: /* WHOAMI */ |
813 | dbda808a | bellard | retval = idx; |
814 | dbda808a | bellard | break;
|
815 | dbda808a | bellard | case 0xA0: /* PIAC */ |
816 | dbda808a | bellard | n_IRQ = IRQ_get_next(opp, &dst->raised); |
817 | dbda808a | bellard | DPRINTF("PIAC: irq=%d\n", n_IRQ);
|
818 | dbda808a | bellard | if (n_IRQ == -1) { |
819 | dbda808a | bellard | /* No more interrupt pending */
|
820 | dbda808a | bellard | retval = opp->spve; |
821 | dbda808a | bellard | } else {
|
822 | dbda808a | bellard | src = &opp->src[n_IRQ]; |
823 | dbda808a | bellard | if (!test_bit(&src->ipvp, IPVP_ACTIVITY) ||
|
824 | dbda808a | bellard | !(IPVP_PRIORITY(src->ipvp) > dst->pctp)) { |
825 | dbda808a | bellard | /* - Spurious level-sensitive IRQ
|
826 | dbda808a | bellard | * - Priorities has been changed
|
827 | dbda808a | bellard | * and the pending IRQ isn't allowed anymore
|
828 | dbda808a | bellard | */
|
829 | dbda808a | bellard | reset_bit(&src->ipvp, IPVP_ACTIVITY); |
830 | dbda808a | bellard | retval = IPVP_VECTOR(opp->spve); |
831 | dbda808a | bellard | } else {
|
832 | dbda808a | bellard | /* IRQ enter servicing state */
|
833 | dbda808a | bellard | IRQ_setbit(&dst->servicing, n_IRQ); |
834 | dbda808a | bellard | retval = IPVP_VECTOR(src->ipvp); |
835 | dbda808a | bellard | } |
836 | dbda808a | bellard | IRQ_resetbit(&dst->raised, n_IRQ); |
837 | dbda808a | bellard | dst->raised.next = -1;
|
838 | 611493d9 | bellard | if (!test_bit(&src->ipvp, IPVP_SENSE)) {
|
839 | 611493d9 | bellard | /* edge-sensitive IRQ */
|
840 | dbda808a | bellard | reset_bit(&src->ipvp, IPVP_ACTIVITY); |
841 | 611493d9 | bellard | src->pending = 0;
|
842 | 611493d9 | bellard | } |
843 | dbda808a | bellard | } |
844 | dbda808a | bellard | break;
|
845 | dbda808a | bellard | case 0xB0: /* PEOI */ |
846 | dbda808a | bellard | retval = 0;
|
847 | dbda808a | bellard | break;
|
848 | dbda808a | bellard | #if MAX_IPI > 0 |
849 | dbda808a | bellard | case 0x40: /* IDE */ |
850 | dbda808a | bellard | case 0x50: |
851 | dbda808a | bellard | idx = (addr - 0x40) >> 4; |
852 | dbda808a | bellard | retval = read_IRQreg(opp, IRQ_IPI0 + idx, IRQ_IDE); |
853 | dbda808a | bellard | break;
|
854 | dbda808a | bellard | #endif
|
855 | dbda808a | bellard | default:
|
856 | dbda808a | bellard | break;
|
857 | dbda808a | bellard | } |
858 | dbda808a | bellard | DPRINTF("%s: => %08x\n", __func__, retval);
|
859 | dbda808a | bellard | #if defined OPENPIC_SWAP
|
860 | dbda808a | bellard | retval= bswap32(retval); |
861 | dbda808a | bellard | #endif
|
862 | dbda808a | bellard | |
863 | dbda808a | bellard | return retval;
|
864 | dbda808a | bellard | } |
865 | dbda808a | bellard | |
866 | dbda808a | bellard | static void openpic_buggy_write (void *opaque, |
867 | dbda808a | bellard | target_phys_addr_t addr, uint32_t val) |
868 | dbda808a | bellard | { |
869 | dbda808a | bellard | printf("Invalid OPENPIC write access !\n");
|
870 | dbda808a | bellard | } |
871 | dbda808a | bellard | |
872 | dbda808a | bellard | static uint32_t openpic_buggy_read (void *opaque, target_phys_addr_t addr) |
873 | dbda808a | bellard | { |
874 | dbda808a | bellard | printf("Invalid OPENPIC read access !\n");
|
875 | dbda808a | bellard | |
876 | dbda808a | bellard | return -1; |
877 | dbda808a | bellard | } |
878 | dbda808a | bellard | |
879 | dbda808a | bellard | static void openpic_writel (void *opaque, |
880 | dbda808a | bellard | target_phys_addr_t addr, uint32_t val) |
881 | dbda808a | bellard | { |
882 | dbda808a | bellard | openpic_t *opp = opaque; |
883 | dbda808a | bellard | |
884 | dbda808a | bellard | addr &= 0x3FFFF;
|
885 | 611493d9 | bellard | DPRINTF("%s: offset %08x val: %08x\n", __func__, (int)addr, val); |
886 | dbda808a | bellard | if (addr < 0x1100) { |
887 | dbda808a | bellard | /* Global registers */
|
888 | dbda808a | bellard | openpic_gbl_write(opp, addr, val); |
889 | dbda808a | bellard | } else if (addr < 0x10000) { |
890 | dbda808a | bellard | /* Timers registers */
|
891 | dbda808a | bellard | openpic_timer_write(opp, addr, val); |
892 | dbda808a | bellard | } else if (addr < 0x20000) { |
893 | dbda808a | bellard | /* Source registers */
|
894 | dbda808a | bellard | openpic_src_write(opp, addr, val); |
895 | dbda808a | bellard | } else {
|
896 | dbda808a | bellard | /* CPU registers */
|
897 | dbda808a | bellard | openpic_cpu_write(opp, addr, val); |
898 | dbda808a | bellard | } |
899 | dbda808a | bellard | } |
900 | dbda808a | bellard | |
901 | dbda808a | bellard | static uint32_t openpic_readl (void *opaque,target_phys_addr_t addr) |
902 | dbda808a | bellard | { |
903 | dbda808a | bellard | openpic_t *opp = opaque; |
904 | dbda808a | bellard | uint32_t retval; |
905 | dbda808a | bellard | |
906 | dbda808a | bellard | addr &= 0x3FFFF;
|
907 | 611493d9 | bellard | DPRINTF("%s: offset %08x\n", __func__, (int)addr); |
908 | dbda808a | bellard | if (addr < 0x1100) { |
909 | dbda808a | bellard | /* Global registers */
|
910 | dbda808a | bellard | retval = openpic_gbl_read(opp, addr); |
911 | dbda808a | bellard | } else if (addr < 0x10000) { |
912 | dbda808a | bellard | /* Timers registers */
|
913 | dbda808a | bellard | retval = openpic_timer_read(opp, addr); |
914 | dbda808a | bellard | } else if (addr < 0x20000) { |
915 | dbda808a | bellard | /* Source registers */
|
916 | dbda808a | bellard | retval = openpic_src_read(opp, addr); |
917 | dbda808a | bellard | } else {
|
918 | dbda808a | bellard | /* CPU registers */
|
919 | dbda808a | bellard | retval = openpic_cpu_read(opp, addr); |
920 | dbda808a | bellard | } |
921 | dbda808a | bellard | |
922 | dbda808a | bellard | return retval;
|
923 | dbda808a | bellard | } |
924 | dbda808a | bellard | |
925 | dbda808a | bellard | static CPUWriteMemoryFunc *openpic_write[] = {
|
926 | dbda808a | bellard | &openpic_buggy_write, |
927 | dbda808a | bellard | &openpic_buggy_write, |
928 | dbda808a | bellard | &openpic_writel, |
929 | dbda808a | bellard | }; |
930 | dbda808a | bellard | |
931 | dbda808a | bellard | static CPUReadMemoryFunc *openpic_read[] = {
|
932 | dbda808a | bellard | &openpic_buggy_read, |
933 | dbda808a | bellard | &openpic_buggy_read, |
934 | dbda808a | bellard | &openpic_readl, |
935 | dbda808a | bellard | }; |
936 | dbda808a | bellard | |
937 | dbda808a | bellard | static void openpic_map(PCIDevice *pci_dev, int region_num, |
938 | dbda808a | bellard | uint32_t addr, uint32_t size, int type)
|
939 | dbda808a | bellard | { |
940 | dbda808a | bellard | openpic_t *opp; |
941 | dbda808a | bellard | |
942 | dbda808a | bellard | DPRINTF("Map OpenPIC\n");
|
943 | dbda808a | bellard | opp = (openpic_t *)pci_dev; |
944 | dbda808a | bellard | /* Global registers */
|
945 | dbda808a | bellard | DPRINTF("Register OPENPIC gbl %08x => %08x\n",
|
946 | dbda808a | bellard | addr + 0x1000, addr + 0x1000 + 0x100); |
947 | dbda808a | bellard | /* Timer registers */
|
948 | dbda808a | bellard | DPRINTF("Register OPENPIC timer %08x => %08x\n",
|
949 | dbda808a | bellard | addr + 0x1100, addr + 0x1100 + 0x40 * MAX_TMR); |
950 | dbda808a | bellard | /* Interrupt source registers */
|
951 | dbda808a | bellard | DPRINTF("Register OPENPIC src %08x => %08x\n",
|
952 | dbda808a | bellard | addr + 0x10000, addr + 0x10000 + 0x20 * (EXT_IRQ + 2)); |
953 | dbda808a | bellard | /* Per CPU registers */
|
954 | dbda808a | bellard | DPRINTF("Register OPENPIC dst %08x => %08x\n",
|
955 | dbda808a | bellard | addr + 0x20000, addr + 0x20000 + 0x1000 * MAX_CPU); |
956 | 91d848eb | bellard | cpu_register_physical_memory(addr, 0x40000, opp->mem_index);
|
957 | dbda808a | bellard | #if 0 // Don't implement ISU for now
|
958 | dbda808a | bellard | opp_io_memory = cpu_register_io_memory(0, openpic_src_read,
|
959 | dbda808a | bellard | openpic_src_write);
|
960 | dbda808a | bellard | cpu_register_physical_memory(isu_base, 0x20 * (EXT_IRQ + 2),
|
961 | dbda808a | bellard | opp_io_memory);
|
962 | dbda808a | bellard | #endif
|
963 | dbda808a | bellard | } |
964 | dbda808a | bellard | |
965 | 91d848eb | bellard | openpic_t *openpic_init (PCIBus *bus, int *pmem_index, int nb_cpus) |
966 | dbda808a | bellard | { |
967 | dbda808a | bellard | openpic_t *opp; |
968 | dbda808a | bellard | uint8_t *pci_conf; |
969 | dbda808a | bellard | int i, m;
|
970 | dbda808a | bellard | |
971 | dbda808a | bellard | /* XXX: for now, only one CPU is supported */
|
972 | dbda808a | bellard | if (nb_cpus != 1) |
973 | dbda808a | bellard | return NULL; |
974 | 91d848eb | bellard | if (bus) {
|
975 | 91d848eb | bellard | opp = (openpic_t *)pci_register_device(bus, "OpenPIC", sizeof(openpic_t), |
976 | 91d848eb | bellard | -1, NULL, NULL); |
977 | 91d848eb | bellard | if (opp == NULL) |
978 | 91d848eb | bellard | return NULL; |
979 | 91d848eb | bellard | pci_conf = opp->pci_dev.config; |
980 | 91d848eb | bellard | pci_conf[0x00] = 0x14; // IBM MPIC2 |
981 | 91d848eb | bellard | pci_conf[0x01] = 0x10; |
982 | 91d848eb | bellard | pci_conf[0x02] = 0xFF; |
983 | 91d848eb | bellard | pci_conf[0x03] = 0xFF; |
984 | 91d848eb | bellard | pci_conf[0x0a] = 0x80; // PIC |
985 | 91d848eb | bellard | pci_conf[0x0b] = 0x08; |
986 | 91d848eb | bellard | pci_conf[0x0e] = 0x00; // header_type |
987 | 91d848eb | bellard | pci_conf[0x3d] = 0x00; // no interrupt pin |
988 | 91d848eb | bellard | |
989 | 91d848eb | bellard | /* Register I/O spaces */
|
990 | 91d848eb | bellard | pci_register_io_region((PCIDevice *)opp, 0, 0x40000, |
991 | 91d848eb | bellard | PCI_ADDRESS_SPACE_MEM, &openpic_map); |
992 | 91d848eb | bellard | } else {
|
993 | 91d848eb | bellard | opp = qemu_mallocz(sizeof(openpic_t));
|
994 | 91d848eb | bellard | } |
995 | 91d848eb | bellard | |
996 | 91d848eb | bellard | opp->mem_index = cpu_register_io_memory(0, openpic_read,
|
997 | 91d848eb | bellard | openpic_write, opp); |
998 | 91d848eb | bellard | |
999 | 91d848eb | bellard | // isu_base &= 0xFFFC0000;
|
1000 | dbda808a | bellard | opp->nb_cpus = nb_cpus; |
1001 | dbda808a | bellard | /* Set IRQ types */
|
1002 | dbda808a | bellard | for (i = 0; i < EXT_IRQ; i++) { |
1003 | dbda808a | bellard | opp->src[i].type = IRQ_EXTERNAL; |
1004 | dbda808a | bellard | } |
1005 | dbda808a | bellard | for (; i < IRQ_TIM0; i++) {
|
1006 | dbda808a | bellard | opp->src[i].type = IRQ_SPECIAL; |
1007 | dbda808a | bellard | } |
1008 | dbda808a | bellard | #if MAX_IPI > 0 |
1009 | dbda808a | bellard | m = IRQ_IPI0; |
1010 | dbda808a | bellard | #else
|
1011 | dbda808a | bellard | m = IRQ_DBL0; |
1012 | dbda808a | bellard | #endif
|
1013 | dbda808a | bellard | for (; i < m; i++) {
|
1014 | dbda808a | bellard | opp->src[i].type = IRQ_TIMER; |
1015 | dbda808a | bellard | } |
1016 | dbda808a | bellard | for (; i < MAX_IRQ; i++) {
|
1017 | dbda808a | bellard | opp->src[i].type = IRQ_INTERNAL; |
1018 | dbda808a | bellard | } |
1019 | dbda808a | bellard | openpic_reset(opp); |
1020 | 91d848eb | bellard | if (pmem_index)
|
1021 | 91d848eb | bellard | *pmem_index = opp->mem_index; |
1022 | dbda808a | bellard | return opp;
|
1023 | dbda808a | bellard | } |