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/*
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* QEMU NE2000 emulation
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*
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* Copyright (c) 2003-2004 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "vl.h" |
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|
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/* debug NE2000 card */
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//#define DEBUG_NE2000
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#define MAX_ETH_FRAME_SIZE 1514 |
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#define E8390_CMD 0x00 /* The command register (for all pages) */ |
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/* Page 0 register offsets. */
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#define EN0_CLDALO 0x01 /* Low byte of current local dma addr RD */ |
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#define EN0_STARTPG 0x01 /* Starting page of ring bfr WR */ |
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#define EN0_CLDAHI 0x02 /* High byte of current local dma addr RD */ |
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#define EN0_STOPPG 0x02 /* Ending page +1 of ring bfr WR */ |
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#define EN0_BOUNDARY 0x03 /* Boundary page of ring bfr RD WR */ |
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#define EN0_TSR 0x04 /* Transmit status reg RD */ |
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#define EN0_TPSR 0x04 /* Transmit starting page WR */ |
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#define EN0_NCR 0x05 /* Number of collision reg RD */ |
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#define EN0_TCNTLO 0x05 /* Low byte of tx byte count WR */ |
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#define EN0_FIFO 0x06 /* FIFO RD */ |
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#define EN0_TCNTHI 0x06 /* High byte of tx byte count WR */ |
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#define EN0_ISR 0x07 /* Interrupt status reg RD WR */ |
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#define EN0_CRDALO 0x08 /* low byte of current remote dma address RD */ |
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#define EN0_RSARLO 0x08 /* Remote start address reg 0 */ |
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#define EN0_CRDAHI 0x09 /* high byte, current remote dma address RD */ |
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#define EN0_RSARHI 0x09 /* Remote start address reg 1 */ |
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#define EN0_RCNTLO 0x0a /* Remote byte count reg WR */ |
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#define EN0_RCNTHI 0x0b /* Remote byte count reg WR */ |
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#define EN0_RSR 0x0c /* rx status reg RD */ |
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#define EN0_RXCR 0x0c /* RX configuration reg WR */ |
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#define EN0_TXCR 0x0d /* TX configuration reg WR */ |
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#define EN0_COUNTER0 0x0d /* Rcv alignment error counter RD */ |
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#define EN0_DCFG 0x0e /* Data configuration reg WR */ |
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#define EN0_COUNTER1 0x0e /* Rcv CRC error counter RD */ |
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#define EN0_IMR 0x0f /* Interrupt mask reg WR */ |
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#define EN0_COUNTER2 0x0f /* Rcv missed frame error counter RD */ |
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|
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#define EN1_PHYS 0x11 |
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#define EN1_CURPAG 0x17 |
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#define EN1_MULT 0x18 |
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|
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#define EN2_STARTPG 0x21 /* Starting page of ring bfr RD */ |
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#define EN2_STOPPG 0x22 /* Ending page +1 of ring bfr RD */ |
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/* Register accessed at EN_CMD, the 8390 base addr. */
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#define E8390_STOP 0x01 /* Stop and reset the chip */ |
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#define E8390_START 0x02 /* Start the chip, clear reset */ |
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#define E8390_TRANS 0x04 /* Transmit a frame */ |
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#define E8390_RREAD 0x08 /* Remote read */ |
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#define E8390_RWRITE 0x10 /* Remote write */ |
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#define E8390_NODMA 0x20 /* Remote DMA */ |
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#define E8390_PAGE0 0x00 /* Select page chip registers */ |
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#define E8390_PAGE1 0x40 /* using the two high-order bits */ |
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#define E8390_PAGE2 0x80 /* Page 3 is invalid. */ |
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|
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/* Bits in EN0_ISR - Interrupt status register */
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#define ENISR_RX 0x01 /* Receiver, no error */ |
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#define ENISR_TX 0x02 /* Transmitter, no error */ |
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#define ENISR_RX_ERR 0x04 /* Receiver, with error */ |
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#define ENISR_TX_ERR 0x08 /* Transmitter, with error */ |
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#define ENISR_OVER 0x10 /* Receiver overwrote the ring */ |
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#define ENISR_COUNTERS 0x20 /* Counters need emptying */ |
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#define ENISR_RDC 0x40 /* remote dma complete */ |
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#define ENISR_RESET 0x80 /* Reset completed */ |
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#define ENISR_ALL 0x3f /* Interrupts we will enable */ |
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|
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/* Bits in received packet status byte and EN0_RSR*/
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#define ENRSR_RXOK 0x01 /* Received a good packet */ |
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#define ENRSR_CRC 0x02 /* CRC error */ |
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#define ENRSR_FAE 0x04 /* frame alignment error */ |
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#define ENRSR_FO 0x08 /* FIFO overrun */ |
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#define ENRSR_MPA 0x10 /* missed pkt */ |
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#define ENRSR_PHY 0x20 /* physical/multicast address */ |
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#define ENRSR_DIS 0x40 /* receiver disable. set in monitor mode */ |
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#define ENRSR_DEF 0x80 /* deferring */ |
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|
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/* Transmitted packet status, EN0_TSR. */
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#define ENTSR_PTX 0x01 /* Packet transmitted without error */ |
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#define ENTSR_ND 0x02 /* The transmit wasn't deferred. */ |
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#define ENTSR_COL 0x04 /* The transmit collided at least once. */ |
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#define ENTSR_ABT 0x08 /* The transmit collided 16 times, and was deferred. */ |
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#define ENTSR_CRS 0x10 /* The carrier sense was lost. */ |
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#define ENTSR_FU 0x20 /* A "FIFO underrun" occurred during transmit. */ |
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#define ENTSR_CDH 0x40 /* The collision detect "heartbeat" signal was lost. */ |
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#define ENTSR_OWC 0x80 /* There was an out-of-window collision. */ |
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#define NE2000_PMEM_SIZE (32*1024) |
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#define NE2000_PMEM_START (16*1024) |
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#define NE2000_PMEM_END (NE2000_PMEM_SIZE+NE2000_PMEM_START)
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#define NE2000_MEM_SIZE NE2000_PMEM_END
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typedef struct NE2000State { |
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uint8_t cmd; |
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uint32_t start; |
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uint32_t stop; |
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uint8_t boundary; |
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uint8_t tsr; |
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uint8_t tpsr; |
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uint16_t tcnt; |
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uint16_t rcnt; |
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uint32_t rsar; |
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uint8_t rsr; |
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uint8_t isr; |
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uint8_t dcfg; |
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uint8_t imr; |
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uint8_t phys[6]; /* mac address */ |
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uint8_t curpag; |
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uint8_t mult[8]; /* multicast mask array */ |
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int irq;
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PCIDevice *pci_dev; |
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NetDriverState *nd; |
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uint8_t mem[NE2000_MEM_SIZE]; |
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} NE2000State; |
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|
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static void ne2000_reset(NE2000State *s) |
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{
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int i;
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s->isr = ENISR_RESET; |
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memcpy(s->mem, s->nd->macaddr, 6);
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s->mem[14] = 0x57; |
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s->mem[15] = 0x57; |
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|
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/* duplicate prom data */
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for(i = 15;i >= 0; i--) { |
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s->mem[2 * i] = s->mem[i];
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s->mem[2 * i + 1] = s->mem[i]; |
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} |
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} |
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static void ne2000_update_irq(NE2000State *s) |
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{
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int isr;
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isr = (s->isr & s->imr) & 0x7f;
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#if defined(DEBUG_NE2000)
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printf("NE2000: Set IRQ line %d to %d (%02x %02x)\n",
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s->irq, isr ? 1 : 0, s->isr, s->imr); |
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#endif
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if (s->irq == 16) { |
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/* PCI irq */
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pci_set_irq(s->pci_dev, 0, (isr != 0)); |
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} else {
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/* ISA irq */
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pic_set_irq(s->irq, (isr != 0));
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} |
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} |
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/* return the max buffer size if the NE2000 can receive more data */
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static int ne2000_can_receive(void *opaque) |
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{
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NE2000State *s = opaque; |
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int avail, index, boundary;
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if (s->cmd & E8390_STOP)
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return 0; |
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index = s->curpag << 8;
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boundary = s->boundary << 8;
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if (index < boundary)
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avail = boundary - index; |
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else
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avail = (s->stop - s->start) - (index - boundary); |
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if (avail < (MAX_ETH_FRAME_SIZE + 4)) |
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return 0; |
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return MAX_ETH_FRAME_SIZE;
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} |
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#define MIN_BUF_SIZE 60 |
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|
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static void ne2000_receive(void *opaque, const uint8_t *buf, int size) |
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{
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NE2000State *s = opaque; |
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uint8_t *p; |
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int total_len, next, avail, len, index;
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uint8_t buf1[60];
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#if defined(DEBUG_NE2000)
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printf("NE2000: received len=%d\n", size);
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#endif
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/* if too small buffer, then expand it */
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if (size < MIN_BUF_SIZE) {
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memcpy(buf1, buf, size); |
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memset(buf1 + size, 0, MIN_BUF_SIZE - size);
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buf = buf1; |
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size = MIN_BUF_SIZE; |
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} |
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|
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index = s->curpag << 8;
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/* 4 bytes for header */
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total_len = size + 4;
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/* address for next packet (4 bytes for CRC) */
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next = index + ((total_len + 4 + 255) & ~0xff); |
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if (next >= s->stop)
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next -= (s->stop - s->start); |
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/* prepare packet header */
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p = s->mem + index; |
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s->rsr = ENRSR_RXOK; /* receive status */
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/* XXX: check this */
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if (buf[0] & 0x01) |
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s->rsr |= ENRSR_PHY; |
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p[0] = s->rsr;
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p[1] = next >> 8; |
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p[2] = total_len;
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p[3] = total_len >> 8; |
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index += 4;
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|
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/* write packet data */
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while (size > 0) { |
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avail = s->stop - index; |
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len = size; |
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if (len > avail)
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len = avail; |
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memcpy(s->mem + index, buf, len); |
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buf += len; |
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index += len; |
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if (index == s->stop)
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index = s->start; |
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size -= len; |
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} |
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s->curpag = next >> 8;
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|
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/* now we can signal we have receive something */
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s->isr |= ENISR_RX; |
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ne2000_update_irq(s); |
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} |
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|
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static void ne2000_ioport_write(void *opaque, uint32_t addr, uint32_t val) |
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{
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NE2000State *s = opaque; |
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int offset, page, index;
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|
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addr &= 0xf;
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#ifdef DEBUG_NE2000
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printf("NE2000: write addr=0x%x val=0x%02x\n", addr, val);
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#endif
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if (addr == E8390_CMD) {
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/* control register */
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s->cmd = val; |
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if (!(val & E8390_STOP)) { /* START bit makes no sense on RTL8029... */ |
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s->isr &= ~ENISR_RESET; |
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/* test specific case: zero length transfert */
|
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if ((val & (E8390_RREAD | E8390_RWRITE)) &&
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s->rcnt == 0) {
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s->isr |= ENISR_RDC; |
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ne2000_update_irq(s); |
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} |
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if (val & E8390_TRANS) {
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index = (s->tpsr << 8);
|
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/* XXX: next 2 lines are a hack to make netware 3.11 work */
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if (index >= NE2000_PMEM_END)
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index -= NE2000_PMEM_SIZE; |
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/* fail safe: check range on the transmitted length */
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if (index + s->tcnt <= NE2000_PMEM_END) {
|
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qemu_send_packet(s->nd, s->mem + index, s->tcnt); |
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} |
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/* signal end of transfert */
|
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s->tsr = ENTSR_PTX; |
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s->isr |= ENISR_TX; |
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s->cmd &= ~E8390_TRANS; |
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ne2000_update_irq(s); |
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} |
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} |
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} else {
|
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page = s->cmd >> 6;
|
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offset = addr | (page << 4);
|
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switch(offset) {
|
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case EN0_STARTPG:
|
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s->start = val << 8;
|
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break;
|
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case EN0_STOPPG:
|
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s->stop = val << 8;
|
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break;
|
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case EN0_BOUNDARY:
|
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s->boundary = val; |
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break;
|
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case EN0_IMR:
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s->imr = val; |
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ne2000_update_irq(s); |
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break;
|
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case EN0_TPSR:
|
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s->tpsr = val; |
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break;
|
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case EN0_TCNTLO:
|
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s->tcnt = (s->tcnt & 0xff00) | val;
|
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break;
|
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case EN0_TCNTHI:
|
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s->tcnt = (s->tcnt & 0x00ff) | (val << 8); |
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break;
|
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case EN0_RSARLO:
|
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s->rsar = (s->rsar & 0xff00) | val;
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break;
|
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case EN0_RSARHI:
|
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s->rsar = (s->rsar & 0x00ff) | (val << 8); |
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break;
|
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case EN0_RCNTLO:
|
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s->rcnt = (s->rcnt & 0xff00) | val;
|
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break;
|
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case EN0_RCNTHI:
|
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s->rcnt = (s->rcnt & 0x00ff) | (val << 8); |
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break;
|
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case EN0_DCFG:
|
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s->dcfg = val; |
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break;
|
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case EN0_ISR:
|
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s->isr &= ~(val & 0x7f);
|
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ne2000_update_irq(s); |
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break;
|
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case EN1_PHYS ... EN1_PHYS + 5: |
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s->phys[offset - EN1_PHYS] = val; |
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break;
|
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case EN1_CURPAG:
|
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s->curpag = val; |
| 335 |
break;
|
| 336 |
case EN1_MULT ... EN1_MULT + 7: |
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s->mult[offset - EN1_MULT] = val; |
| 338 |
break;
|
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} |
| 340 |
} |
| 341 |
} |
| 342 |
|
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static uint32_t ne2000_ioport_read(void *opaque, uint32_t addr) |
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{
|
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NE2000State *s = opaque; |
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int offset, page, ret;
|
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|
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addr &= 0xf;
|
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if (addr == E8390_CMD) {
|
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ret = s->cmd; |
| 351 |
} else {
|
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page = s->cmd >> 6;
|
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offset = addr | (page << 4);
|
| 354 |
switch(offset) {
|
| 355 |
case EN0_TSR:
|
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ret = s->tsr; |
| 357 |
break;
|
| 358 |
case EN0_BOUNDARY:
|
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ret = s->boundary; |
| 360 |
break;
|
| 361 |
case EN0_ISR:
|
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ret = s->isr; |
| 363 |
break;
|
| 364 |
case EN0_RSARLO:
|
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ret = s->rsar & 0x00ff;
|
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break;
|
| 367 |
case EN0_RSARHI:
|
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ret = s->rsar >> 8;
|
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break;
|
| 370 |
case EN1_PHYS ... EN1_PHYS + 5: |
| 371 |
ret = s->phys[offset - EN1_PHYS]; |
| 372 |
break;
|
| 373 |
case EN1_CURPAG:
|
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ret = s->curpag; |
| 375 |
break;
|
| 376 |
case EN1_MULT ... EN1_MULT + 7: |
| 377 |
ret = s->mult[offset - EN1_MULT]; |
| 378 |
break;
|
| 379 |
case EN0_RSR:
|
| 380 |
ret = s->rsr; |
| 381 |
break;
|
| 382 |
case EN2_STARTPG:
|
| 383 |
ret = s->start >> 8;
|
| 384 |
break;
|
| 385 |
case EN2_STOPPG:
|
| 386 |
ret = s->stop >> 8;
|
| 387 |
break;
|
| 388 |
default:
|
| 389 |
ret = 0x00;
|
| 390 |
break;
|
| 391 |
} |
| 392 |
} |
| 393 |
#ifdef DEBUG_NE2000
|
| 394 |
printf("NE2000: read addr=0x%x val=%02x\n", addr, ret);
|
| 395 |
#endif
|
| 396 |
return ret;
|
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} |
| 398 |
|
| 399 |
static inline void ne2000_mem_writeb(NE2000State *s, uint32_t addr, |
| 400 |
uint32_t val) |
| 401 |
{
|
| 402 |
if (addr < 32 || |
| 403 |
(addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
|
| 404 |
s->mem[addr] = val; |
| 405 |
} |
| 406 |
} |
| 407 |
|
| 408 |
static inline void ne2000_mem_writew(NE2000State *s, uint32_t addr, |
| 409 |
uint32_t val) |
| 410 |
{
|
| 411 |
addr &= ~1; /* XXX: check exact behaviour if not even */ |
| 412 |
if (addr < 32 || |
| 413 |
(addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
|
| 414 |
*(uint16_t *)(s->mem + addr) = cpu_to_le16(val); |
| 415 |
} |
| 416 |
} |
| 417 |
|
| 418 |
static inline void ne2000_mem_writel(NE2000State *s, uint32_t addr, |
| 419 |
uint32_t val) |
| 420 |
{
|
| 421 |
addr &= ~1; /* XXX: check exact behaviour if not even */ |
| 422 |
if (addr < 32 || |
| 423 |
(addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
|
| 424 |
cpu_to_le32wu((uint32_t *)(s->mem + addr), val); |
| 425 |
} |
| 426 |
} |
| 427 |
|
| 428 |
static inline uint32_t ne2000_mem_readb(NE2000State *s, uint32_t addr) |
| 429 |
{
|
| 430 |
if (addr < 32 || |
| 431 |
(addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
|
| 432 |
return s->mem[addr];
|
| 433 |
} else {
|
| 434 |
return 0xff; |
| 435 |
} |
| 436 |
} |
| 437 |
|
| 438 |
static inline uint32_t ne2000_mem_readw(NE2000State *s, uint32_t addr) |
| 439 |
{
|
| 440 |
addr &= ~1; /* XXX: check exact behaviour if not even */ |
| 441 |
if (addr < 32 || |
| 442 |
(addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
|
| 443 |
return le16_to_cpu(*(uint16_t *)(s->mem + addr));
|
| 444 |
} else {
|
| 445 |
return 0xffff; |
| 446 |
} |
| 447 |
} |
| 448 |
|
| 449 |
static inline uint32_t ne2000_mem_readl(NE2000State *s, uint32_t addr) |
| 450 |
{
|
| 451 |
addr &= ~1; /* XXX: check exact behaviour if not even */ |
| 452 |
if (addr < 32 || |
| 453 |
(addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
|
| 454 |
return le32_to_cpupu((uint32_t *)(s->mem + addr));
|
| 455 |
} else {
|
| 456 |
return 0xffffffff; |
| 457 |
} |
| 458 |
} |
| 459 |
|
| 460 |
static inline void ne2000_dma_update(NE2000State *s, int len) |
| 461 |
{
|
| 462 |
s->rsar += len; |
| 463 |
/* wrap */
|
| 464 |
/* XXX: check what to do if rsar > stop */
|
| 465 |
if (s->rsar == s->stop)
|
| 466 |
s->rsar = s->start; |
| 467 |
|
| 468 |
if (s->rcnt <= len) {
|
| 469 |
s->rcnt = 0;
|
| 470 |
/* signal end of transfert */
|
| 471 |
s->isr |= ENISR_RDC; |
| 472 |
ne2000_update_irq(s); |
| 473 |
} else {
|
| 474 |
s->rcnt -= len; |
| 475 |
} |
| 476 |
} |
| 477 |
|
| 478 |
static void ne2000_asic_ioport_write(void *opaque, uint32_t addr, uint32_t val) |
| 479 |
{
|
| 480 |
NE2000State *s = opaque; |
| 481 |
|
| 482 |
#ifdef DEBUG_NE2000
|
| 483 |
printf("NE2000: asic write val=0x%04x\n", val);
|
| 484 |
#endif
|
| 485 |
if (s->rcnt == 0) |
| 486 |
return;
|
| 487 |
if (s->dcfg & 0x01) { |
| 488 |
/* 16 bit access */
|
| 489 |
ne2000_mem_writew(s, s->rsar, val); |
| 490 |
ne2000_dma_update(s, 2);
|
| 491 |
} else {
|
| 492 |
/* 8 bit access */
|
| 493 |
ne2000_mem_writeb(s, s->rsar, val); |
| 494 |
ne2000_dma_update(s, 1);
|
| 495 |
} |
| 496 |
} |
| 497 |
|
| 498 |
static uint32_t ne2000_asic_ioport_read(void *opaque, uint32_t addr) |
| 499 |
{
|
| 500 |
NE2000State *s = opaque; |
| 501 |
int ret;
|
| 502 |
|
| 503 |
if (s->dcfg & 0x01) { |
| 504 |
/* 16 bit access */
|
| 505 |
ret = ne2000_mem_readw(s, s->rsar); |
| 506 |
ne2000_dma_update(s, 2);
|
| 507 |
} else {
|
| 508 |
/* 8 bit access */
|
| 509 |
ret = ne2000_mem_readb(s, s->rsar); |
| 510 |
ne2000_dma_update(s, 1);
|
| 511 |
} |
| 512 |
#ifdef DEBUG_NE2000
|
| 513 |
printf("NE2000: asic read val=0x%04x\n", ret);
|
| 514 |
#endif
|
| 515 |
return ret;
|
| 516 |
} |
| 517 |
|
| 518 |
static void ne2000_asic_ioport_writel(void *opaque, uint32_t addr, uint32_t val) |
| 519 |
{
|
| 520 |
NE2000State *s = opaque; |
| 521 |
|
| 522 |
#ifdef DEBUG_NE2000
|
| 523 |
printf("NE2000: asic writel val=0x%04x\n", val);
|
| 524 |
#endif
|
| 525 |
if (s->rcnt == 0) |
| 526 |
return;
|
| 527 |
/* 32 bit access */
|
| 528 |
ne2000_mem_writel(s, s->rsar, val); |
| 529 |
ne2000_dma_update(s, 4);
|
| 530 |
} |
| 531 |
|
| 532 |
static uint32_t ne2000_asic_ioport_readl(void *opaque, uint32_t addr) |
| 533 |
{
|
| 534 |
NE2000State *s = opaque; |
| 535 |
int ret;
|
| 536 |
|
| 537 |
/* 32 bit access */
|
| 538 |
ret = ne2000_mem_readl(s, s->rsar); |
| 539 |
ne2000_dma_update(s, 4);
|
| 540 |
#ifdef DEBUG_NE2000
|
| 541 |
printf("NE2000: asic readl val=0x%04x\n", ret);
|
| 542 |
#endif
|
| 543 |
return ret;
|
| 544 |
} |
| 545 |
|
| 546 |
static void ne2000_reset_ioport_write(void *opaque, uint32_t addr, uint32_t val) |
| 547 |
{
|
| 548 |
/* nothing to do (end of reset pulse) */
|
| 549 |
} |
| 550 |
|
| 551 |
static uint32_t ne2000_reset_ioport_read(void *opaque, uint32_t addr) |
| 552 |
{
|
| 553 |
NE2000State *s = opaque; |
| 554 |
ne2000_reset(s); |
| 555 |
return 0; |
| 556 |
} |
| 557 |
|
| 558 |
static void ne2000_save(QEMUFile* f,void* opaque) |
| 559 |
{
|
| 560 |
NE2000State* s=(NE2000State*)opaque; |
| 561 |
|
| 562 |
qemu_put_8s(f, &s->cmd); |
| 563 |
qemu_put_be32s(f, &s->start); |
| 564 |
qemu_put_be32s(f, &s->stop); |
| 565 |
qemu_put_8s(f, &s->boundary); |
| 566 |
qemu_put_8s(f, &s->tsr); |
| 567 |
qemu_put_8s(f, &s->tpsr); |
| 568 |
qemu_put_be16s(f, &s->tcnt); |
| 569 |
qemu_put_be16s(f, &s->rcnt); |
| 570 |
qemu_put_be32s(f, &s->rsar); |
| 571 |
qemu_put_8s(f, &s->rsr); |
| 572 |
qemu_put_8s(f, &s->isr); |
| 573 |
qemu_put_8s(f, &s->dcfg); |
| 574 |
qemu_put_8s(f, &s->imr); |
| 575 |
qemu_put_buffer(f, s->phys, 6);
|
| 576 |
qemu_put_8s(f, &s->curpag); |
| 577 |
qemu_put_buffer(f, s->mult, 8);
|
| 578 |
qemu_put_be32s(f, &s->irq); |
| 579 |
qemu_put_buffer(f, s->mem, NE2000_MEM_SIZE); |
| 580 |
} |
| 581 |
|
| 582 |
static int ne2000_load(QEMUFile* f,void* opaque,int version_id) |
| 583 |
{
|
| 584 |
NE2000State* s=(NE2000State*)opaque; |
| 585 |
|
| 586 |
if (version_id != 1) |
| 587 |
return -EINVAL;
|
| 588 |
|
| 589 |
qemu_get_8s(f, &s->cmd); |
| 590 |
qemu_get_be32s(f, &s->start); |
| 591 |
qemu_get_be32s(f, &s->stop); |
| 592 |
qemu_get_8s(f, &s->boundary); |
| 593 |
qemu_get_8s(f, &s->tsr); |
| 594 |
qemu_get_8s(f, &s->tpsr); |
| 595 |
qemu_get_be16s(f, &s->tcnt); |
| 596 |
qemu_get_be16s(f, &s->rcnt); |
| 597 |
qemu_get_be32s(f, &s->rsar); |
| 598 |
qemu_get_8s(f, &s->rsr); |
| 599 |
qemu_get_8s(f, &s->isr); |
| 600 |
qemu_get_8s(f, &s->dcfg); |
| 601 |
qemu_get_8s(f, &s->imr); |
| 602 |
qemu_get_buffer(f, s->phys, 6);
|
| 603 |
qemu_get_8s(f, &s->curpag); |
| 604 |
qemu_get_buffer(f, s->mult, 8);
|
| 605 |
qemu_get_be32s(f, &s->irq); |
| 606 |
qemu_get_buffer(f, s->mem, NE2000_MEM_SIZE); |
| 607 |
|
| 608 |
return 0; |
| 609 |
} |
| 610 |
|
| 611 |
void isa_ne2000_init(int base, int irq, NetDriverState *nd) |
| 612 |
{
|
| 613 |
NE2000State *s; |
| 614 |
|
| 615 |
s = qemu_mallocz(sizeof(NE2000State));
|
| 616 |
if (!s)
|
| 617 |
return;
|
| 618 |
|
| 619 |
register_ioport_write(base, 16, 1, ne2000_ioport_write, s); |
| 620 |
register_ioport_read(base, 16, 1, ne2000_ioport_read, s); |
| 621 |
|
| 622 |
register_ioport_write(base + 0x10, 1, 1, ne2000_asic_ioport_write, s); |
| 623 |
register_ioport_read(base + 0x10, 1, 1, ne2000_asic_ioport_read, s); |
| 624 |
register_ioport_write(base + 0x10, 2, 2, ne2000_asic_ioport_write, s); |
| 625 |
register_ioport_read(base + 0x10, 2, 2, ne2000_asic_ioport_read, s); |
| 626 |
|
| 627 |
register_ioport_write(base + 0x1f, 1, 1, ne2000_reset_ioport_write, s); |
| 628 |
register_ioport_read(base + 0x1f, 1, 1, ne2000_reset_ioport_read, s); |
| 629 |
s->irq = irq; |
| 630 |
s->nd = nd; |
| 631 |
|
| 632 |
ne2000_reset(s); |
| 633 |
|
| 634 |
qemu_add_read_packet(nd, ne2000_can_receive, ne2000_receive, s); |
| 635 |
|
| 636 |
register_savevm("ne2000", 0, 1, ne2000_save, ne2000_load, s); |
| 637 |
|
| 638 |
} |
| 639 |
|
| 640 |
/***********************************************************/
|
| 641 |
/* PCI NE2000 definitions */
|
| 642 |
|
| 643 |
typedef struct PCINE2000State { |
| 644 |
PCIDevice dev; |
| 645 |
NE2000State ne2000; |
| 646 |
} PCINE2000State; |
| 647 |
|
| 648 |
static void ne2000_map(PCIDevice *pci_dev, int region_num, |
| 649 |
uint32_t addr, uint32_t size, int type)
|
| 650 |
{
|
| 651 |
PCINE2000State *d = (PCINE2000State *)pci_dev; |
| 652 |
NE2000State *s = &d->ne2000; |
| 653 |
|
| 654 |
register_ioport_write(addr, 16, 1, ne2000_ioport_write, s); |
| 655 |
register_ioport_read(addr, 16, 1, ne2000_ioport_read, s); |
| 656 |
|
| 657 |
register_ioport_write(addr + 0x10, 1, 1, ne2000_asic_ioport_write, s); |
| 658 |
register_ioport_read(addr + 0x10, 1, 1, ne2000_asic_ioport_read, s); |
| 659 |
register_ioport_write(addr + 0x10, 2, 2, ne2000_asic_ioport_write, s); |
| 660 |
register_ioport_read(addr + 0x10, 2, 2, ne2000_asic_ioport_read, s); |
| 661 |
register_ioport_write(addr + 0x10, 4, 4, ne2000_asic_ioport_writel, s); |
| 662 |
register_ioport_read(addr + 0x10, 4, 4, ne2000_asic_ioport_readl, s); |
| 663 |
|
| 664 |
register_ioport_write(addr + 0x1f, 1, 1, ne2000_reset_ioport_write, s); |
| 665 |
register_ioport_read(addr + 0x1f, 1, 1, ne2000_reset_ioport_read, s); |
| 666 |
} |
| 667 |
|
| 668 |
void pci_ne2000_init(PCIBus *bus, NetDriverState *nd)
|
| 669 |
{
|
| 670 |
PCINE2000State *d; |
| 671 |
NE2000State *s; |
| 672 |
uint8_t *pci_conf; |
| 673 |
|
| 674 |
d = (PCINE2000State *)pci_register_device(bus, |
| 675 |
"NE2000", sizeof(PCINE2000State), |
| 676 |
-1,
|
| 677 |
NULL, NULL); |
| 678 |
pci_conf = d->dev.config; |
| 679 |
pci_conf[0x00] = 0xec; // Realtek 8029 |
| 680 |
pci_conf[0x01] = 0x10; |
| 681 |
pci_conf[0x02] = 0x29; |
| 682 |
pci_conf[0x03] = 0x80; |
| 683 |
pci_conf[0x0a] = 0x00; // ethernet network controller |
| 684 |
pci_conf[0x0b] = 0x02; |
| 685 |
pci_conf[0x0e] = 0x00; // header_type |
| 686 |
pci_conf[0x3d] = 1; // interrupt pin 0 |
| 687 |
|
| 688 |
pci_register_io_region(&d->dev, 0, 0x100, |
| 689 |
PCI_ADDRESS_SPACE_IO, ne2000_map); |
| 690 |
s = &d->ne2000; |
| 691 |
s->irq = 16; // PCI interrupt |
| 692 |
s->pci_dev = (PCIDevice *)d; |
| 693 |
s->nd = nd; |
| 694 |
ne2000_reset(s); |
| 695 |
qemu_add_read_packet(nd, ne2000_can_receive, ne2000_receive, s); |
| 696 |
|
| 697 |
/* XXX: instance number ? */
|
| 698 |
register_savevm("ne2000", 0, 1, ne2000_save, ne2000_load, s); |
| 699 |
register_savevm("ne2000_pci", 0, 1, generic_pci_save, generic_pci_load, |
| 700 |
&d->dev); |
| 701 |
} |