root / hw / pci.c @ 71be0fc3
History | View | Annotate | Download (42.7 kB)
1 |
/*
|
---|---|
2 |
* QEMU PCI bus manager
|
3 |
*
|
4 |
* Copyright (c) 2004 Fabrice Bellard
|
5 |
*
|
6 |
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
7 |
* of this software and associated documentation files (the "Software"), to deal
|
8 |
* in the Software without restriction, including without limitation the rights
|
9 |
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
10 |
* copies of the Software, and to permit persons to whom the Software is
|
11 |
* furnished to do so, subject to the following conditions:
|
12 |
*
|
13 |
* The above copyright notice and this permission notice shall be included in
|
14 |
* all copies or substantial portions of the Software.
|
15 |
*
|
16 |
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
17 |
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
18 |
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
19 |
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
20 |
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
21 |
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
22 |
* THE SOFTWARE.
|
23 |
*/
|
24 |
#include "vl.h" |
25 |
|
26 |
//#define DEBUG_PCI
|
27 |
|
28 |
#define PCI_VENDOR_ID 0x00 /* 16 bits */ |
29 |
#define PCI_DEVICE_ID 0x02 /* 16 bits */ |
30 |
#define PCI_COMMAND 0x04 /* 16 bits */ |
31 |
#define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */ |
32 |
#define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */ |
33 |
#define PCI_CLASS_DEVICE 0x0a /* Device class */ |
34 |
#define PCI_INTERRUPT_LINE 0x3c /* 8 bits */ |
35 |
#define PCI_INTERRUPT_PIN 0x3d /* 8 bits */ |
36 |
#define PCI_MIN_GNT 0x3e /* 8 bits */ |
37 |
#define PCI_MAX_LAT 0x3f /* 8 bits */ |
38 |
|
39 |
/* just used for simpler irq handling. */
|
40 |
#define PCI_DEVICES_MAX 64 |
41 |
#define PCI_IRQ_WORDS ((PCI_DEVICES_MAX + 31) / 32) |
42 |
|
43 |
struct PCIBus {
|
44 |
int bus_num;
|
45 |
int devfn_min;
|
46 |
void (*set_irq)(PCIDevice *pci_dev, int irq_num, int level); |
47 |
uint32_t config_reg; /* XXX: suppress */
|
48 |
openpic_t *openpic; /* XXX: suppress */
|
49 |
PCIDevice *devices[256];
|
50 |
}; |
51 |
|
52 |
target_phys_addr_t pci_mem_base; |
53 |
static int pci_irq_index; |
54 |
static uint32_t pci_irq_levels[4][PCI_IRQ_WORDS]; |
55 |
static PCIBus *first_bus;
|
56 |
|
57 |
static PCIBus *pci_register_bus(void) |
58 |
{ |
59 |
PCIBus *bus; |
60 |
bus = qemu_mallocz(sizeof(PCIBus));
|
61 |
first_bus = bus; |
62 |
return bus;
|
63 |
} |
64 |
|
65 |
void generic_pci_save(QEMUFile* f, void *opaque) |
66 |
{ |
67 |
PCIDevice* s=(PCIDevice*)opaque; |
68 |
|
69 |
qemu_put_buffer(f, s->config, 256);
|
70 |
} |
71 |
|
72 |
int generic_pci_load(QEMUFile* f, void *opaque, int version_id) |
73 |
{ |
74 |
PCIDevice* s=(PCIDevice*)opaque; |
75 |
|
76 |
if (version_id != 1) |
77 |
return -EINVAL;
|
78 |
|
79 |
qemu_get_buffer(f, s->config, 256);
|
80 |
return 0; |
81 |
} |
82 |
|
83 |
/* -1 for devfn means auto assign */
|
84 |
PCIDevice *pci_register_device(PCIBus *bus, const char *name, |
85 |
int instance_size, int devfn, |
86 |
PCIConfigReadFunc *config_read, |
87 |
PCIConfigWriteFunc *config_write) |
88 |
{ |
89 |
PCIDevice *pci_dev; |
90 |
|
91 |
if (pci_irq_index >= PCI_DEVICES_MAX)
|
92 |
return NULL; |
93 |
|
94 |
if (devfn < 0) { |
95 |
for(devfn = bus->devfn_min ; devfn < 256; devfn += 8) { |
96 |
if (!bus->devices[devfn])
|
97 |
goto found;
|
98 |
} |
99 |
return NULL; |
100 |
found: ;
|
101 |
} |
102 |
pci_dev = qemu_mallocz(instance_size); |
103 |
if (!pci_dev)
|
104 |
return NULL; |
105 |
pci_dev->bus = bus; |
106 |
pci_dev->devfn = devfn; |
107 |
pstrcpy(pci_dev->name, sizeof(pci_dev->name), name);
|
108 |
|
109 |
if (!config_read)
|
110 |
config_read = pci_default_read_config; |
111 |
if (!config_write)
|
112 |
config_write = pci_default_write_config; |
113 |
pci_dev->config_read = config_read; |
114 |
pci_dev->config_write = config_write; |
115 |
pci_dev->irq_index = pci_irq_index++; |
116 |
bus->devices[devfn] = pci_dev; |
117 |
return pci_dev;
|
118 |
} |
119 |
|
120 |
void pci_register_io_region(PCIDevice *pci_dev, int region_num, |
121 |
uint32_t size, int type,
|
122 |
PCIMapIORegionFunc *map_func) |
123 |
{ |
124 |
PCIIORegion *r; |
125 |
|
126 |
if ((unsigned int)region_num >= PCI_NUM_REGIONS) |
127 |
return;
|
128 |
r = &pci_dev->io_regions[region_num]; |
129 |
r->addr = -1;
|
130 |
r->size = size; |
131 |
r->type = type; |
132 |
r->map_func = map_func; |
133 |
} |
134 |
|
135 |
static void pci_addr_writel(void* opaque, uint32_t addr, uint32_t val) |
136 |
{ |
137 |
PCIBus *s = opaque; |
138 |
s->config_reg = val; |
139 |
} |
140 |
|
141 |
static uint32_t pci_addr_readl(void* opaque, uint32_t addr) |
142 |
{ |
143 |
PCIBus *s = opaque; |
144 |
return s->config_reg;
|
145 |
} |
146 |
|
147 |
static void pci_update_mappings(PCIDevice *d) |
148 |
{ |
149 |
PCIIORegion *r; |
150 |
int cmd, i;
|
151 |
uint32_t last_addr, new_addr, config_ofs; |
152 |
|
153 |
cmd = le16_to_cpu(*(uint16_t *)(d->config + PCI_COMMAND)); |
154 |
for(i = 0; i < PCI_NUM_REGIONS; i++) { |
155 |
r = &d->io_regions[i]; |
156 |
if (i == PCI_ROM_SLOT) {
|
157 |
config_ofs = 0x30;
|
158 |
} else {
|
159 |
config_ofs = 0x10 + i * 4; |
160 |
} |
161 |
if (r->size != 0) { |
162 |
if (r->type & PCI_ADDRESS_SPACE_IO) {
|
163 |
if (cmd & PCI_COMMAND_IO) {
|
164 |
new_addr = le32_to_cpu(*(uint32_t *)(d->config + |
165 |
config_ofs)); |
166 |
new_addr = new_addr & ~(r->size - 1);
|
167 |
last_addr = new_addr + r->size - 1;
|
168 |
/* NOTE: we have only 64K ioports on PC */
|
169 |
if (last_addr <= new_addr || new_addr == 0 || |
170 |
last_addr >= 0x10000) {
|
171 |
new_addr = -1;
|
172 |
} |
173 |
} else {
|
174 |
new_addr = -1;
|
175 |
} |
176 |
} else {
|
177 |
if (cmd & PCI_COMMAND_MEMORY) {
|
178 |
new_addr = le32_to_cpu(*(uint32_t *)(d->config + |
179 |
config_ofs)); |
180 |
/* the ROM slot has a specific enable bit */
|
181 |
if (i == PCI_ROM_SLOT && !(new_addr & 1)) |
182 |
goto no_mem_map;
|
183 |
new_addr = new_addr & ~(r->size - 1);
|
184 |
last_addr = new_addr + r->size - 1;
|
185 |
/* NOTE: we do not support wrapping */
|
186 |
/* XXX: as we cannot support really dynamic
|
187 |
mappings, we handle specific values as invalid
|
188 |
mappings. */
|
189 |
if (last_addr <= new_addr || new_addr == 0 || |
190 |
last_addr == -1) {
|
191 |
new_addr = -1;
|
192 |
} |
193 |
} else {
|
194 |
no_mem_map:
|
195 |
new_addr = -1;
|
196 |
} |
197 |
} |
198 |
/* now do the real mapping */
|
199 |
if (new_addr != r->addr) {
|
200 |
if (r->addr != -1) { |
201 |
if (r->type & PCI_ADDRESS_SPACE_IO) {
|
202 |
int class;
|
203 |
/* NOTE: specific hack for IDE in PC case:
|
204 |
only one byte must be mapped. */
|
205 |
class = d->config[0x0a] | (d->config[0x0b] << 8); |
206 |
if (class == 0x0101 && r->size == 4) { |
207 |
isa_unassign_ioport(r->addr + 2, 1); |
208 |
} else {
|
209 |
isa_unassign_ioport(r->addr, r->size); |
210 |
} |
211 |
} else {
|
212 |
cpu_register_physical_memory(r->addr + pci_mem_base, |
213 |
r->size, |
214 |
IO_MEM_UNASSIGNED); |
215 |
} |
216 |
} |
217 |
r->addr = new_addr; |
218 |
if (r->addr != -1) { |
219 |
r->map_func(d, i, r->addr, r->size, r->type); |
220 |
} |
221 |
} |
222 |
} |
223 |
} |
224 |
} |
225 |
|
226 |
uint32_t pci_default_read_config(PCIDevice *d, |
227 |
uint32_t address, int len)
|
228 |
{ |
229 |
uint32_t val; |
230 |
switch(len) {
|
231 |
case 1: |
232 |
val = d->config[address]; |
233 |
break;
|
234 |
case 2: |
235 |
val = le16_to_cpu(*(uint16_t *)(d->config + address)); |
236 |
break;
|
237 |
default:
|
238 |
case 4: |
239 |
val = le32_to_cpu(*(uint32_t *)(d->config + address)); |
240 |
break;
|
241 |
} |
242 |
return val;
|
243 |
} |
244 |
|
245 |
void pci_default_write_config(PCIDevice *d,
|
246 |
uint32_t address, uint32_t val, int len)
|
247 |
{ |
248 |
int can_write, i;
|
249 |
uint32_t end, addr; |
250 |
|
251 |
if (len == 4 && ((address >= 0x10 && address < 0x10 + 4 * 6) || |
252 |
(address >= 0x30 && address < 0x34))) { |
253 |
PCIIORegion *r; |
254 |
int reg;
|
255 |
|
256 |
if ( address >= 0x30 ) { |
257 |
reg = PCI_ROM_SLOT; |
258 |
}else{
|
259 |
reg = (address - 0x10) >> 2; |
260 |
} |
261 |
r = &d->io_regions[reg]; |
262 |
if (r->size == 0) |
263 |
goto default_config;
|
264 |
/* compute the stored value */
|
265 |
if (reg == PCI_ROM_SLOT) {
|
266 |
/* keep ROM enable bit */
|
267 |
val &= (~(r->size - 1)) | 1; |
268 |
} else {
|
269 |
val &= ~(r->size - 1);
|
270 |
val |= r->type; |
271 |
} |
272 |
*(uint32_t *)(d->config + address) = cpu_to_le32(val); |
273 |
pci_update_mappings(d); |
274 |
return;
|
275 |
} |
276 |
default_config:
|
277 |
/* not efficient, but simple */
|
278 |
addr = address; |
279 |
for(i = 0; i < len; i++) { |
280 |
/* default read/write accesses */
|
281 |
switch(d->config[0x0e]) { |
282 |
case 0x00: |
283 |
case 0x80: |
284 |
switch(addr) {
|
285 |
case 0x00: |
286 |
case 0x01: |
287 |
case 0x02: |
288 |
case 0x03: |
289 |
case 0x08: |
290 |
case 0x09: |
291 |
case 0x0a: |
292 |
case 0x0b: |
293 |
case 0x0e: |
294 |
case 0x10 ... 0x27: /* base */ |
295 |
case 0x30 ... 0x33: /* rom */ |
296 |
case 0x3d: |
297 |
can_write = 0;
|
298 |
break;
|
299 |
default:
|
300 |
can_write = 1;
|
301 |
break;
|
302 |
} |
303 |
break;
|
304 |
default:
|
305 |
case 0x01: |
306 |
switch(addr) {
|
307 |
case 0x00: |
308 |
case 0x01: |
309 |
case 0x02: |
310 |
case 0x03: |
311 |
case 0x08: |
312 |
case 0x09: |
313 |
case 0x0a: |
314 |
case 0x0b: |
315 |
case 0x0e: |
316 |
case 0x38 ... 0x3b: /* rom */ |
317 |
case 0x3d: |
318 |
can_write = 0;
|
319 |
break;
|
320 |
default:
|
321 |
can_write = 1;
|
322 |
break;
|
323 |
} |
324 |
break;
|
325 |
} |
326 |
if (can_write) {
|
327 |
d->config[addr] = val; |
328 |
} |
329 |
addr++; |
330 |
val >>= 8;
|
331 |
} |
332 |
|
333 |
end = address + len; |
334 |
if (end > PCI_COMMAND && address < (PCI_COMMAND + 2)) { |
335 |
/* if the command register is modified, we must modify the mappings */
|
336 |
pci_update_mappings(d); |
337 |
} |
338 |
} |
339 |
|
340 |
static void pci_data_write(void *opaque, uint32_t addr, |
341 |
uint32_t val, int len)
|
342 |
{ |
343 |
PCIBus *s = opaque; |
344 |
PCIDevice *pci_dev; |
345 |
int config_addr, bus_num;
|
346 |
|
347 |
#if defined(DEBUG_PCI) && 0 |
348 |
printf("pci_data_write: addr=%08x val=%08x len=%d\n",
|
349 |
s->config_reg, val, len); |
350 |
#endif
|
351 |
if (!(s->config_reg & (1 << 31))) { |
352 |
return;
|
353 |
} |
354 |
if ((s->config_reg & 0x3) != 0) { |
355 |
return;
|
356 |
} |
357 |
bus_num = (s->config_reg >> 16) & 0xff; |
358 |
if (bus_num != 0) |
359 |
return;
|
360 |
pci_dev = s->devices[(s->config_reg >> 8) & 0xff]; |
361 |
if (!pci_dev)
|
362 |
return;
|
363 |
config_addr = (s->config_reg & 0xfc) | (addr & 3); |
364 |
#if defined(DEBUG_PCI)
|
365 |
printf("pci_config_write: %s: addr=%02x val=%08x len=%d\n",
|
366 |
pci_dev->name, config_addr, val, len); |
367 |
#endif
|
368 |
pci_dev->config_write(pci_dev, config_addr, val, len); |
369 |
} |
370 |
|
371 |
static uint32_t pci_data_read(void *opaque, uint32_t addr, |
372 |
int len)
|
373 |
{ |
374 |
PCIBus *s = opaque; |
375 |
PCIDevice *pci_dev; |
376 |
int config_addr, bus_num;
|
377 |
uint32_t val; |
378 |
|
379 |
if (!(s->config_reg & (1 << 31))) |
380 |
goto fail;
|
381 |
if ((s->config_reg & 0x3) != 0) |
382 |
goto fail;
|
383 |
bus_num = (s->config_reg >> 16) & 0xff; |
384 |
if (bus_num != 0) |
385 |
goto fail;
|
386 |
pci_dev = s->devices[(s->config_reg >> 8) & 0xff]; |
387 |
if (!pci_dev) {
|
388 |
fail:
|
389 |
switch(len) {
|
390 |
case 1: |
391 |
val = 0xff;
|
392 |
break;
|
393 |
case 2: |
394 |
val = 0xffff;
|
395 |
break;
|
396 |
default:
|
397 |
case 4: |
398 |
val = 0xffffffff;
|
399 |
break;
|
400 |
} |
401 |
goto the_end;
|
402 |
} |
403 |
config_addr = (s->config_reg & 0xfc) | (addr & 3); |
404 |
val = pci_dev->config_read(pci_dev, config_addr, len); |
405 |
#if defined(DEBUG_PCI)
|
406 |
printf("pci_config_read: %s: addr=%02x val=%08x len=%d\n",
|
407 |
pci_dev->name, config_addr, val, len); |
408 |
#endif
|
409 |
the_end:
|
410 |
#if defined(DEBUG_PCI) && 0 |
411 |
printf("pci_data_read: addr=%08x val=%08x len=%d\n",
|
412 |
s->config_reg, val, len); |
413 |
#endif
|
414 |
return val;
|
415 |
} |
416 |
|
417 |
static void pci_data_writeb(void* opaque, uint32_t addr, uint32_t val) |
418 |
{ |
419 |
pci_data_write(opaque, addr, val, 1);
|
420 |
} |
421 |
|
422 |
static void pci_data_writew(void* opaque, uint32_t addr, uint32_t val) |
423 |
{ |
424 |
pci_data_write(opaque, addr, val, 2);
|
425 |
} |
426 |
|
427 |
static void pci_data_writel(void* opaque, uint32_t addr, uint32_t val) |
428 |
{ |
429 |
pci_data_write(opaque, addr, val, 4);
|
430 |
} |
431 |
|
432 |
static uint32_t pci_data_readb(void* opaque, uint32_t addr) |
433 |
{ |
434 |
return pci_data_read(opaque, addr, 1); |
435 |
} |
436 |
|
437 |
static uint32_t pci_data_readw(void* opaque, uint32_t addr) |
438 |
{ |
439 |
return pci_data_read(opaque, addr, 2); |
440 |
} |
441 |
|
442 |
static uint32_t pci_data_readl(void* opaque, uint32_t addr) |
443 |
{ |
444 |
return pci_data_read(opaque, addr, 4); |
445 |
} |
446 |
|
447 |
/* i440FX PCI bridge */
|
448 |
|
449 |
static void piix3_set_irq(PCIDevice *pci_dev, int irq_num, int level); |
450 |
|
451 |
PCIBus *i440fx_init(void)
|
452 |
{ |
453 |
PCIBus *s; |
454 |
PCIDevice *d; |
455 |
|
456 |
s = pci_register_bus(); |
457 |
s->set_irq = piix3_set_irq; |
458 |
|
459 |
register_ioport_write(0xcf8, 4, 4, pci_addr_writel, s); |
460 |
register_ioport_read(0xcf8, 4, 4, pci_addr_readl, s); |
461 |
|
462 |
register_ioport_write(0xcfc, 4, 1, pci_data_writeb, s); |
463 |
register_ioport_write(0xcfc, 4, 2, pci_data_writew, s); |
464 |
register_ioport_write(0xcfc, 4, 4, pci_data_writel, s); |
465 |
register_ioport_read(0xcfc, 4, 1, pci_data_readb, s); |
466 |
register_ioport_read(0xcfc, 4, 2, pci_data_readw, s); |
467 |
register_ioport_read(0xcfc, 4, 4, pci_data_readl, s); |
468 |
|
469 |
d = pci_register_device(s, "i440FX", sizeof(PCIDevice), 0, |
470 |
NULL, NULL); |
471 |
|
472 |
d->config[0x00] = 0x86; // vendor_id |
473 |
d->config[0x01] = 0x80; |
474 |
d->config[0x02] = 0x37; // device_id |
475 |
d->config[0x03] = 0x12; |
476 |
d->config[0x08] = 0x02; // revision |
477 |
d->config[0x0a] = 0x00; // class_sub = host2pci |
478 |
d->config[0x0b] = 0x06; // class_base = PCI_bridge |
479 |
d->config[0x0e] = 0x00; // header_type |
480 |
return s;
|
481 |
} |
482 |
|
483 |
/* PIIX3 PCI to ISA bridge */
|
484 |
|
485 |
typedef struct PIIX3State { |
486 |
PCIDevice dev; |
487 |
} PIIX3State; |
488 |
|
489 |
PIIX3State *piix3_state; |
490 |
|
491 |
/* return the global irq number corresponding to a given device irq
|
492 |
pin. We could also use the bus number to have a more precise
|
493 |
mapping. */
|
494 |
static inline int pci_slot_get_pirq(PCIDevice *pci_dev, int irq_num) |
495 |
{ |
496 |
int slot_addend;
|
497 |
slot_addend = (pci_dev->devfn >> 3) - 1; |
498 |
return (irq_num + slot_addend) & 3; |
499 |
} |
500 |
|
501 |
static inline int get_pci_irq_level(int irq_num) |
502 |
{ |
503 |
int pic_level;
|
504 |
#if (PCI_IRQ_WORDS == 2) |
505 |
pic_level = ((pci_irq_levels[irq_num][0] |
|
506 |
pci_irq_levels[irq_num][1]) != 0); |
507 |
#else
|
508 |
{ |
509 |
int i;
|
510 |
pic_level = 0;
|
511 |
for(i = 0; i < PCI_IRQ_WORDS; i++) { |
512 |
if (pci_irq_levels[irq_num][i]) {
|
513 |
pic_level = 1;
|
514 |
break;
|
515 |
} |
516 |
} |
517 |
} |
518 |
#endif
|
519 |
return pic_level;
|
520 |
} |
521 |
|
522 |
static void piix3_set_irq(PCIDevice *pci_dev, int irq_num, int level) |
523 |
{ |
524 |
int irq_index, shift, pic_irq, pic_level;
|
525 |
uint32_t *p; |
526 |
|
527 |
irq_num = pci_slot_get_pirq(pci_dev, irq_num); |
528 |
irq_index = pci_dev->irq_index; |
529 |
p = &pci_irq_levels[irq_num][irq_index >> 5];
|
530 |
shift = (irq_index & 0x1f);
|
531 |
*p = (*p & ~(1 << shift)) | (level << shift);
|
532 |
|
533 |
/* now we change the pic irq level according to the piix irq mappings */
|
534 |
/* XXX: optimize */
|
535 |
pic_irq = piix3_state->dev.config[0x60 + irq_num];
|
536 |
if (pic_irq < 16) { |
537 |
/* the pic level is the logical OR of all the PCI irqs mapped
|
538 |
to it */
|
539 |
pic_level = 0;
|
540 |
if (pic_irq == piix3_state->dev.config[0x60]) |
541 |
pic_level |= get_pci_irq_level(0);
|
542 |
if (pic_irq == piix3_state->dev.config[0x61]) |
543 |
pic_level |= get_pci_irq_level(1);
|
544 |
if (pic_irq == piix3_state->dev.config[0x62]) |
545 |
pic_level |= get_pci_irq_level(2);
|
546 |
if (pic_irq == piix3_state->dev.config[0x63]) |
547 |
pic_level |= get_pci_irq_level(3);
|
548 |
pic_set_irq(pic_irq, pic_level); |
549 |
} |
550 |
} |
551 |
|
552 |
static void piix3_reset(PIIX3State *d) |
553 |
{ |
554 |
uint8_t *pci_conf = d->dev.config; |
555 |
|
556 |
pci_conf[0x04] = 0x07; // master, memory and I/O |
557 |
pci_conf[0x05] = 0x00; |
558 |
pci_conf[0x06] = 0x00; |
559 |
pci_conf[0x07] = 0x02; // PCI_status_devsel_medium |
560 |
pci_conf[0x4c] = 0x4d; |
561 |
pci_conf[0x4e] = 0x03; |
562 |
pci_conf[0x4f] = 0x00; |
563 |
pci_conf[0x60] = 0x80; |
564 |
pci_conf[0x69] = 0x02; |
565 |
pci_conf[0x70] = 0x80; |
566 |
pci_conf[0x76] = 0x0c; |
567 |
pci_conf[0x77] = 0x0c; |
568 |
pci_conf[0x78] = 0x02; |
569 |
pci_conf[0x79] = 0x00; |
570 |
pci_conf[0x80] = 0x00; |
571 |
pci_conf[0x82] = 0x00; |
572 |
pci_conf[0xa0] = 0x08; |
573 |
pci_conf[0xa0] = 0x08; |
574 |
pci_conf[0xa2] = 0x00; |
575 |
pci_conf[0xa3] = 0x00; |
576 |
pci_conf[0xa4] = 0x00; |
577 |
pci_conf[0xa5] = 0x00; |
578 |
pci_conf[0xa6] = 0x00; |
579 |
pci_conf[0xa7] = 0x00; |
580 |
pci_conf[0xa8] = 0x0f; |
581 |
pci_conf[0xaa] = 0x00; |
582 |
pci_conf[0xab] = 0x00; |
583 |
pci_conf[0xac] = 0x00; |
584 |
pci_conf[0xae] = 0x00; |
585 |
} |
586 |
|
587 |
void piix3_init(PCIBus *bus)
|
588 |
{ |
589 |
PIIX3State *d; |
590 |
uint8_t *pci_conf; |
591 |
|
592 |
d = (PIIX3State *)pci_register_device(bus, "PIIX3", sizeof(PIIX3State), |
593 |
-1, NULL, NULL); |
594 |
register_savevm("PIIX3", 0, 1, generic_pci_save, generic_pci_load, d); |
595 |
|
596 |
piix3_state = d; |
597 |
pci_conf = d->dev.config; |
598 |
|
599 |
pci_conf[0x00] = 0x86; // Intel |
600 |
pci_conf[0x01] = 0x80; |
601 |
pci_conf[0x02] = 0x00; // 82371SB PIIX3 PCI-to-ISA bridge (Step A1) |
602 |
pci_conf[0x03] = 0x70; |
603 |
pci_conf[0x0a] = 0x01; // class_sub = PCI_ISA |
604 |
pci_conf[0x0b] = 0x06; // class_base = PCI_bridge |
605 |
pci_conf[0x0e] = 0x80; // header_type = PCI_multifunction, generic |
606 |
|
607 |
piix3_reset(d); |
608 |
} |
609 |
|
610 |
/* PREP pci init */
|
611 |
|
612 |
static inline void set_config(PCIBus *s, target_phys_addr_t addr) |
613 |
{ |
614 |
int devfn, i;
|
615 |
|
616 |
for(i = 0; i < 11; i++) { |
617 |
if ((addr & (1 << (11 + i))) != 0) |
618 |
break;
|
619 |
} |
620 |
devfn = ((addr >> 8) & 7) | (i << 3); |
621 |
s->config_reg = 0x80000000 | (addr & 0xfc) | (devfn << 8); |
622 |
} |
623 |
|
624 |
static void PPC_PCIIO_writeb (void *opaque, target_phys_addr_t addr, uint32_t val) |
625 |
{ |
626 |
PCIBus *s = opaque; |
627 |
set_config(s, addr); |
628 |
pci_data_write(s, addr, val, 1);
|
629 |
} |
630 |
|
631 |
static void PPC_PCIIO_writew (void *opaque, target_phys_addr_t addr, uint32_t val) |
632 |
{ |
633 |
PCIBus *s = opaque; |
634 |
set_config(s, addr); |
635 |
#ifdef TARGET_WORDS_BIGENDIAN
|
636 |
val = bswap16(val); |
637 |
#endif
|
638 |
pci_data_write(s, addr, val, 2);
|
639 |
} |
640 |
|
641 |
static void PPC_PCIIO_writel (void *opaque, target_phys_addr_t addr, uint32_t val) |
642 |
{ |
643 |
PCIBus *s = opaque; |
644 |
set_config(s, addr); |
645 |
#ifdef TARGET_WORDS_BIGENDIAN
|
646 |
val = bswap32(val); |
647 |
#endif
|
648 |
pci_data_write(s, addr, val, 4);
|
649 |
} |
650 |
|
651 |
static uint32_t PPC_PCIIO_readb (void *opaque, target_phys_addr_t addr) |
652 |
{ |
653 |
PCIBus *s = opaque; |
654 |
uint32_t val; |
655 |
set_config(s, addr); |
656 |
val = pci_data_read(s, addr, 1);
|
657 |
return val;
|
658 |
} |
659 |
|
660 |
static uint32_t PPC_PCIIO_readw (void *opaque, target_phys_addr_t addr) |
661 |
{ |
662 |
PCIBus *s = opaque; |
663 |
uint32_t val; |
664 |
set_config(s, addr); |
665 |
val = pci_data_read(s, addr, 2);
|
666 |
#ifdef TARGET_WORDS_BIGENDIAN
|
667 |
val = bswap16(val); |
668 |
#endif
|
669 |
return val;
|
670 |
} |
671 |
|
672 |
static uint32_t PPC_PCIIO_readl (void *opaque, target_phys_addr_t addr) |
673 |
{ |
674 |
PCIBus *s = opaque; |
675 |
uint32_t val; |
676 |
set_config(s, addr); |
677 |
val = pci_data_read(s, addr, 4);
|
678 |
#ifdef TARGET_WORDS_BIGENDIAN
|
679 |
val = bswap32(val); |
680 |
#endif
|
681 |
return val;
|
682 |
} |
683 |
|
684 |
static CPUWriteMemoryFunc *PPC_PCIIO_write[] = {
|
685 |
&PPC_PCIIO_writeb, |
686 |
&PPC_PCIIO_writew, |
687 |
&PPC_PCIIO_writel, |
688 |
}; |
689 |
|
690 |
static CPUReadMemoryFunc *PPC_PCIIO_read[] = {
|
691 |
&PPC_PCIIO_readb, |
692 |
&PPC_PCIIO_readw, |
693 |
&PPC_PCIIO_readl, |
694 |
}; |
695 |
|
696 |
static void prep_set_irq(PCIDevice *d, int irq_num, int level) |
697 |
{ |
698 |
/* XXX: we do not simulate the hardware - we rely on the BIOS to
|
699 |
set correctly for irq line field */
|
700 |
pic_set_irq(d->config[PCI_INTERRUPT_LINE], level); |
701 |
} |
702 |
|
703 |
PCIBus *pci_prep_init(void)
|
704 |
{ |
705 |
PCIBus *s; |
706 |
PCIDevice *d; |
707 |
int PPC_io_memory;
|
708 |
|
709 |
s = pci_register_bus(); |
710 |
s->set_irq = prep_set_irq; |
711 |
|
712 |
register_ioport_write(0xcf8, 4, 4, pci_addr_writel, s); |
713 |
register_ioport_read(0xcf8, 4, 4, pci_addr_readl, s); |
714 |
|
715 |
register_ioport_write(0xcfc, 4, 1, pci_data_writeb, s); |
716 |
register_ioport_write(0xcfc, 4, 2, pci_data_writew, s); |
717 |
register_ioport_write(0xcfc, 4, 4, pci_data_writel, s); |
718 |
register_ioport_read(0xcfc, 4, 1, pci_data_readb, s); |
719 |
register_ioport_read(0xcfc, 4, 2, pci_data_readw, s); |
720 |
register_ioport_read(0xcfc, 4, 4, pci_data_readl, s); |
721 |
|
722 |
PPC_io_memory = cpu_register_io_memory(0, PPC_PCIIO_read,
|
723 |
PPC_PCIIO_write, s); |
724 |
cpu_register_physical_memory(0x80800000, 0x00400000, PPC_io_memory); |
725 |
|
726 |
d = pci_register_device(s, "PREP PCI Bridge", sizeof(PCIDevice), 0, |
727 |
NULL, NULL); |
728 |
|
729 |
/* XXX: put correct IDs */
|
730 |
d->config[0x00] = 0x11; // vendor_id |
731 |
d->config[0x01] = 0x10; |
732 |
d->config[0x02] = 0x26; // device_id |
733 |
d->config[0x03] = 0x00; |
734 |
d->config[0x08] = 0x02; // revision |
735 |
d->config[0x0a] = 0x04; // class_sub = pci2pci |
736 |
d->config[0x0b] = 0x06; // class_base = PCI_bridge |
737 |
d->config[0x0e] = 0x01; // header_type |
738 |
return s;
|
739 |
} |
740 |
|
741 |
|
742 |
/* pmac pci init */
|
743 |
|
744 |
#if 0
|
745 |
/* Grackle PCI host */
|
746 |
static void pci_grackle_config_writel (void *opaque, target_phys_addr_t addr,
|
747 |
uint32_t val)
|
748 |
{
|
749 |
PCIBus *s = opaque;
|
750 |
#ifdef TARGET_WORDS_BIGENDIAN
|
751 |
val = bswap32(val);
|
752 |
#endif
|
753 |
s->config_reg = val; |
754 |
} |
755 |
|
756 |
static uint32_t pci_grackle_config_readl (void *opaque, target_phys_addr_t addr) |
757 |
{ |
758 |
PCIBus *s = opaque; |
759 |
uint32_t val; |
760 |
|
761 |
val = s->config_reg; |
762 |
#ifdef TARGET_WORDS_BIGENDIAN
|
763 |
val = bswap32(val); |
764 |
#endif
|
765 |
return val;
|
766 |
} |
767 |
|
768 |
static CPUWriteMemoryFunc *pci_grackle_config_write[] = {
|
769 |
&pci_grackle_config_writel, |
770 |
&pci_grackle_config_writel, |
771 |
&pci_grackle_config_writel, |
772 |
}; |
773 |
|
774 |
static CPUReadMemoryFunc *pci_grackle_config_read[] = {
|
775 |
&pci_grackle_config_readl, |
776 |
&pci_grackle_config_readl, |
777 |
&pci_grackle_config_readl, |
778 |
}; |
779 |
|
780 |
static void pci_grackle_writeb (void *opaque, target_phys_addr_t addr, |
781 |
uint32_t val) |
782 |
{ |
783 |
PCIBus *s = opaque; |
784 |
pci_data_write(s, addr, val, 1);
|
785 |
} |
786 |
|
787 |
static void pci_grackle_writew (void *opaque, target_phys_addr_t addr, |
788 |
uint32_t val) |
789 |
{ |
790 |
PCIBus *s = opaque; |
791 |
#ifdef TARGET_WORDS_BIGENDIAN
|
792 |
val = bswap16(val); |
793 |
#endif
|
794 |
pci_data_write(s, addr, val, 2);
|
795 |
} |
796 |
|
797 |
static void pci_grackle_writel (void *opaque, target_phys_addr_t addr, |
798 |
uint32_t val) |
799 |
{ |
800 |
PCIBus *s = opaque; |
801 |
#ifdef TARGET_WORDS_BIGENDIAN
|
802 |
val = bswap32(val); |
803 |
#endif
|
804 |
pci_data_write(s, addr, val, 4);
|
805 |
} |
806 |
|
807 |
static uint32_t pci_grackle_readb (void *opaque, target_phys_addr_t addr) |
808 |
{ |
809 |
PCIBus *s = opaque; |
810 |
uint32_t val; |
811 |
val = pci_data_read(s, addr, 1);
|
812 |
return val;
|
813 |
} |
814 |
|
815 |
static uint32_t pci_grackle_readw (void *opaque, target_phys_addr_t addr) |
816 |
{ |
817 |
PCIBus *s = opaque; |
818 |
uint32_t val; |
819 |
val = pci_data_read(s, addr, 2);
|
820 |
#ifdef TARGET_WORDS_BIGENDIAN
|
821 |
val = bswap16(val); |
822 |
#endif
|
823 |
return val;
|
824 |
} |
825 |
|
826 |
static uint32_t pci_grackle_readl (void *opaque, target_phys_addr_t addr) |
827 |
{ |
828 |
PCIBus *s = opaque; |
829 |
uint32_t val; |
830 |
|
831 |
val = pci_data_read(s, addr, 4);
|
832 |
#ifdef TARGET_WORDS_BIGENDIAN
|
833 |
val = bswap32(val); |
834 |
#endif
|
835 |
return val;
|
836 |
} |
837 |
|
838 |
static CPUWriteMemoryFunc *pci_grackle_write[] = {
|
839 |
&pci_grackle_writeb, |
840 |
&pci_grackle_writew, |
841 |
&pci_grackle_writel, |
842 |
}; |
843 |
|
844 |
static CPUReadMemoryFunc *pci_grackle_read[] = {
|
845 |
&pci_grackle_readb, |
846 |
&pci_grackle_readw, |
847 |
&pci_grackle_readl, |
848 |
}; |
849 |
#endif
|
850 |
|
851 |
/* Uninorth PCI host (for all Mac99 and newer machines */
|
852 |
static void pci_unin_main_config_writel (void *opaque, target_phys_addr_t addr, |
853 |
uint32_t val) |
854 |
{ |
855 |
PCIBus *s = opaque; |
856 |
int i;
|
857 |
|
858 |
#ifdef TARGET_WORDS_BIGENDIAN
|
859 |
val = bswap32(val); |
860 |
#endif
|
861 |
|
862 |
for (i = 11; i < 32; i++) { |
863 |
if ((val & (1 << i)) != 0) |
864 |
break;
|
865 |
} |
866 |
#if 0
|
867 |
s->config_reg = 0x80000000 | (1 << 16) | (val & 0x7FC) | (i << 11);
|
868 |
#else
|
869 |
s->config_reg = 0x80000000 | (0 << 16) | (val & 0x7FC) | (i << 11); |
870 |
#endif
|
871 |
} |
872 |
|
873 |
static uint32_t pci_unin_main_config_readl (void *opaque, |
874 |
target_phys_addr_t addr) |
875 |
{ |
876 |
PCIBus *s = opaque; |
877 |
uint32_t val; |
878 |
int devfn;
|
879 |
|
880 |
devfn = (s->config_reg >> 8) & 0xFF; |
881 |
val = (1 << (devfn >> 3)) | ((devfn & 0x07) << 8) | (s->config_reg & 0xFC); |
882 |
#ifdef TARGET_WORDS_BIGENDIAN
|
883 |
val = bswap32(val); |
884 |
#endif
|
885 |
|
886 |
return val;
|
887 |
} |
888 |
|
889 |
static CPUWriteMemoryFunc *pci_unin_main_config_write[] = {
|
890 |
&pci_unin_main_config_writel, |
891 |
&pci_unin_main_config_writel, |
892 |
&pci_unin_main_config_writel, |
893 |
}; |
894 |
|
895 |
static CPUReadMemoryFunc *pci_unin_main_config_read[] = {
|
896 |
&pci_unin_main_config_readl, |
897 |
&pci_unin_main_config_readl, |
898 |
&pci_unin_main_config_readl, |
899 |
}; |
900 |
|
901 |
static void pci_unin_main_writeb (void *opaque, target_phys_addr_t addr, |
902 |
uint32_t val) |
903 |
{ |
904 |
PCIBus *s = opaque; |
905 |
pci_data_write(s, addr & 7, val, 1); |
906 |
} |
907 |
|
908 |
static void pci_unin_main_writew (void *opaque, target_phys_addr_t addr, |
909 |
uint32_t val) |
910 |
{ |
911 |
PCIBus *s = opaque; |
912 |
#ifdef TARGET_WORDS_BIGENDIAN
|
913 |
val = bswap16(val); |
914 |
#endif
|
915 |
pci_data_write(s, addr & 7, val, 2); |
916 |
} |
917 |
|
918 |
static void pci_unin_main_writel (void *opaque, target_phys_addr_t addr, |
919 |
uint32_t val) |
920 |
{ |
921 |
PCIBus *s = opaque; |
922 |
#ifdef TARGET_WORDS_BIGENDIAN
|
923 |
val = bswap32(val); |
924 |
#endif
|
925 |
pci_data_write(s, addr & 7, val, 4); |
926 |
} |
927 |
|
928 |
static uint32_t pci_unin_main_readb (void *opaque, target_phys_addr_t addr) |
929 |
{ |
930 |
PCIBus *s = opaque; |
931 |
uint32_t val; |
932 |
|
933 |
val = pci_data_read(s, addr & 7, 1); |
934 |
|
935 |
return val;
|
936 |
} |
937 |
|
938 |
static uint32_t pci_unin_main_readw (void *opaque, target_phys_addr_t addr) |
939 |
{ |
940 |
PCIBus *s = opaque; |
941 |
uint32_t val; |
942 |
|
943 |
val = pci_data_read(s, addr & 7, 2); |
944 |
#ifdef TARGET_WORDS_BIGENDIAN
|
945 |
val = bswap16(val); |
946 |
#endif
|
947 |
|
948 |
return val;
|
949 |
} |
950 |
|
951 |
static uint32_t pci_unin_main_readl (void *opaque, target_phys_addr_t addr) |
952 |
{ |
953 |
PCIBus *s = opaque; |
954 |
uint32_t val; |
955 |
|
956 |
val = pci_data_read(s, addr, 4);
|
957 |
#ifdef TARGET_WORDS_BIGENDIAN
|
958 |
val = bswap32(val); |
959 |
#endif
|
960 |
|
961 |
return val;
|
962 |
} |
963 |
|
964 |
static CPUWriteMemoryFunc *pci_unin_main_write[] = {
|
965 |
&pci_unin_main_writeb, |
966 |
&pci_unin_main_writew, |
967 |
&pci_unin_main_writel, |
968 |
}; |
969 |
|
970 |
static CPUReadMemoryFunc *pci_unin_main_read[] = {
|
971 |
&pci_unin_main_readb, |
972 |
&pci_unin_main_readw, |
973 |
&pci_unin_main_readl, |
974 |
}; |
975 |
|
976 |
#if 0
|
977 |
|
978 |
static void pci_unin_config_writel (void *opaque, target_phys_addr_t addr,
|
979 |
uint32_t val)
|
980 |
{
|
981 |
PCIBus *s = opaque;
|
982 |
|
983 |
#ifdef TARGET_WORDS_BIGENDIAN
|
984 |
val = bswap32(val);
|
985 |
#endif
|
986 |
s->config_reg = 0x80000000 | (val & ~0x00000001); |
987 |
} |
988 |
|
989 |
static uint32_t pci_unin_config_readl (void *opaque, |
990 |
target_phys_addr_t addr) |
991 |
{ |
992 |
PCIBus *s = opaque; |
993 |
uint32_t val; |
994 |
|
995 |
val = (s->config_reg | 0x00000001) & ~0x80000000; |
996 |
#ifdef TARGET_WORDS_BIGENDIAN
|
997 |
val = bswap32(val); |
998 |
#endif
|
999 |
|
1000 |
return val;
|
1001 |
} |
1002 |
|
1003 |
static CPUWriteMemoryFunc *pci_unin_config_write[] = {
|
1004 |
&pci_unin_config_writel, |
1005 |
&pci_unin_config_writel, |
1006 |
&pci_unin_config_writel, |
1007 |
}; |
1008 |
|
1009 |
static CPUReadMemoryFunc *pci_unin_config_read[] = {
|
1010 |
&pci_unin_config_readl, |
1011 |
&pci_unin_config_readl, |
1012 |
&pci_unin_config_readl, |
1013 |
}; |
1014 |
|
1015 |
static void pci_unin_writeb (void *opaque, target_phys_addr_t addr, |
1016 |
uint32_t val) |
1017 |
{ |
1018 |
PCIBus *s = opaque; |
1019 |
pci_data_write(s, addr & 3, val, 1); |
1020 |
} |
1021 |
|
1022 |
static void pci_unin_writew (void *opaque, target_phys_addr_t addr, |
1023 |
uint32_t val) |
1024 |
{ |
1025 |
PCIBus *s = opaque; |
1026 |
#ifdef TARGET_WORDS_BIGENDIAN
|
1027 |
val = bswap16(val); |
1028 |
#endif
|
1029 |
pci_data_write(s, addr & 3, val, 2); |
1030 |
} |
1031 |
|
1032 |
static void pci_unin_writel (void *opaque, target_phys_addr_t addr, |
1033 |
uint32_t val) |
1034 |
{ |
1035 |
PCIBus *s = opaque; |
1036 |
#ifdef TARGET_WORDS_BIGENDIAN
|
1037 |
val = bswap32(val); |
1038 |
#endif
|
1039 |
pci_data_write(s, addr & 3, val, 4); |
1040 |
} |
1041 |
|
1042 |
static uint32_t pci_unin_readb (void *opaque, target_phys_addr_t addr) |
1043 |
{ |
1044 |
PCIBus *s = opaque; |
1045 |
uint32_t val; |
1046 |
|
1047 |
val = pci_data_read(s, addr & 3, 1); |
1048 |
|
1049 |
return val;
|
1050 |
} |
1051 |
|
1052 |
static uint32_t pci_unin_readw (void *opaque, target_phys_addr_t addr) |
1053 |
{ |
1054 |
PCIBus *s = opaque; |
1055 |
uint32_t val; |
1056 |
|
1057 |
val = pci_data_read(s, addr & 3, 2); |
1058 |
#ifdef TARGET_WORDS_BIGENDIAN
|
1059 |
val = bswap16(val); |
1060 |
#endif
|
1061 |
|
1062 |
return val;
|
1063 |
} |
1064 |
|
1065 |
static uint32_t pci_unin_readl (void *opaque, target_phys_addr_t addr) |
1066 |
{ |
1067 |
PCIBus *s = opaque; |
1068 |
uint32_t val; |
1069 |
|
1070 |
val = pci_data_read(s, addr & 3, 4); |
1071 |
#ifdef TARGET_WORDS_BIGENDIAN
|
1072 |
val = bswap32(val); |
1073 |
#endif
|
1074 |
|
1075 |
return val;
|
1076 |
} |
1077 |
|
1078 |
static CPUWriteMemoryFunc *pci_unin_write[] = {
|
1079 |
&pci_unin_writeb, |
1080 |
&pci_unin_writew, |
1081 |
&pci_unin_writel, |
1082 |
}; |
1083 |
|
1084 |
static CPUReadMemoryFunc *pci_unin_read[] = {
|
1085 |
&pci_unin_readb, |
1086 |
&pci_unin_readw, |
1087 |
&pci_unin_readl, |
1088 |
}; |
1089 |
#endif
|
1090 |
|
1091 |
static void pmac_set_irq(PCIDevice *d, int irq_num, int level) |
1092 |
{ |
1093 |
openpic_t *openpic; |
1094 |
/* XXX: we do not simulate the hardware - we rely on the BIOS to
|
1095 |
set correctly for irq line field */
|
1096 |
openpic = d->bus->openpic; |
1097 |
#ifdef TARGET_PPC
|
1098 |
if (openpic)
|
1099 |
openpic_set_irq(openpic, d->config[PCI_INTERRUPT_LINE], level); |
1100 |
#endif
|
1101 |
} |
1102 |
|
1103 |
void pci_pmac_set_openpic(PCIBus *bus, openpic_t *openpic)
|
1104 |
{ |
1105 |
bus->openpic = openpic; |
1106 |
} |
1107 |
|
1108 |
PCIBus *pci_pmac_init(void)
|
1109 |
{ |
1110 |
PCIBus *s; |
1111 |
PCIDevice *d; |
1112 |
int pci_mem_config, pci_mem_data;
|
1113 |
|
1114 |
/* Use values found on a real PowerMac */
|
1115 |
/* Uninorth main bus */
|
1116 |
s = pci_register_bus(); |
1117 |
s->set_irq = pmac_set_irq; |
1118 |
|
1119 |
pci_mem_config = cpu_register_io_memory(0, pci_unin_main_config_read,
|
1120 |
pci_unin_main_config_write, s); |
1121 |
pci_mem_data = cpu_register_io_memory(0, pci_unin_main_read,
|
1122 |
pci_unin_main_write, s); |
1123 |
cpu_register_physical_memory(0xf2800000, 0x1000, pci_mem_config); |
1124 |
cpu_register_physical_memory(0xf2c00000, 0x1000, pci_mem_data); |
1125 |
s->devfn_min = 11 << 3; |
1126 |
d = pci_register_device(s, "Uni-north main", sizeof(PCIDevice), |
1127 |
11 << 3, NULL, NULL); |
1128 |
d->config[0x00] = 0x6b; // vendor_id : Apple |
1129 |
d->config[0x01] = 0x10; |
1130 |
d->config[0x02] = 0x1F; // device_id |
1131 |
d->config[0x03] = 0x00; |
1132 |
d->config[0x08] = 0x00; // revision |
1133 |
d->config[0x0A] = 0x00; // class_sub = pci host |
1134 |
d->config[0x0B] = 0x06; // class_base = PCI_bridge |
1135 |
d->config[0x0C] = 0x08; // cache_line_size |
1136 |
d->config[0x0D] = 0x10; // latency_timer |
1137 |
d->config[0x0E] = 0x00; // header_type |
1138 |
d->config[0x34] = 0x00; // capabilities_pointer |
1139 |
|
1140 |
#if 0 // XXX: not activated as PPC BIOS doesn't handle mutiple buses properly
|
1141 |
/* pci-to-pci bridge */
|
1142 |
d = pci_register_device("Uni-north bridge", sizeof(PCIDevice), 0, 13 << 3,
|
1143 |
NULL, NULL);
|
1144 |
d->config[0x00] = 0x11; // vendor_id : TI
|
1145 |
d->config[0x01] = 0x10;
|
1146 |
d->config[0x02] = 0x26; // device_id
|
1147 |
d->config[0x03] = 0x00;
|
1148 |
d->config[0x08] = 0x05; // revision
|
1149 |
d->config[0x0A] = 0x04; // class_sub = pci2pci
|
1150 |
d->config[0x0B] = 0x06; // class_base = PCI_bridge
|
1151 |
d->config[0x0C] = 0x08; // cache_line_size
|
1152 |
d->config[0x0D] = 0x20; // latency_timer
|
1153 |
d->config[0x0E] = 0x01; // header_type
|
1154 |
|
1155 |
d->config[0x18] = 0x01; // primary_bus
|
1156 |
d->config[0x19] = 0x02; // secondary_bus
|
1157 |
d->config[0x1A] = 0x02; // subordinate_bus
|
1158 |
d->config[0x1B] = 0x20; // secondary_latency_timer
|
1159 |
d->config[0x1C] = 0x11; // io_base
|
1160 |
d->config[0x1D] = 0x01; // io_limit
|
1161 |
d->config[0x20] = 0x00; // memory_base
|
1162 |
d->config[0x21] = 0x80;
|
1163 |
d->config[0x22] = 0x00; // memory_limit
|
1164 |
d->config[0x23] = 0x80;
|
1165 |
d->config[0x24] = 0x01; // prefetchable_memory_base
|
1166 |
d->config[0x25] = 0x80;
|
1167 |
d->config[0x26] = 0xF1; // prefectchable_memory_limit
|
1168 |
d->config[0x27] = 0x7F;
|
1169 |
// d->config[0x34] = 0xdc // capabilities_pointer
|
1170 |
#endif
|
1171 |
#if 0 // XXX: not needed for now
|
1172 |
/* Uninorth AGP bus */
|
1173 |
s = &pci_bridge[1];
|
1174 |
pci_mem_config = cpu_register_io_memory(0, pci_unin_config_read,
|
1175 |
pci_unin_config_write, s);
|
1176 |
pci_mem_data = cpu_register_io_memory(0, pci_unin_read,
|
1177 |
pci_unin_write, s);
|
1178 |
cpu_register_physical_memory(0xf0800000, 0x1000, pci_mem_config);
|
1179 |
cpu_register_physical_memory(0xf0c00000, 0x1000, pci_mem_data);
|
1180 |
|
1181 |
d = pci_register_device("Uni-north AGP", sizeof(PCIDevice), 0, 11 << 3,
|
1182 |
NULL, NULL);
|
1183 |
d->config[0x00] = 0x6b; // vendor_id : Apple
|
1184 |
d->config[0x01] = 0x10;
|
1185 |
d->config[0x02] = 0x20; // device_id
|
1186 |
d->config[0x03] = 0x00;
|
1187 |
d->config[0x08] = 0x00; // revision
|
1188 |
d->config[0x0A] = 0x00; // class_sub = pci host
|
1189 |
d->config[0x0B] = 0x06; // class_base = PCI_bridge
|
1190 |
d->config[0x0C] = 0x08; // cache_line_size
|
1191 |
d->config[0x0D] = 0x10; // latency_timer
|
1192 |
d->config[0x0E] = 0x00; // header_type
|
1193 |
// d->config[0x34] = 0x80; // capabilities_pointer
|
1194 |
#endif
|
1195 |
|
1196 |
#if 0 // XXX: not needed for now
|
1197 |
/* Uninorth internal bus */
|
1198 |
s = &pci_bridge[2];
|
1199 |
pci_mem_config = cpu_register_io_memory(0, pci_unin_config_read,
|
1200 |
pci_unin_config_write, s);
|
1201 |
pci_mem_data = cpu_register_io_memory(0, pci_unin_read,
|
1202 |
pci_unin_write, s);
|
1203 |
cpu_register_physical_memory(0xf4800000, 0x1000, pci_mem_config);
|
1204 |
cpu_register_physical_memory(0xf4c00000, 0x1000, pci_mem_data);
|
1205 |
|
1206 |
d = pci_register_device("Uni-north internal", sizeof(PCIDevice),
|
1207 |
3, 11 << 3, NULL, NULL);
|
1208 |
d->config[0x00] = 0x6b; // vendor_id : Apple
|
1209 |
d->config[0x01] = 0x10;
|
1210 |
d->config[0x02] = 0x1E; // device_id
|
1211 |
d->config[0x03] = 0x00;
|
1212 |
d->config[0x08] = 0x00; // revision
|
1213 |
d->config[0x0A] = 0x00; // class_sub = pci host
|
1214 |
d->config[0x0B] = 0x06; // class_base = PCI_bridge
|
1215 |
d->config[0x0C] = 0x08; // cache_line_size
|
1216 |
d->config[0x0D] = 0x10; // latency_timer
|
1217 |
d->config[0x0E] = 0x00; // header_type
|
1218 |
d->config[0x34] = 0x00; // capabilities_pointer
|
1219 |
#endif
|
1220 |
|
1221 |
#if 0 // Grackle ?
|
1222 |
/* same values as PearPC - check this */
|
1223 |
d->config[0x00] = 0x11; // vendor_id
|
1224 |
d->config[0x01] = 0x10;
|
1225 |
d->config[0x02] = 0x26; // device_id
|
1226 |
d->config[0x03] = 0x00;
|
1227 |
d->config[0x08] = 0x02; // revision
|
1228 |
d->config[0x0a] = 0x04; // class_sub = pci2pci
|
1229 |
d->config[0x0b] = 0x06; // class_base = PCI_bridge
|
1230 |
d->config[0x0e] = 0x01; // header_type
|
1231 |
|
1232 |
d->config[0x18] = 0x0; // primary_bus
|
1233 |
d->config[0x19] = 0x1; // secondary_bus
|
1234 |
d->config[0x1a] = 0x1; // subordinate_bus
|
1235 |
d->config[0x1c] = 0x10; // io_base
|
1236 |
d->config[0x1d] = 0x20; // io_limit
|
1237 |
|
1238 |
d->config[0x20] = 0x80; // memory_base
|
1239 |
d->config[0x21] = 0x80;
|
1240 |
d->config[0x22] = 0x90; // memory_limit
|
1241 |
d->config[0x23] = 0x80;
|
1242 |
|
1243 |
d->config[0x24] = 0x00; // prefetchable_memory_base
|
1244 |
d->config[0x25] = 0x84;
|
1245 |
d->config[0x26] = 0x00; // prefetchable_memory_limit
|
1246 |
d->config[0x27] = 0x85;
|
1247 |
#endif
|
1248 |
return s;
|
1249 |
} |
1250 |
|
1251 |
/***********************************************************/
|
1252 |
/* generic PCI irq support */
|
1253 |
|
1254 |
/* 0 <= irq_num <= 3. level must be 0 or 1 */
|
1255 |
void pci_set_irq(PCIDevice *pci_dev, int irq_num, int level) |
1256 |
{ |
1257 |
PCIBus *bus = pci_dev->bus; |
1258 |
bus->set_irq(pci_dev, irq_num, level); |
1259 |
} |
1260 |
|
1261 |
/***********************************************************/
|
1262 |
/* monitor info on PCI */
|
1263 |
|
1264 |
static void pci_info_device(PCIDevice *d) |
1265 |
{ |
1266 |
int i, class;
|
1267 |
PCIIORegion *r; |
1268 |
|
1269 |
term_printf(" Bus %2d, device %3d, function %d:\n",
|
1270 |
d->bus->bus_num, d->devfn >> 3, d->devfn & 7); |
1271 |
class = le16_to_cpu(*((uint16_t *)(d->config + PCI_CLASS_DEVICE))); |
1272 |
term_printf(" ");
|
1273 |
switch(class) {
|
1274 |
case 0x0101: |
1275 |
term_printf("IDE controller");
|
1276 |
break;
|
1277 |
case 0x0200: |
1278 |
term_printf("Ethernet controller");
|
1279 |
break;
|
1280 |
case 0x0300: |
1281 |
term_printf("VGA controller");
|
1282 |
break;
|
1283 |
default:
|
1284 |
term_printf("Class %04x", class);
|
1285 |
break;
|
1286 |
} |
1287 |
term_printf(": PCI device %04x:%04x\n",
|
1288 |
le16_to_cpu(*((uint16_t *)(d->config + PCI_VENDOR_ID))), |
1289 |
le16_to_cpu(*((uint16_t *)(d->config + PCI_DEVICE_ID)))); |
1290 |
|
1291 |
if (d->config[PCI_INTERRUPT_PIN] != 0) { |
1292 |
term_printf(" IRQ %d.\n", d->config[PCI_INTERRUPT_LINE]);
|
1293 |
} |
1294 |
for(i = 0;i < PCI_NUM_REGIONS; i++) { |
1295 |
r = &d->io_regions[i]; |
1296 |
if (r->size != 0) { |
1297 |
term_printf(" BAR%d: ", i);
|
1298 |
if (r->type & PCI_ADDRESS_SPACE_IO) {
|
1299 |
term_printf("I/O at 0x%04x [0x%04x].\n",
|
1300 |
r->addr, r->addr + r->size - 1);
|
1301 |
} else {
|
1302 |
term_printf("32 bit memory at 0x%08x [0x%08x].\n",
|
1303 |
r->addr, r->addr + r->size - 1);
|
1304 |
} |
1305 |
} |
1306 |
} |
1307 |
} |
1308 |
|
1309 |
void pci_info(void) |
1310 |
{ |
1311 |
PCIBus *bus = first_bus; |
1312 |
PCIDevice *d; |
1313 |
int devfn;
|
1314 |
|
1315 |
if (bus) {
|
1316 |
for(devfn = 0; devfn < 256; devfn++) { |
1317 |
d = bus->devices[devfn]; |
1318 |
if (d)
|
1319 |
pci_info_device(d); |
1320 |
} |
1321 |
} |
1322 |
} |
1323 |
|
1324 |
/***********************************************************/
|
1325 |
/* XXX: the following should be moved to the PC BIOS */
|
1326 |
|
1327 |
static __attribute__((unused)) uint32_t isa_inb(uint32_t addr)
|
1328 |
{ |
1329 |
return cpu_inb(cpu_single_env, addr);
|
1330 |
} |
1331 |
|
1332 |
static void isa_outb(uint32_t val, uint32_t addr) |
1333 |
{ |
1334 |
cpu_outb(cpu_single_env, addr, val); |
1335 |
} |
1336 |
|
1337 |
static __attribute__((unused)) uint32_t isa_inw(uint32_t addr)
|
1338 |
{ |
1339 |
return cpu_inw(cpu_single_env, addr);
|
1340 |
} |
1341 |
|
1342 |
static __attribute__((unused)) void isa_outw(uint32_t val, uint32_t addr) |
1343 |
{ |
1344 |
cpu_outw(cpu_single_env, addr, val); |
1345 |
} |
1346 |
|
1347 |
static __attribute__((unused)) uint32_t isa_inl(uint32_t addr)
|
1348 |
{ |
1349 |
return cpu_inl(cpu_single_env, addr);
|
1350 |
} |
1351 |
|
1352 |
static __attribute__((unused)) void isa_outl(uint32_t val, uint32_t addr) |
1353 |
{ |
1354 |
cpu_outl(cpu_single_env, addr, val); |
1355 |
} |
1356 |
|
1357 |
static void pci_config_writel(PCIDevice *d, uint32_t addr, uint32_t val) |
1358 |
{ |
1359 |
PCIBus *s = d->bus; |
1360 |
s->config_reg = 0x80000000 | (s->bus_num << 16) | |
1361 |
(d->devfn << 8) | addr;
|
1362 |
pci_data_write(s, 0, val, 4); |
1363 |
} |
1364 |
|
1365 |
static void pci_config_writew(PCIDevice *d, uint32_t addr, uint32_t val) |
1366 |
{ |
1367 |
PCIBus *s = d->bus; |
1368 |
s->config_reg = 0x80000000 | (s->bus_num << 16) | |
1369 |
(d->devfn << 8) | (addr & ~3); |
1370 |
pci_data_write(s, addr & 3, val, 2); |
1371 |
} |
1372 |
|
1373 |
static void pci_config_writeb(PCIDevice *d, uint32_t addr, uint32_t val) |
1374 |
{ |
1375 |
PCIBus *s = d->bus; |
1376 |
s->config_reg = 0x80000000 | (s->bus_num << 16) | |
1377 |
(d->devfn << 8) | (addr & ~3); |
1378 |
pci_data_write(s, addr & 3, val, 1); |
1379 |
} |
1380 |
|
1381 |
static __attribute__((unused)) uint32_t pci_config_readl(PCIDevice *d, uint32_t addr)
|
1382 |
{ |
1383 |
PCIBus *s = d->bus; |
1384 |
s->config_reg = 0x80000000 | (s->bus_num << 16) | |
1385 |
(d->devfn << 8) | addr;
|
1386 |
return pci_data_read(s, 0, 4); |
1387 |
} |
1388 |
|
1389 |
static uint32_t pci_config_readw(PCIDevice *d, uint32_t addr)
|
1390 |
{ |
1391 |
PCIBus *s = d->bus; |
1392 |
s->config_reg = 0x80000000 | (s->bus_num << 16) | |
1393 |
(d->devfn << 8) | (addr & ~3); |
1394 |
return pci_data_read(s, addr & 3, 2); |
1395 |
} |
1396 |
|
1397 |
static uint32_t pci_config_readb(PCIDevice *d, uint32_t addr)
|
1398 |
{ |
1399 |
PCIBus *s = d->bus; |
1400 |
s->config_reg = 0x80000000 | (s->bus_num << 16) | |
1401 |
(d->devfn << 8) | (addr & ~3); |
1402 |
return pci_data_read(s, addr & 3, 1); |
1403 |
} |
1404 |
|
1405 |
static uint32_t pci_bios_io_addr;
|
1406 |
static uint32_t pci_bios_mem_addr;
|
1407 |
/* host irqs corresponding to PCI irqs A-D */
|
1408 |
static uint8_t pci_irqs[4] = { 11, 9, 11, 9 }; |
1409 |
|
1410 |
static void pci_set_io_region_addr(PCIDevice *d, int region_num, uint32_t addr) |
1411 |
{ |
1412 |
PCIIORegion *r; |
1413 |
uint16_t cmd; |
1414 |
uint32_t ofs; |
1415 |
|
1416 |
if ( region_num == PCI_ROM_SLOT ) {
|
1417 |
ofs = 0x30;
|
1418 |
}else{
|
1419 |
ofs = 0x10 + region_num * 4; |
1420 |
} |
1421 |
|
1422 |
pci_config_writel(d, ofs, addr); |
1423 |
r = &d->io_regions[region_num]; |
1424 |
|
1425 |
/* enable memory mappings */
|
1426 |
cmd = pci_config_readw(d, PCI_COMMAND); |
1427 |
if ( region_num == PCI_ROM_SLOT )
|
1428 |
cmd |= 2;
|
1429 |
else if (r->type & PCI_ADDRESS_SPACE_IO) |
1430 |
cmd |= 1;
|
1431 |
else
|
1432 |
cmd |= 2;
|
1433 |
pci_config_writew(d, PCI_COMMAND, cmd); |
1434 |
} |
1435 |
|
1436 |
static void pci_bios_init_device(PCIDevice *d) |
1437 |
{ |
1438 |
int class;
|
1439 |
PCIIORegion *r; |
1440 |
uint32_t *paddr; |
1441 |
int i, pin, pic_irq, vendor_id, device_id;
|
1442 |
|
1443 |
class = pci_config_readw(d, PCI_CLASS_DEVICE); |
1444 |
vendor_id = pci_config_readw(d, PCI_VENDOR_ID); |
1445 |
device_id = pci_config_readw(d, PCI_DEVICE_ID); |
1446 |
switch(class) {
|
1447 |
case 0x0101: |
1448 |
if (vendor_id == 0x8086 && device_id == 0x7010) { |
1449 |
/* PIIX3 IDE */
|
1450 |
pci_config_writew(d, 0x40, 0x8000); // enable IDE0 |
1451 |
pci_config_writew(d, 0x42, 0x8000); // enable IDE1 |
1452 |
goto default_map;
|
1453 |
} else {
|
1454 |
/* IDE: we map it as in ISA mode */
|
1455 |
pci_set_io_region_addr(d, 0, 0x1f0); |
1456 |
pci_set_io_region_addr(d, 1, 0x3f4); |
1457 |
pci_set_io_region_addr(d, 2, 0x170); |
1458 |
pci_set_io_region_addr(d, 3, 0x374); |
1459 |
} |
1460 |
break;
|
1461 |
case 0x0300: |
1462 |
if (vendor_id != 0x1234) |
1463 |
goto default_map;
|
1464 |
/* VGA: map frame buffer to default Bochs VBE address */
|
1465 |
pci_set_io_region_addr(d, 0, 0xE0000000); |
1466 |
break;
|
1467 |
case 0x0800: |
1468 |
/* PIC */
|
1469 |
vendor_id = pci_config_readw(d, PCI_VENDOR_ID); |
1470 |
device_id = pci_config_readw(d, PCI_DEVICE_ID); |
1471 |
if (vendor_id == 0x1014) { |
1472 |
/* IBM */
|
1473 |
if (device_id == 0x0046 || device_id == 0xFFFF) { |
1474 |
/* MPIC & MPIC2 */
|
1475 |
pci_set_io_region_addr(d, 0, 0x80800000 + 0x00040000); |
1476 |
} |
1477 |
} |
1478 |
break;
|
1479 |
case 0xff00: |
1480 |
if (vendor_id == 0x0106b && |
1481 |
(device_id == 0x0017 || device_id == 0x0022)) { |
1482 |
/* macio bridge */
|
1483 |
pci_set_io_region_addr(d, 0, 0x80800000); |
1484 |
} |
1485 |
break;
|
1486 |
default:
|
1487 |
default_map:
|
1488 |
/* default memory mappings */
|
1489 |
for(i = 0; i < PCI_NUM_REGIONS; i++) { |
1490 |
r = &d->io_regions[i]; |
1491 |
if (r->size) {
|
1492 |
if (r->type & PCI_ADDRESS_SPACE_IO)
|
1493 |
paddr = &pci_bios_io_addr; |
1494 |
else
|
1495 |
paddr = &pci_bios_mem_addr; |
1496 |
*paddr = (*paddr + r->size - 1) & ~(r->size - 1); |
1497 |
pci_set_io_region_addr(d, i, *paddr); |
1498 |
*paddr += r->size; |
1499 |
} |
1500 |
} |
1501 |
break;
|
1502 |
} |
1503 |
|
1504 |
/* map the interrupt */
|
1505 |
pin = pci_config_readb(d, PCI_INTERRUPT_PIN); |
1506 |
if (pin != 0) { |
1507 |
pin = pci_slot_get_pirq(d, pin - 1);
|
1508 |
pic_irq = pci_irqs[pin]; |
1509 |
pci_config_writeb(d, PCI_INTERRUPT_LINE, pic_irq); |
1510 |
} |
1511 |
} |
1512 |
|
1513 |
/*
|
1514 |
* This function initializes the PCI devices as a normal PCI BIOS
|
1515 |
* would do. It is provided just in case the BIOS has no support for
|
1516 |
* PCI.
|
1517 |
*/
|
1518 |
void pci_bios_init(void) |
1519 |
{ |
1520 |
PCIBus *bus; |
1521 |
PCIDevice *d; |
1522 |
int devfn, i, irq;
|
1523 |
uint8_t elcr[2];
|
1524 |
|
1525 |
pci_bios_io_addr = 0xc000;
|
1526 |
pci_bios_mem_addr = 0xf0000000;
|
1527 |
|
1528 |
/* activate IRQ mappings */
|
1529 |
elcr[0] = 0x00; |
1530 |
elcr[1] = 0x00; |
1531 |
for(i = 0; i < 4; i++) { |
1532 |
irq = pci_irqs[i]; |
1533 |
/* set to trigger level */
|
1534 |
elcr[irq >> 3] |= (1 << (irq & 7)); |
1535 |
/* activate irq remapping in PIIX */
|
1536 |
pci_config_writeb((PCIDevice *)piix3_state, 0x60 + i, irq);
|
1537 |
} |
1538 |
isa_outb(elcr[0], 0x4d0); |
1539 |
isa_outb(elcr[1], 0x4d1); |
1540 |
|
1541 |
bus = first_bus; |
1542 |
if (bus) {
|
1543 |
for(devfn = 0; devfn < 256; devfn++) { |
1544 |
d = bus->devices[devfn]; |
1545 |
if (d)
|
1546 |
pci_bios_init_device(d); |
1547 |
} |
1548 |
} |
1549 |
} |