Revision 71d9bc50 hw/integratorcp.c
| b/hw/integratorcp.c | ||
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typedef struct {
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SysBusDevice busdev; |
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MemoryRegion iomem; |
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uint32_t memsz; |
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MemoryRegion flash; |
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bool flash_mapped; |
| ... | ... | |
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0xe, 4, 0x1c, 1, 2, 0x20, 0xc0, 0, 0, 0, 0, 0x30, 0x28, 0x30, 0x28, 0x40 |
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}; |
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static uint32_t integratorcm_read(void *opaque, target_phys_addr_t offset) |
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static uint64_t integratorcm_read(void *opaque, target_phys_addr_t offset, |
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unsigned size) |
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{
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integratorcm_state *s = (integratorcm_state *)opaque; |
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if (offset >= 0x100 && offset < 0x200) {
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| ... | ... | |
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} |
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static void integratorcm_write(void *opaque, target_phys_addr_t offset, |
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uint32_t value)
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uint64_t value, unsigned size)
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{
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integratorcm_state *s = (integratorcm_state *)opaque; |
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switch (offset >> 2) {
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| ... | ... | |
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/* Integrator/CM control registers. */ |
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static CPUReadMemoryFunc * const integratorcm_readfn[] = {
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integratorcm_read, |
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integratorcm_read, |
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integratorcm_read |
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}; |
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static CPUWriteMemoryFunc * const integratorcm_writefn[] = {
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integratorcm_write, |
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integratorcm_write, |
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integratorcm_write |
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static const MemoryRegionOps integratorcm_ops = {
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.read = integratorcm_read, |
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.write = integratorcm_write, |
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.endianness = DEVICE_NATIVE_ENDIAN, |
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}; |
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static int integratorcm_init(SysBusDevice *dev) |
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{
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int iomemtype; |
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integratorcm_state *s = FROM_SYSBUS(integratorcm_state, dev); |
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s->cm_osc = 0x01000048; |
| ... | ... | |
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memory_region_init_ram(&s->flash, NULL, "integrator.flash", 0x100000); |
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s->flash_mapped = false; |
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iomemtype = cpu_register_io_memory(integratorcm_readfn,
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integratorcm_writefn, s,
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DEVICE_NATIVE_ENDIAN);
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sysbus_init_mmio(dev, 0x00800000, iomemtype); |
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memory_region_init_io(&s->iomem, &integratorcm_ops, s,
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"integratorcm", 0x00800000);
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sysbus_init_mmio_region(dev, &s->iomem);
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integratorcm_do_remap(s, 1); |
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/* ??? Save/restore. */ |
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return 0; |
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