390 |
390 |
GEN32(gen_op_store_T0_gpr, gen_op_store_T0_gpr_gpr);
|
391 |
391 |
GEN32(gen_op_store_T1_gpr, gen_op_store_T1_gpr_gpr);
|
392 |
392 |
|
|
393 |
#ifdef MIPS_USES_FPU
|
|
394 |
|
393 |
395 |
static const char *fregnames[] =
|
394 |
396 |
{ "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
|
395 |
397 |
"f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
|
... | ... | |
473 |
475 |
FOP_CONDS(d)
|
474 |
476 |
FOP_CONDS(s)
|
475 |
477 |
|
|
478 |
#endif /* MIPS_USES_FPU */
|
|
479 |
|
476 |
480 |
typedef struct DisasContext {
|
477 |
481 |
struct TranslationBlock *tb;
|
478 |
482 |
target_ulong pc, saved_pc;
|
... | ... | |
633 |
637 |
OP_ST_TABLE(b);
|
634 |
638 |
OP_LD_TABLE(l);
|
635 |
639 |
OP_ST_TABLE(c);
|
|
640 |
#ifdef MIPS_USES_FPU
|
636 |
641 |
OP_LD_TABLE(wc1);
|
637 |
642 |
OP_ST_TABLE(wc1);
|
638 |
643 |
OP_LD_TABLE(dc1);
|
639 |
644 |
OP_ST_TABLE(dc1);
|
|
645 |
#endif
|
640 |
646 |
|
641 |
647 |
/* Load and store */
|
642 |
648 |
static void gen_ldst (DisasContext *ctx, uint32_t opc, int rt,
|
... | ... | |
785 |
791 |
MIPS_DEBUG("%s %s, %d(%s)", opn, regnames[rt], offset, regnames[base]);
|
786 |
792 |
}
|
787 |
793 |
|
|
794 |
#ifdef MIPS_USES_FPU
|
|
795 |
|
788 |
796 |
/* Load and store */
|
789 |
797 |
static void gen_flt_ldst (DisasContext *ctx, uint32_t opc, int ft,
|
790 |
798 |
int base, int16_t offset)
|
... | ... | |
832 |
840 |
MIPS_DEBUG("%s %s, %d(%s)", opn, fregnames[ft], offset, regnames[base]);
|
833 |
841 |
}
|
834 |
842 |
|
|
843 |
#endif /* MIPS_USES_FPU */
|
|
844 |
|
835 |
845 |
/* Arithmetic with immediate operand */
|
836 |
846 |
static void gen_arith_imm (DisasContext *ctx, uint32_t opc, int rt,
|
837 |
847 |
int rs, int16_t imm)
|
... | ... | |
2903 |
2913 |
MIPS_DEBUG("%s %s %d", opn, regnames[rt], rd);
|
2904 |
2914 |
}
|
2905 |
2915 |
|
|
2916 |
#ifdef MIPS_USES_FPU
|
|
2917 |
|
2906 |
2918 |
/* CP1 Branches (before delay slot) */
|
2907 |
2919 |
static void gen_compute_branch1 (DisasContext *ctx, uint32_t op,
|
2908 |
2920 |
int32_t offset)
|
... | ... | |
3331 |
3343 |
gen_op_movt(ccbit, rd, rs);
|
3332 |
3344 |
}
|
3333 |
3345 |
|
|
3346 |
#endif /* MIPS_USES_FPU */
|
|
3347 |
|
3334 |
3348 |
/* ISA extensions (ASEs) */
|
3335 |
3349 |
/* MIPS16 extension to MIPS32 */
|
3336 |
3350 |
/* SmartMIPS extension to MIPS32 */
|
... | ... | |
3453 |
3467 |
/* Treat as a noop. */
|
3454 |
3468 |
break;
|
3455 |
3469 |
|
|
3470 |
#ifdef MIPS_USES_FPU
|
3456 |
3471 |
case OPC_MOVCI:
|
3457 |
3472 |
gen_op_cp1_enabled();
|
3458 |
3473 |
gen_movci(ctx, rd, rs, (ctx->opcode >> 18) & 0x7,
|
3459 |
3474 |
(ctx->opcode >> 16) & 1);
|
3460 |
3475 |
break;
|
|
3476 |
#endif
|
3461 |
3477 |
|
3462 |
3478 |
#ifdef MIPS_HAS_MIPS64
|
3463 |
3479 |
/* MIPS64 specific opcodes */
|
... | ... | |
3737 |
3753 |
generate_exception_err(ctx, EXCP_CpU, 2);
|
3738 |
3754 |
break;
|
3739 |
3755 |
|
|
3756 |
#ifdef MIPS_USES_FPU
|
3740 |
3757 |
case OPC_CP3:
|
3741 |
3758 |
gen_op_cp1_enabled();
|
3742 |
3759 |
op1 = MASK_CP3(ctx->opcode);
|
... | ... | |
3747 |
3764 |
break;
|
3748 |
3765 |
}
|
3749 |
3766 |
break;
|
|
3767 |
#endif
|
3750 |
3768 |
|
3751 |
3769 |
#ifdef MIPS_HAS_MIPS64
|
3752 |
3770 |
/* MIPS64 opcodes */
|
... | ... | |
3962 |
3980 |
return gen_intermediate_code_internal(env, tb, 1);
|
3963 |
3981 |
}
|
3964 |
3982 |
|
|
3983 |
#ifdef MIPS_USES_FPU
|
|
3984 |
|
3965 |
3985 |
void fpu_dump_state(CPUState *env, FILE *f,
|
3966 |
3986 |
int (*fpu_fprintf)(FILE *f, const char *fmt, ...),
|
3967 |
3987 |
int flags)
|
... | ... | |
3996 |
4016 |
}
|
3997 |
4017 |
}
|
3998 |
4018 |
|
|
4019 |
#endif /* MIPS_USES_FPU */
|
|
4020 |
|
3999 |
4021 |
void cpu_dump_state (CPUState *env, FILE *f,
|
4000 |
4022 |
int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
|
4001 |
4023 |
int flags)
|
... | ... | |
4025 |
4047 |
c0_status, env->CP0_Cause, env->CP0_EPC);
|
4026 |
4048 |
cpu_fprintf(f, " Config0 0x%08x Config1 0x%08x LLAddr 0x%08x\n",
|
4027 |
4049 |
env->CP0_Config0, env->CP0_Config1, env->CP0_LLAddr);
|
|
4050 |
#ifdef MIPS_USES_FPU
|
4028 |
4051 |
if (c0_status & (1 << CP0St_CU1))
|
4029 |
4052 |
fpu_dump_state(env, f, cpu_fprintf, flags);
|
|
4053 |
#endif
|
4030 |
4054 |
}
|
4031 |
4055 |
|
4032 |
4056 |
CPUMIPSState *cpu_mips_init (void)
|