root / hw / arm11mpcore.c @ 721589dd
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1 | f7c70325 | Paul Brook | /*
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2 | f7c70325 | Paul Brook | * ARM11MPCore internal peripheral emulation.
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3 | f7c70325 | Paul Brook | *
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4 | f7c70325 | Paul Brook | * Copyright (c) 2006-2007 CodeSourcery.
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5 | f7c70325 | Paul Brook | * Written by Paul Brook
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6 | f7c70325 | Paul Brook | *
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7 | 8e31bf38 | Matthew Fernandez | * This code is licensed under the GPL.
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8 | f7c70325 | Paul Brook | */
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9 | f7c70325 | Paul Brook | |
10 | 2a6ab1e3 | Peter Maydell | #include "sysbus.h" |
11 | 2a6ab1e3 | Peter Maydell | #include "qemu-timer.h" |
12 | 2a6ab1e3 | Peter Maydell | |
13 | 2a6ab1e3 | Peter Maydell | /* MPCore private memory region. */
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14 | 2a6ab1e3 | Peter Maydell | |
15 | 2a6ab1e3 | Peter Maydell | typedef struct mpcore_priv_state { |
16 | 2e9dfe20 | Peter Maydell | SysBusDevice busdev; |
17 | 2a6ab1e3 | Peter Maydell | uint32_t scu_control; |
18 | 2a6ab1e3 | Peter Maydell | int iomemtype;
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19 | 2a6ab1e3 | Peter Maydell | uint32_t old_timer_status[8];
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20 | 2a6ab1e3 | Peter Maydell | uint32_t num_cpu; |
21 | 2a6ab1e3 | Peter Maydell | MemoryRegion iomem; |
22 | 2a6ab1e3 | Peter Maydell | MemoryRegion container; |
23 | 2a6ab1e3 | Peter Maydell | DeviceState *mptimer; |
24 | 2e9dfe20 | Peter Maydell | DeviceState *gic; |
25 | a32134aa | Mark Langsdorf | uint32_t num_irq; |
26 | 2a6ab1e3 | Peter Maydell | } mpcore_priv_state; |
27 | 2a6ab1e3 | Peter Maydell | |
28 | 2a6ab1e3 | Peter Maydell | /* Per-CPU private memory mapped IO. */
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29 | 2a6ab1e3 | Peter Maydell | |
30 | 2a6ab1e3 | Peter Maydell | static uint64_t mpcore_scu_read(void *opaque, target_phys_addr_t offset, |
31 | 2a6ab1e3 | Peter Maydell | unsigned size)
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32 | 2a6ab1e3 | Peter Maydell | { |
33 | 2a6ab1e3 | Peter Maydell | mpcore_priv_state *s = (mpcore_priv_state *)opaque; |
34 | 2a6ab1e3 | Peter Maydell | int id;
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35 | 2a6ab1e3 | Peter Maydell | /* SCU */
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36 | 2a6ab1e3 | Peter Maydell | switch (offset) {
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37 | 2a6ab1e3 | Peter Maydell | case 0x00: /* Control. */ |
38 | 2a6ab1e3 | Peter Maydell | return s->scu_control;
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39 | 2a6ab1e3 | Peter Maydell | case 0x04: /* Configuration. */ |
40 | 2a6ab1e3 | Peter Maydell | id = ((1 << s->num_cpu) - 1) << 4; |
41 | 2a6ab1e3 | Peter Maydell | return id | (s->num_cpu - 1); |
42 | 2a6ab1e3 | Peter Maydell | case 0x08: /* CPU status. */ |
43 | 2a6ab1e3 | Peter Maydell | return 0; |
44 | 2a6ab1e3 | Peter Maydell | case 0x0c: /* Invalidate all. */ |
45 | 2a6ab1e3 | Peter Maydell | return 0; |
46 | 2a6ab1e3 | Peter Maydell | default:
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47 | 2a6ab1e3 | Peter Maydell | hw_error("mpcore_priv_read: Bad offset %x\n", (int)offset); |
48 | 2a6ab1e3 | Peter Maydell | } |
49 | 2a6ab1e3 | Peter Maydell | } |
50 | 2a6ab1e3 | Peter Maydell | |
51 | 2a6ab1e3 | Peter Maydell | static void mpcore_scu_write(void *opaque, target_phys_addr_t offset, |
52 | 2a6ab1e3 | Peter Maydell | uint64_t value, unsigned size)
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53 | 2a6ab1e3 | Peter Maydell | { |
54 | 2a6ab1e3 | Peter Maydell | mpcore_priv_state *s = (mpcore_priv_state *)opaque; |
55 | 2a6ab1e3 | Peter Maydell | /* SCU */
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56 | 2a6ab1e3 | Peter Maydell | switch (offset) {
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57 | 2a6ab1e3 | Peter Maydell | case 0: /* Control register. */ |
58 | 2a6ab1e3 | Peter Maydell | s->scu_control = value & 1;
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59 | 2a6ab1e3 | Peter Maydell | break;
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60 | 2a6ab1e3 | Peter Maydell | case 0x0c: /* Invalidate all. */ |
61 | 2a6ab1e3 | Peter Maydell | /* This is a no-op as cache is not emulated. */
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62 | 2a6ab1e3 | Peter Maydell | break;
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63 | 2a6ab1e3 | Peter Maydell | default:
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64 | 2a6ab1e3 | Peter Maydell | hw_error("mpcore_priv_read: Bad offset %x\n", (int)offset); |
65 | 2a6ab1e3 | Peter Maydell | } |
66 | 2a6ab1e3 | Peter Maydell | } |
67 | 2a6ab1e3 | Peter Maydell | |
68 | 2a6ab1e3 | Peter Maydell | static const MemoryRegionOps mpcore_scu_ops = { |
69 | 2a6ab1e3 | Peter Maydell | .read = mpcore_scu_read, |
70 | 2a6ab1e3 | Peter Maydell | .write = mpcore_scu_write, |
71 | 2a6ab1e3 | Peter Maydell | .endianness = DEVICE_NATIVE_ENDIAN, |
72 | 2a6ab1e3 | Peter Maydell | }; |
73 | 2a6ab1e3 | Peter Maydell | |
74 | 2e9dfe20 | Peter Maydell | static void mpcore_priv_set_irq(void *opaque, int irq, int level) |
75 | 2a6ab1e3 | Peter Maydell | { |
76 | 2a6ab1e3 | Peter Maydell | mpcore_priv_state *s = (mpcore_priv_state *)opaque; |
77 | 2e9dfe20 | Peter Maydell | qemu_set_irq(qdev_get_gpio_in(s->gic, irq), level); |
78 | 2a6ab1e3 | Peter Maydell | } |
79 | 2a6ab1e3 | Peter Maydell | |
80 | 2a6ab1e3 | Peter Maydell | static void mpcore_priv_map_setup(mpcore_priv_state *s) |
81 | 2a6ab1e3 | Peter Maydell | { |
82 | 2a6ab1e3 | Peter Maydell | int i;
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83 | 2e9dfe20 | Peter Maydell | SysBusDevice *gicbusdev = sysbus_from_qdev(s->gic); |
84 | 2a6ab1e3 | Peter Maydell | SysBusDevice *busdev = sysbus_from_qdev(s->mptimer); |
85 | 2a6ab1e3 | Peter Maydell | memory_region_init(&s->container, "mpcode-priv-container", 0x2000); |
86 | 2a6ab1e3 | Peter Maydell | memory_region_init_io(&s->iomem, &mpcore_scu_ops, s, "mpcore-scu", 0x100); |
87 | 2a6ab1e3 | Peter Maydell | memory_region_add_subregion(&s->container, 0, &s->iomem);
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88 | 2a6ab1e3 | Peter Maydell | /* GIC CPU interfaces: "current CPU" at 0x100, then specific CPUs
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89 | 2a6ab1e3 | Peter Maydell | * at 0x200, 0x300...
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90 | 2a6ab1e3 | Peter Maydell | */
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91 | 2a6ab1e3 | Peter Maydell | for (i = 0; i < (s->num_cpu + 1); i++) { |
92 | 2a6ab1e3 | Peter Maydell | target_phys_addr_t offset = 0x100 + (i * 0x100); |
93 | 2e9dfe20 | Peter Maydell | memory_region_add_subregion(&s->container, offset, |
94 | 2e9dfe20 | Peter Maydell | sysbus_mmio_get_region(gicbusdev, i + 1));
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95 | 2a6ab1e3 | Peter Maydell | } |
96 | 2a6ab1e3 | Peter Maydell | /* Add the regions for timer and watchdog for "current CPU" and
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97 | 2a6ab1e3 | Peter Maydell | * for each specific CPU.
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98 | 2a6ab1e3 | Peter Maydell | */
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99 | 2a6ab1e3 | Peter Maydell | for (i = 0; i < (s->num_cpu + 1) * 2; i++) { |
100 | 2a6ab1e3 | Peter Maydell | /* Timers at 0x600, 0x700, ...; watchdogs at 0x620, 0x720, ... */
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101 | 2a6ab1e3 | Peter Maydell | target_phys_addr_t offset = 0x600 + (i >> 1) * 0x100 + (i & 1) * 0x20; |
102 | 2a6ab1e3 | Peter Maydell | memory_region_add_subregion(&s->container, offset, |
103 | 2a6ab1e3 | Peter Maydell | sysbus_mmio_get_region(busdev, i)); |
104 | 2a6ab1e3 | Peter Maydell | } |
105 | 2e9dfe20 | Peter Maydell | memory_region_add_subregion(&s->container, 0x1000,
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106 | 2e9dfe20 | Peter Maydell | sysbus_mmio_get_region(gicbusdev, 0));
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107 | 2e9dfe20 | Peter Maydell | /* Wire up the interrupt from each watchdog and timer.
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108 | 2e9dfe20 | Peter Maydell | * For each core the timer is PPI 29 and the watchdog PPI 30.
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109 | 2e9dfe20 | Peter Maydell | */
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110 | 2e9dfe20 | Peter Maydell | for (i = 0; i < s->num_cpu; i++) { |
111 | 2e9dfe20 | Peter Maydell | int ppibase = (s->num_irq - 32) + i * 32; |
112 | 2e9dfe20 | Peter Maydell | sysbus_connect_irq(busdev, i * 2,
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113 | 2e9dfe20 | Peter Maydell | qdev_get_gpio_in(s->gic, ppibase + 29));
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114 | 2e9dfe20 | Peter Maydell | sysbus_connect_irq(busdev, i * 2 + 1, |
115 | 2e9dfe20 | Peter Maydell | qdev_get_gpio_in(s->gic, ppibase + 30));
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116 | 2a6ab1e3 | Peter Maydell | } |
117 | 2a6ab1e3 | Peter Maydell | } |
118 | 2a6ab1e3 | Peter Maydell | |
119 | 2a6ab1e3 | Peter Maydell | static int mpcore_priv_init(SysBusDevice *dev) |
120 | 2a6ab1e3 | Peter Maydell | { |
121 | 2e9dfe20 | Peter Maydell | mpcore_priv_state *s = FROM_SYSBUS(mpcore_priv_state, dev); |
122 | 2e9dfe20 | Peter Maydell | |
123 | 2e9dfe20 | Peter Maydell | s->gic = qdev_create(NULL, "arm_gic"); |
124 | 2e9dfe20 | Peter Maydell | qdev_prop_set_uint32(s->gic, "num-cpu", s->num_cpu);
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125 | 2e9dfe20 | Peter Maydell | qdev_prop_set_uint32(s->gic, "num-irq", s->num_irq);
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126 | 2e9dfe20 | Peter Maydell | qdev_init_nofail(s->gic); |
127 | 2e9dfe20 | Peter Maydell | |
128 | 2e9dfe20 | Peter Maydell | /* Pass through outbound IRQ lines from the GIC */
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129 | 2e9dfe20 | Peter Maydell | sysbus_pass_irq(dev, sysbus_from_qdev(s->gic)); |
130 | 2e9dfe20 | Peter Maydell | |
131 | 2e9dfe20 | Peter Maydell | /* Pass through inbound GPIO lines to the GIC */
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132 | 2e9dfe20 | Peter Maydell | qdev_init_gpio_in(&s->busdev.qdev, mpcore_priv_set_irq, s->num_irq - 32);
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133 | 2a6ab1e3 | Peter Maydell | |
134 | 2a6ab1e3 | Peter Maydell | s->mptimer = qdev_create(NULL, "arm_mptimer"); |
135 | 2a6ab1e3 | Peter Maydell | qdev_prop_set_uint32(s->mptimer, "num-cpu", s->num_cpu);
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136 | 2a6ab1e3 | Peter Maydell | qdev_init_nofail(s->mptimer); |
137 | 2a6ab1e3 | Peter Maydell | mpcore_priv_map_setup(s); |
138 | 2a6ab1e3 | Peter Maydell | sysbus_init_mmio(dev, &s->container); |
139 | 2a6ab1e3 | Peter Maydell | return 0; |
140 | 2a6ab1e3 | Peter Maydell | } |
141 | f7c70325 | Paul Brook | |
142 | f7c70325 | Paul Brook | /* Dummy PIC to route IRQ lines. The baseboard has 4 independent IRQ
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143 | f7c70325 | Paul Brook | controllers. The output of these, plus some of the raw input lines
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144 | f7c70325 | Paul Brook | are fed into a single SMP-aware interrupt controller on the CPU. */
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145 | f7c70325 | Paul Brook | typedef struct { |
146 | f7c70325 | Paul Brook | SysBusDevice busdev; |
147 | f7c70325 | Paul Brook | SysBusDevice *priv; |
148 | f7c70325 | Paul Brook | qemu_irq cpuic[32];
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149 | f7c70325 | Paul Brook | qemu_irq rvic[4][64]; |
150 | f7c70325 | Paul Brook | uint32_t num_cpu; |
151 | f7c70325 | Paul Brook | } mpcore_rirq_state; |
152 | f7c70325 | Paul Brook | |
153 | f7c70325 | Paul Brook | /* Map baseboard IRQs onto CPU IRQ lines. */
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154 | f7c70325 | Paul Brook | static const int mpcore_irq_map[32] = { |
155 | f7c70325 | Paul Brook | -1, -1, -1, -1, 1, 2, -1, -1, |
156 | f7c70325 | Paul Brook | -1, -1, 6, -1, 4, 5, -1, -1, |
157 | f7c70325 | Paul Brook | -1, 14, 15, 0, 7, 8, -1, -1, |
158 | f7c70325 | Paul Brook | -1, -1, -1, -1, 9, 3, -1, -1, |
159 | f7c70325 | Paul Brook | }; |
160 | f7c70325 | Paul Brook | |
161 | f7c70325 | Paul Brook | static void mpcore_rirq_set_irq(void *opaque, int irq, int level) |
162 | f7c70325 | Paul Brook | { |
163 | f7c70325 | Paul Brook | mpcore_rirq_state *s = (mpcore_rirq_state *)opaque; |
164 | f7c70325 | Paul Brook | int i;
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165 | f7c70325 | Paul Brook | |
166 | f7c70325 | Paul Brook | for (i = 0; i < 4; i++) { |
167 | f7c70325 | Paul Brook | qemu_set_irq(s->rvic[i][irq], level); |
168 | f7c70325 | Paul Brook | } |
169 | f7c70325 | Paul Brook | if (irq < 32) { |
170 | f7c70325 | Paul Brook | irq = mpcore_irq_map[irq]; |
171 | f7c70325 | Paul Brook | if (irq >= 0) { |
172 | f7c70325 | Paul Brook | qemu_set_irq(s->cpuic[irq], level); |
173 | f7c70325 | Paul Brook | } |
174 | f7c70325 | Paul Brook | } |
175 | f7c70325 | Paul Brook | } |
176 | f7c70325 | Paul Brook | |
177 | f7c70325 | Paul Brook | static int realview_mpcore_init(SysBusDevice *dev) |
178 | f7c70325 | Paul Brook | { |
179 | f7c70325 | Paul Brook | mpcore_rirq_state *s = FROM_SYSBUS(mpcore_rirq_state, dev); |
180 | f7c70325 | Paul Brook | DeviceState *gic; |
181 | f7c70325 | Paul Brook | DeviceState *priv; |
182 | f7c70325 | Paul Brook | int n;
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183 | f7c70325 | Paul Brook | int i;
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184 | f7c70325 | Paul Brook | |
185 | f7c70325 | Paul Brook | priv = qdev_create(NULL, "arm11mpcore_priv"); |
186 | f7c70325 | Paul Brook | qdev_prop_set_uint32(priv, "num-cpu", s->num_cpu);
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187 | f7c70325 | Paul Brook | qdev_init_nofail(priv); |
188 | f7c70325 | Paul Brook | s->priv = sysbus_from_qdev(priv); |
189 | f7c70325 | Paul Brook | sysbus_pass_irq(dev, s->priv); |
190 | f7c70325 | Paul Brook | for (i = 0; i < 32; i++) { |
191 | f7c70325 | Paul Brook | s->cpuic[i] = qdev_get_gpio_in(priv, i); |
192 | f7c70325 | Paul Brook | } |
193 | f7c70325 | Paul Brook | /* ??? IRQ routing is hardcoded to "normal" mode. */
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194 | f7c70325 | Paul Brook | for (n = 0; n < 4; n++) { |
195 | f7c70325 | Paul Brook | gic = sysbus_create_simple("realview_gic", 0x10040000 + n * 0x10000, |
196 | f7c70325 | Paul Brook | s->cpuic[10 + n]);
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197 | f7c70325 | Paul Brook | for (i = 0; i < 64; i++) { |
198 | f7c70325 | Paul Brook | s->rvic[n][i] = qdev_get_gpio_in(gic, i); |
199 | f7c70325 | Paul Brook | } |
200 | f7c70325 | Paul Brook | } |
201 | f7c70325 | Paul Brook | qdev_init_gpio_in(&dev->qdev, mpcore_rirq_set_irq, 64);
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202 | 750ecd44 | Avi Kivity | sysbus_init_mmio(dev, sysbus_mmio_get_region(s->priv, 0));
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203 | f7c70325 | Paul Brook | return 0; |
204 | f7c70325 | Paul Brook | } |
205 | f7c70325 | Paul Brook | |
206 | 999e12bb | Anthony Liguori | static Property mpcore_rirq_properties[] = {
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207 | 0f58a188 | Peter Maydell | DEFINE_PROP_UINT32("num-cpu", mpcore_rirq_state, num_cpu, 1), |
208 | 999e12bb | Anthony Liguori | DEFINE_PROP_END_OF_LIST(), |
209 | f7c70325 | Paul Brook | }; |
210 | f7c70325 | Paul Brook | |
211 | 999e12bb | Anthony Liguori | static void mpcore_rirq_class_init(ObjectClass *klass, void *data) |
212 | 999e12bb | Anthony Liguori | { |
213 | 39bffca2 | Anthony Liguori | DeviceClass *dc = DEVICE_CLASS(klass); |
214 | 999e12bb | Anthony Liguori | SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); |
215 | 999e12bb | Anthony Liguori | |
216 | 999e12bb | Anthony Liguori | k->init = realview_mpcore_init; |
217 | 39bffca2 | Anthony Liguori | dc->props = mpcore_rirq_properties; |
218 | 999e12bb | Anthony Liguori | } |
219 | 999e12bb | Anthony Liguori | |
220 | 39bffca2 | Anthony Liguori | static TypeInfo mpcore_rirq_info = {
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221 | 39bffca2 | Anthony Liguori | .name = "realview_mpcore",
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222 | 39bffca2 | Anthony Liguori | .parent = TYPE_SYS_BUS_DEVICE, |
223 | 39bffca2 | Anthony Liguori | .instance_size = sizeof(mpcore_rirq_state),
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224 | 39bffca2 | Anthony Liguori | .class_init = mpcore_rirq_class_init, |
225 | 999e12bb | Anthony Liguori | }; |
226 | 999e12bb | Anthony Liguori | |
227 | 999e12bb | Anthony Liguori | static Property mpcore_priv_properties[] = {
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228 | 999e12bb | Anthony Liguori | DEFINE_PROP_UINT32("num-cpu", mpcore_priv_state, num_cpu, 1), |
229 | 0f58a188 | Peter Maydell | /* The ARM11 MPCORE TRM says the on-chip controller may have
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230 | 0f58a188 | Peter Maydell | * anything from 0 to 224 external interrupt IRQ lines (with another
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231 | 0f58a188 | Peter Maydell | * 32 internal). We default to 32+32, which is the number provided by
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232 | 0f58a188 | Peter Maydell | * the ARM11 MPCore test chip in the Realview Versatile Express
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233 | 0f58a188 | Peter Maydell | * coretile. Other boards may differ and should set this property
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234 | 0f58a188 | Peter Maydell | * appropriately. Some Linux kernels may not boot if the hardware
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235 | 0f58a188 | Peter Maydell | * has more IRQ lines than the kernel expects.
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236 | 0f58a188 | Peter Maydell | */
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237 | 0f58a188 | Peter Maydell | DEFINE_PROP_UINT32("num-irq", mpcore_priv_state, num_irq, 64), |
238 | 999e12bb | Anthony Liguori | DEFINE_PROP_END_OF_LIST(), |
239 | 999e12bb | Anthony Liguori | }; |
240 | 999e12bb | Anthony Liguori | |
241 | 999e12bb | Anthony Liguori | static void mpcore_priv_class_init(ObjectClass *klass, void *data) |
242 | 999e12bb | Anthony Liguori | { |
243 | 39bffca2 | Anthony Liguori | DeviceClass *dc = DEVICE_CLASS(klass); |
244 | 999e12bb | Anthony Liguori | SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); |
245 | 999e12bb | Anthony Liguori | |
246 | 999e12bb | Anthony Liguori | k->init = mpcore_priv_init; |
247 | 39bffca2 | Anthony Liguori | dc->props = mpcore_priv_properties; |
248 | 999e12bb | Anthony Liguori | } |
249 | 999e12bb | Anthony Liguori | |
250 | 39bffca2 | Anthony Liguori | static TypeInfo mpcore_priv_info = {
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251 | 39bffca2 | Anthony Liguori | .name = "arm11mpcore_priv",
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252 | 39bffca2 | Anthony Liguori | .parent = TYPE_SYS_BUS_DEVICE, |
253 | 39bffca2 | Anthony Liguori | .instance_size = sizeof(mpcore_priv_state),
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254 | 39bffca2 | Anthony Liguori | .class_init = mpcore_priv_class_init, |
255 | f7c70325 | Paul Brook | }; |
256 | f7c70325 | Paul Brook | |
257 | 83f7d43a | Andreas Färber | static void arm11mpcore_register_types(void) |
258 | f7c70325 | Paul Brook | { |
259 | 39bffca2 | Anthony Liguori | type_register_static(&mpcore_rirq_info); |
260 | 39bffca2 | Anthony Liguori | type_register_static(&mpcore_priv_info); |
261 | f7c70325 | Paul Brook | } |
262 | f7c70325 | Paul Brook | |
263 | 83f7d43a | Andreas Färber | type_init(arm11mpcore_register_types) |