Revision 72716184
| b/hw/mc146818rtc.c | ||
|---|---|---|
| 57 | 57 |
#define REG_B_SQWE 0x08 |
| 58 | 58 |
#define REG_B_DM 0x04 |
| 59 | 59 |
|
| 60 |
#define REG_C_UF 0x10 |
|
| 61 |
#define REG_C_IRQF 0x80 |
|
| 62 |
#define REG_C_PF 0x40 |
|
| 63 |
#define REG_C_AF 0x20 |
|
| 64 |
|
|
| 60 | 65 |
struct RTCState {
|
| 61 | 66 |
uint8_t cmos_data[128]; |
| 62 | 67 |
uint8_t cmos_index; |
| ... | ... | |
| 572 | 577 |
{
|
| 573 | 578 |
RTCState *s = opaque; |
| 574 | 579 |
|
| 575 |
/* clear PIE,AIE,SQWE on reset */
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|
| 576 |
s->cmos_data[RTC_REG_B] &= ~((1<<6) | (1<<5) | (1<<3));
|
|
| 580 |
s->cmos_data[RTC_REG_B] &= ~(REG_B_PIE | REG_B_AIE | REG_B_SQWE);
|
|
| 581 |
s->cmos_data[RTC_REG_C] &= ~(REG_C_UF | REG_C_IRQF | REG_C_PF | REG_C_AF);
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|
| 577 | 582 |
|
| 578 |
/* clear UF,IRQF,PF,AF on reset */ |
|
| 579 |
s->cmos_data[RTC_REG_C] &= ~((1<<4) | (1<<7) | (1<<6) | (1<<5)); |
|
| 583 |
qemu_irq_lower(s->irq); |
|
| 580 | 584 |
|
| 581 | 585 |
#ifdef TARGET_I386 |
| 582 | 586 |
if (rtc_td_hack) |
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