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1 | 420557e8 | bellard | /*
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2 | 420557e8 | bellard | * QEMU SPARC iommu emulation
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3 | 420557e8 | bellard | *
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4 | 66321a11 | bellard | * Copyright (c) 2003-2005 Fabrice Bellard
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5 | 5fafdf24 | ths | *
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6 | 420557e8 | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | 420557e8 | bellard | * of this software and associated documentation files (the "Software"), to deal
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8 | 420557e8 | bellard | * in the Software without restriction, including without limitation the rights
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9 | 420557e8 | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | 420557e8 | bellard | * copies of the Software, and to permit persons to whom the Software is
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11 | 420557e8 | bellard | * furnished to do so, subject to the following conditions:
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12 | 420557e8 | bellard | *
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13 | 420557e8 | bellard | * The above copyright notice and this permission notice shall be included in
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14 | 420557e8 | bellard | * all copies or substantial portions of the Software.
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15 | 420557e8 | bellard | *
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16 | 420557e8 | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | 420557e8 | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | 420557e8 | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | 420557e8 | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | 420557e8 | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | 420557e8 | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | 420557e8 | bellard | * THE SOFTWARE.
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23 | 420557e8 | bellard | */
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24 | 87ecb68b | pbrook | #include "hw.h" |
25 | 87ecb68b | pbrook | #include "sun4m.h" |
26 | 420557e8 | bellard | |
27 | 420557e8 | bellard | /* debug iommu */
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28 | 420557e8 | bellard | //#define DEBUG_IOMMU
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29 | 420557e8 | bellard | |
30 | 66321a11 | bellard | #ifdef DEBUG_IOMMU
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31 | 66321a11 | bellard | #define DPRINTF(fmt, args...) \
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32 | 66321a11 | bellard | do { printf("IOMMU: " fmt , ##args); } while (0) |
33 | 66321a11 | bellard | #else
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34 | 66321a11 | bellard | #define DPRINTF(fmt, args...)
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35 | 66321a11 | bellard | #endif
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36 | 420557e8 | bellard | |
37 | e5e38121 | blueswir1 | #define IOMMU_NREGS (4*4096/4) |
38 | 4e3b1ea1 | bellard | #define IOMMU_CTRL (0x0000 >> 2) |
39 | 420557e8 | bellard | #define IOMMU_CTRL_IMPL 0xf0000000 /* Implementation */ |
40 | 420557e8 | bellard | #define IOMMU_CTRL_VERS 0x0f000000 /* Version */ |
41 | 420557e8 | bellard | #define IOMMU_CTRL_RNGE 0x0000001c /* Mapping RANGE */ |
42 | 420557e8 | bellard | #define IOMMU_RNGE_16MB 0x00000000 /* 0xff000000 -> 0xffffffff */ |
43 | 420557e8 | bellard | #define IOMMU_RNGE_32MB 0x00000004 /* 0xfe000000 -> 0xffffffff */ |
44 | 420557e8 | bellard | #define IOMMU_RNGE_64MB 0x00000008 /* 0xfc000000 -> 0xffffffff */ |
45 | 420557e8 | bellard | #define IOMMU_RNGE_128MB 0x0000000c /* 0xf8000000 -> 0xffffffff */ |
46 | 420557e8 | bellard | #define IOMMU_RNGE_256MB 0x00000010 /* 0xf0000000 -> 0xffffffff */ |
47 | 420557e8 | bellard | #define IOMMU_RNGE_512MB 0x00000014 /* 0xe0000000 -> 0xffffffff */ |
48 | 420557e8 | bellard | #define IOMMU_RNGE_1GB 0x00000018 /* 0xc0000000 -> 0xffffffff */ |
49 | 420557e8 | bellard | #define IOMMU_RNGE_2GB 0x0000001c /* 0x80000000 -> 0xffffffff */ |
50 | 420557e8 | bellard | #define IOMMU_CTRL_ENAB 0x00000001 /* IOMMU Enable */ |
51 | 4e3b1ea1 | bellard | #define IOMMU_CTRL_MASK 0x0000001d |
52 | 4e3b1ea1 | bellard | |
53 | 4e3b1ea1 | bellard | #define IOMMU_BASE (0x0004 >> 2) |
54 | 4e3b1ea1 | bellard | #define IOMMU_BASE_MASK 0x07fffc00 |
55 | 4e3b1ea1 | bellard | |
56 | 4e3b1ea1 | bellard | #define IOMMU_TLBFLUSH (0x0014 >> 2) |
57 | 4e3b1ea1 | bellard | #define IOMMU_TLBFLUSH_MASK 0xffffffff |
58 | 4e3b1ea1 | bellard | |
59 | 4e3b1ea1 | bellard | #define IOMMU_PGFLUSH (0x0018 >> 2) |
60 | 4e3b1ea1 | bellard | #define IOMMU_PGFLUSH_MASK 0xffffffff |
61 | 4e3b1ea1 | bellard | |
62 | 225d4be7 | blueswir1 | #define IOMMU_AFSR (0x1000 >> 2) |
63 | 225d4be7 | blueswir1 | #define IOMMU_AFSR_ERR 0x80000000 /* LE, TO, or BE asserted */ |
64 | 5ad6bb97 | blueswir1 | #define IOMMU_AFSR_LE 0x40000000 /* SBUS reports error after |
65 | 5ad6bb97 | blueswir1 | transaction */
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66 | 5ad6bb97 | blueswir1 | #define IOMMU_AFSR_TO 0x20000000 /* Write access took more than |
67 | 5ad6bb97 | blueswir1 | 12.8 us. */
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68 | 5ad6bb97 | blueswir1 | #define IOMMU_AFSR_BE 0x10000000 /* Write access received error |
69 | 5ad6bb97 | blueswir1 | acknowledge */
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70 | 225d4be7 | blueswir1 | #define IOMMU_AFSR_SIZE 0x0e000000 /* Size of transaction causing error */ |
71 | 225d4be7 | blueswir1 | #define IOMMU_AFSR_S 0x01000000 /* Sparc was in supervisor mode */ |
72 | 5ad6bb97 | blueswir1 | #define IOMMU_AFSR_RESV 0x00800000 /* Reserved, forced to 0x8 by |
73 | 5ad6bb97 | blueswir1 | hardware */
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74 | 225d4be7 | blueswir1 | #define IOMMU_AFSR_ME 0x00080000 /* Multiple errors occurred */ |
75 | 225d4be7 | blueswir1 | #define IOMMU_AFSR_RD 0x00040000 /* A read operation was in progress */ |
76 | 225d4be7 | blueswir1 | #define IOMMU_AFSR_FAV 0x00020000 /* IOMMU afar has valid contents */ |
77 | c52428fc | blueswir1 | #define IOMMU_AFSR_MASK 0xff0fffff |
78 | 225d4be7 | blueswir1 | |
79 | 225d4be7 | blueswir1 | #define IOMMU_AFAR (0x1004 >> 2) |
80 | 225d4be7 | blueswir1 | |
81 | 7b169687 | blueswir1 | #define IOMMU_AER (0x1008 >> 2) /* Arbiter Enable Register */ |
82 | 7b169687 | blueswir1 | #define IOMMU_AER_EN_P0_ARB 0x00000001 /* MBus master 0x8 (Always 1) */ |
83 | 7b169687 | blueswir1 | #define IOMMU_AER_EN_P1_ARB 0x00000002 /* MBus master 0x9 */ |
84 | 7b169687 | blueswir1 | #define IOMMU_AER_EN_P2_ARB 0x00000004 /* MBus master 0xa */ |
85 | 7b169687 | blueswir1 | #define IOMMU_AER_EN_P3_ARB 0x00000008 /* MBus master 0xb */ |
86 | 7b169687 | blueswir1 | #define IOMMU_AER_EN_0 0x00010000 /* SBus slot 0 */ |
87 | 7b169687 | blueswir1 | #define IOMMU_AER_EN_1 0x00020000 /* SBus slot 1 */ |
88 | 7b169687 | blueswir1 | #define IOMMU_AER_EN_2 0x00040000 /* SBus slot 2 */ |
89 | 7b169687 | blueswir1 | #define IOMMU_AER_EN_3 0x00080000 /* SBus slot 3 */ |
90 | 7b169687 | blueswir1 | #define IOMMU_AER_EN_F 0x00100000 /* SBus on-board */ |
91 | 7b169687 | blueswir1 | #define IOMMU_AER_SBW 0x80000000 /* S-to-M asynchronous writes */ |
92 | 7b169687 | blueswir1 | #define IOMMU_AER_MASK 0x801f000f |
93 | 7b169687 | blueswir1 | |
94 | 4e3b1ea1 | bellard | #define IOMMU_SBCFG0 (0x1010 >> 2) /* SBUS configration per-slot */ |
95 | 4e3b1ea1 | bellard | #define IOMMU_SBCFG1 (0x1014 >> 2) /* SBUS configration per-slot */ |
96 | 4e3b1ea1 | bellard | #define IOMMU_SBCFG2 (0x1018 >> 2) /* SBUS configration per-slot */ |
97 | 4e3b1ea1 | bellard | #define IOMMU_SBCFG3 (0x101c >> 2) /* SBUS configration per-slot */ |
98 | 5ad6bb97 | blueswir1 | #define IOMMU_SBCFG_SAB30 0x00010000 /* Phys-address bit 30 when |
99 | 5ad6bb97 | blueswir1 | bypass enabled */
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100 | 4e3b1ea1 | bellard | #define IOMMU_SBCFG_BA16 0x00000004 /* Slave supports 16 byte bursts */ |
101 | 4e3b1ea1 | bellard | #define IOMMU_SBCFG_BA8 0x00000002 /* Slave supports 8 byte bursts */ |
102 | 4e3b1ea1 | bellard | #define IOMMU_SBCFG_BYPASS 0x00000001 /* Bypass IOMMU, treat all addresses |
103 | f930d07e | blueswir1 | produced by this device as pure
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104 | 4e3b1ea1 | bellard | physical. */
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105 | 4e3b1ea1 | bellard | #define IOMMU_SBCFG_MASK 0x00010003 |
106 | 4e3b1ea1 | bellard | |
107 | 4e3b1ea1 | bellard | #define IOMMU_ARBEN (0x2000 >> 2) /* SBUS arbitration enable */ |
108 | 4e3b1ea1 | bellard | #define IOMMU_ARBEN_MASK 0x001f0000 |
109 | 4e3b1ea1 | bellard | #define IOMMU_MID 0x00000008 |
110 | 420557e8 | bellard | |
111 | e5e38121 | blueswir1 | #define IOMMU_MASK_ID (0x3018 >> 2) /* Mask ID */ |
112 | e5e38121 | blueswir1 | #define IOMMU_MASK_ID_MASK 0x00ffffff |
113 | e5e38121 | blueswir1 | |
114 | e5e38121 | blueswir1 | #define IOMMU_MSII_MASK 0x26000000 /* microSPARC II mask number */ |
115 | e5e38121 | blueswir1 | #define IOMMU_TS_MASK 0x23000000 /* turboSPARC mask number */ |
116 | e5e38121 | blueswir1 | |
117 | 420557e8 | bellard | /* The format of an iopte in the page tables */
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118 | 498fbd8a | blueswir1 | #define IOPTE_PAGE 0xffffff00 /* Physical page number (PA[35:12]) */ |
119 | 5ad6bb97 | blueswir1 | #define IOPTE_CACHE 0x00000080 /* Cached (in vme IOCACHE or |
120 | 5ad6bb97 | blueswir1 | Viking/MXCC) */
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121 | 420557e8 | bellard | #define IOPTE_WRITE 0x00000004 /* Writeable */ |
122 | 420557e8 | bellard | #define IOPTE_VALID 0x00000002 /* IOPTE is valid */ |
123 | 420557e8 | bellard | #define IOPTE_WAZ 0x00000001 /* Write as zeros */ |
124 | 420557e8 | bellard | |
125 | 8b0de438 | blueswir1 | #define IOMMU_PAGE_SHIFT 12 |
126 | 8b0de438 | blueswir1 | #define IOMMU_PAGE_SIZE (1 << IOMMU_PAGE_SHIFT) |
127 | 8b0de438 | blueswir1 | #define IOMMU_PAGE_MASK ~(IOMMU_PAGE_SIZE - 1) |
128 | 420557e8 | bellard | |
129 | 420557e8 | bellard | typedef struct IOMMUState { |
130 | 66321a11 | bellard | uint32_t regs[IOMMU_NREGS]; |
131 | 5dcb6b91 | blueswir1 | target_phys_addr_t iostart; |
132 | 7fbfb139 | blueswir1 | uint32_t version; |
133 | ff403da6 | blueswir1 | qemu_irq irq; |
134 | 420557e8 | bellard | } IOMMUState; |
135 | 420557e8 | bellard | |
136 | 7c560456 | blueswir1 | static uint32_t iommu_mem_readl(void *opaque, target_phys_addr_t addr) |
137 | 420557e8 | bellard | { |
138 | 420557e8 | bellard | IOMMUState *s = opaque; |
139 | 5dcb6b91 | blueswir1 | target_phys_addr_t saddr; |
140 | ff403da6 | blueswir1 | uint32_t ret; |
141 | 420557e8 | bellard | |
142 | 8da3ff18 | pbrook | saddr = addr >> 2;
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143 | 420557e8 | bellard | switch (saddr) {
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144 | 420557e8 | bellard | default:
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145 | ff403da6 | blueswir1 | ret = s->regs[saddr]; |
146 | ff403da6 | blueswir1 | break;
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147 | ff403da6 | blueswir1 | case IOMMU_AFAR:
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148 | ff403da6 | blueswir1 | case IOMMU_AFSR:
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149 | ff403da6 | blueswir1 | ret = s->regs[saddr]; |
150 | ff403da6 | blueswir1 | qemu_irq_lower(s->irq); |
151 | f930d07e | blueswir1 | break;
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152 | 420557e8 | bellard | } |
153 | ff403da6 | blueswir1 | DPRINTF("read reg[%d] = %x\n", (int)saddr, ret); |
154 | ff403da6 | blueswir1 | return ret;
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155 | 420557e8 | bellard | } |
156 | 420557e8 | bellard | |
157 | 7c560456 | blueswir1 | static void iommu_mem_writel(void *opaque, target_phys_addr_t addr, |
158 | 5ad6bb97 | blueswir1 | uint32_t val) |
159 | 420557e8 | bellard | { |
160 | 420557e8 | bellard | IOMMUState *s = opaque; |
161 | 5dcb6b91 | blueswir1 | target_phys_addr_t saddr; |
162 | 420557e8 | bellard | |
163 | 8da3ff18 | pbrook | saddr = addr >> 2;
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164 | 981a2e99 | blueswir1 | DPRINTF("write reg[%d] = %x\n", (int)saddr, val); |
165 | 420557e8 | bellard | switch (saddr) {
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166 | 4e3b1ea1 | bellard | case IOMMU_CTRL:
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167 | f930d07e | blueswir1 | switch (val & IOMMU_CTRL_RNGE) {
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168 | f930d07e | blueswir1 | case IOMMU_RNGE_16MB:
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169 | f930d07e | blueswir1 | s->iostart = 0xffffffffff000000ULL;
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170 | f930d07e | blueswir1 | break;
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171 | f930d07e | blueswir1 | case IOMMU_RNGE_32MB:
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172 | f930d07e | blueswir1 | s->iostart = 0xfffffffffe000000ULL;
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173 | f930d07e | blueswir1 | break;
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174 | f930d07e | blueswir1 | case IOMMU_RNGE_64MB:
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175 | f930d07e | blueswir1 | s->iostart = 0xfffffffffc000000ULL;
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176 | f930d07e | blueswir1 | break;
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177 | f930d07e | blueswir1 | case IOMMU_RNGE_128MB:
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178 | f930d07e | blueswir1 | s->iostart = 0xfffffffff8000000ULL;
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179 | f930d07e | blueswir1 | break;
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180 | f930d07e | blueswir1 | case IOMMU_RNGE_256MB:
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181 | f930d07e | blueswir1 | s->iostart = 0xfffffffff0000000ULL;
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182 | f930d07e | blueswir1 | break;
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183 | f930d07e | blueswir1 | case IOMMU_RNGE_512MB:
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184 | f930d07e | blueswir1 | s->iostart = 0xffffffffe0000000ULL;
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185 | f930d07e | blueswir1 | break;
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186 | f930d07e | blueswir1 | case IOMMU_RNGE_1GB:
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187 | f930d07e | blueswir1 | s->iostart = 0xffffffffc0000000ULL;
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188 | f930d07e | blueswir1 | break;
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189 | f930d07e | blueswir1 | default:
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190 | f930d07e | blueswir1 | case IOMMU_RNGE_2GB:
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191 | f930d07e | blueswir1 | s->iostart = 0xffffffff80000000ULL;
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192 | f930d07e | blueswir1 | break;
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193 | f930d07e | blueswir1 | } |
194 | f930d07e | blueswir1 | DPRINTF("iostart = " TARGET_FMT_plx "\n", s->iostart); |
195 | 7fbfb139 | blueswir1 | s->regs[saddr] = ((val & IOMMU_CTRL_MASK) | s->version); |
196 | f930d07e | blueswir1 | break;
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197 | 4e3b1ea1 | bellard | case IOMMU_BASE:
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198 | f930d07e | blueswir1 | s->regs[saddr] = val & IOMMU_BASE_MASK; |
199 | f930d07e | blueswir1 | break;
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200 | 4e3b1ea1 | bellard | case IOMMU_TLBFLUSH:
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201 | f930d07e | blueswir1 | DPRINTF("tlb flush %x\n", val);
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202 | f930d07e | blueswir1 | s->regs[saddr] = val & IOMMU_TLBFLUSH_MASK; |
203 | f930d07e | blueswir1 | break;
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204 | 4e3b1ea1 | bellard | case IOMMU_PGFLUSH:
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205 | f930d07e | blueswir1 | DPRINTF("page flush %x\n", val);
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206 | f930d07e | blueswir1 | s->regs[saddr] = val & IOMMU_PGFLUSH_MASK; |
207 | f930d07e | blueswir1 | break;
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208 | ff403da6 | blueswir1 | case IOMMU_AFAR:
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209 | ff403da6 | blueswir1 | s->regs[saddr] = val; |
210 | ff403da6 | blueswir1 | qemu_irq_lower(s->irq); |
211 | ff403da6 | blueswir1 | break;
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212 | 7b169687 | blueswir1 | case IOMMU_AER:
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213 | 7b169687 | blueswir1 | s->regs[saddr] = (val & IOMMU_AER_MASK) | IOMMU_AER_EN_P0_ARB; |
214 | 7b169687 | blueswir1 | break;
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215 | c52428fc | blueswir1 | case IOMMU_AFSR:
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216 | c52428fc | blueswir1 | s->regs[saddr] = (val & IOMMU_AFSR_MASK) | IOMMU_AFSR_RESV; |
217 | ff403da6 | blueswir1 | qemu_irq_lower(s->irq); |
218 | c52428fc | blueswir1 | break;
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219 | 4e3b1ea1 | bellard | case IOMMU_SBCFG0:
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220 | 4e3b1ea1 | bellard | case IOMMU_SBCFG1:
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221 | 4e3b1ea1 | bellard | case IOMMU_SBCFG2:
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222 | 4e3b1ea1 | bellard | case IOMMU_SBCFG3:
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223 | f930d07e | blueswir1 | s->regs[saddr] = val & IOMMU_SBCFG_MASK; |
224 | f930d07e | blueswir1 | break;
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225 | 4e3b1ea1 | bellard | case IOMMU_ARBEN:
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226 | 4e3b1ea1 | bellard | // XXX implement SBus probing: fault when reading unmapped
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227 | 4e3b1ea1 | bellard | // addresses, fault cause and address stored to MMU/IOMMU
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228 | f930d07e | blueswir1 | s->regs[saddr] = (val & IOMMU_ARBEN_MASK) | IOMMU_MID; |
229 | f930d07e | blueswir1 | break;
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230 | e5e38121 | blueswir1 | case IOMMU_MASK_ID:
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231 | e5e38121 | blueswir1 | s->regs[saddr] |= val & IOMMU_MASK_ID_MASK; |
232 | e5e38121 | blueswir1 | break;
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233 | 420557e8 | bellard | default:
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234 | f930d07e | blueswir1 | s->regs[saddr] = val; |
235 | f930d07e | blueswir1 | break;
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236 | 420557e8 | bellard | } |
237 | 420557e8 | bellard | } |
238 | 420557e8 | bellard | |
239 | 420557e8 | bellard | static CPUReadMemoryFunc *iommu_mem_read[3] = { |
240 | 7c560456 | blueswir1 | NULL,
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241 | 7c560456 | blueswir1 | NULL,
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242 | 7c560456 | blueswir1 | iommu_mem_readl, |
243 | 420557e8 | bellard | }; |
244 | 420557e8 | bellard | |
245 | 420557e8 | bellard | static CPUWriteMemoryFunc *iommu_mem_write[3] = { |
246 | 7c560456 | blueswir1 | NULL,
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247 | 7c560456 | blueswir1 | NULL,
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248 | 7c560456 | blueswir1 | iommu_mem_writel, |
249 | 420557e8 | bellard | }; |
250 | 420557e8 | bellard | |
251 | 5dcb6b91 | blueswir1 | static uint32_t iommu_page_get_flags(IOMMUState *s, target_phys_addr_t addr)
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252 | 420557e8 | bellard | { |
253 | 5e3b100b | blueswir1 | uint32_t ret; |
254 | 5e3b100b | blueswir1 | target_phys_addr_t iopte; |
255 | 981a2e99 | blueswir1 | #ifdef DEBUG_IOMMU
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256 | 981a2e99 | blueswir1 | target_phys_addr_t pa = addr; |
257 | 981a2e99 | blueswir1 | #endif
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258 | 420557e8 | bellard | |
259 | 981a2e99 | blueswir1 | iopte = s->regs[IOMMU_BASE] << 4;
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260 | 66321a11 | bellard | addr &= ~s->iostart; |
261 | 8b0de438 | blueswir1 | iopte += (addr >> (IOMMU_PAGE_SHIFT - 2)) & ~3; |
262 | 5e3b100b | blueswir1 | cpu_physical_memory_read(iopte, (uint8_t *)&ret, 4);
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263 | 748e4993 | blueswir1 | tswap32s(&ret); |
264 | 5e3b100b | blueswir1 | DPRINTF("get flags addr " TARGET_FMT_plx " => pte " TARGET_FMT_plx |
265 | 5e3b100b | blueswir1 | ", *pte = %x\n", pa, iopte, ret);
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266 | 981a2e99 | blueswir1 | |
267 | 981a2e99 | blueswir1 | return ret;
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268 | a917d384 | pbrook | } |
269 | a917d384 | pbrook | |
270 | 22548760 | blueswir1 | static target_phys_addr_t iommu_translate_pa(target_phys_addr_t addr,
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271 | 5dcb6b91 | blueswir1 | uint32_t pte) |
272 | a917d384 | pbrook | { |
273 | a917d384 | pbrook | uint32_t tmppte; |
274 | 5dcb6b91 | blueswir1 | target_phys_addr_t pa; |
275 | 5dcb6b91 | blueswir1 | |
276 | 5dcb6b91 | blueswir1 | tmppte = pte; |
277 | 8b0de438 | blueswir1 | pa = ((pte & IOPTE_PAGE) << 4) + (addr & ~IOMMU_PAGE_MASK);
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278 | 5dcb6b91 | blueswir1 | DPRINTF("xlate dva " TARGET_FMT_plx " => pa " TARGET_FMT_plx |
279 | 5dcb6b91 | blueswir1 | " (iopte = %x)\n", addr, pa, tmppte);
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280 | a917d384 | pbrook | |
281 | 66321a11 | bellard | return pa;
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282 | 420557e8 | bellard | } |
283 | 420557e8 | bellard | |
284 | 5ad6bb97 | blueswir1 | static void iommu_bad_addr(IOMMUState *s, target_phys_addr_t addr, |
285 | 5ad6bb97 | blueswir1 | int is_write)
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286 | 225d4be7 | blueswir1 | { |
287 | 225d4be7 | blueswir1 | DPRINTF("bad addr " TARGET_FMT_plx "\n", addr); |
288 | 5ad6bb97 | blueswir1 | s->regs[IOMMU_AFSR] = IOMMU_AFSR_ERR | IOMMU_AFSR_LE | IOMMU_AFSR_RESV | |
289 | 225d4be7 | blueswir1 | IOMMU_AFSR_FAV; |
290 | 225d4be7 | blueswir1 | if (!is_write)
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291 | 225d4be7 | blueswir1 | s->regs[IOMMU_AFSR] |= IOMMU_AFSR_RD; |
292 | 225d4be7 | blueswir1 | s->regs[IOMMU_AFAR] = addr; |
293 | ff403da6 | blueswir1 | qemu_irq_raise(s->irq); |
294 | 225d4be7 | blueswir1 | } |
295 | 225d4be7 | blueswir1 | |
296 | 67e999be | bellard | void sparc_iommu_memory_rw(void *opaque, target_phys_addr_t addr, |
297 | 67e999be | bellard | uint8_t *buf, int len, int is_write) |
298 | a917d384 | pbrook | { |
299 | 5dcb6b91 | blueswir1 | int l;
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300 | 5dcb6b91 | blueswir1 | uint32_t flags; |
301 | 5dcb6b91 | blueswir1 | target_phys_addr_t page, phys_addr; |
302 | a917d384 | pbrook | |
303 | a917d384 | pbrook | while (len > 0) { |
304 | 8b0de438 | blueswir1 | page = addr & IOMMU_PAGE_MASK; |
305 | 8b0de438 | blueswir1 | l = (page + IOMMU_PAGE_SIZE) - addr; |
306 | a917d384 | pbrook | if (l > len)
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307 | a917d384 | pbrook | l = len; |
308 | a917d384 | pbrook | flags = iommu_page_get_flags(opaque, page); |
309 | 225d4be7 | blueswir1 | if (!(flags & IOPTE_VALID)) {
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310 | 225d4be7 | blueswir1 | iommu_bad_addr(opaque, page, is_write); |
311 | a917d384 | pbrook | return;
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312 | 225d4be7 | blueswir1 | } |
313 | 22548760 | blueswir1 | phys_addr = iommu_translate_pa(addr, flags); |
314 | a917d384 | pbrook | if (is_write) {
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315 | 225d4be7 | blueswir1 | if (!(flags & IOPTE_WRITE)) {
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316 | 225d4be7 | blueswir1 | iommu_bad_addr(opaque, page, is_write); |
317 | a917d384 | pbrook | return;
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318 | 225d4be7 | blueswir1 | } |
319 | a5cdf952 | blueswir1 | cpu_physical_memory_write(phys_addr, buf, l); |
320 | a917d384 | pbrook | } else {
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321 | a5cdf952 | blueswir1 | cpu_physical_memory_read(phys_addr, buf, l); |
322 | a917d384 | pbrook | } |
323 | a917d384 | pbrook | len -= l; |
324 | a917d384 | pbrook | buf += l; |
325 | a917d384 | pbrook | addr += l; |
326 | a917d384 | pbrook | } |
327 | a917d384 | pbrook | } |
328 | a917d384 | pbrook | |
329 | e80cfcfc | bellard | static void iommu_save(QEMUFile *f, void *opaque) |
330 | e80cfcfc | bellard | { |
331 | e80cfcfc | bellard | IOMMUState *s = opaque; |
332 | e80cfcfc | bellard | int i;
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333 | 3b46e624 | ths | |
334 | 66321a11 | bellard | for (i = 0; i < IOMMU_NREGS; i++) |
335 | f930d07e | blueswir1 | qemu_put_be32s(f, &s->regs[i]); |
336 | 5dcb6b91 | blueswir1 | qemu_put_be64s(f, &s->iostart); |
337 | e80cfcfc | bellard | } |
338 | e80cfcfc | bellard | |
339 | e80cfcfc | bellard | static int iommu_load(QEMUFile *f, void *opaque, int version_id) |
340 | e80cfcfc | bellard | { |
341 | e80cfcfc | bellard | IOMMUState *s = opaque; |
342 | e80cfcfc | bellard | int i;
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343 | 3b46e624 | ths | |
344 | 5dcb6b91 | blueswir1 | if (version_id != 2) |
345 | e80cfcfc | bellard | return -EINVAL;
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346 | e80cfcfc | bellard | |
347 | 66321a11 | bellard | for (i = 0; i < IOMMU_NREGS; i++) |
348 | fda77c2d | blueswir1 | qemu_get_be32s(f, &s->regs[i]); |
349 | 5dcb6b91 | blueswir1 | qemu_get_be64s(f, &s->iostart); |
350 | e80cfcfc | bellard | |
351 | e80cfcfc | bellard | return 0; |
352 | e80cfcfc | bellard | } |
353 | e80cfcfc | bellard | |
354 | e80cfcfc | bellard | static void iommu_reset(void *opaque) |
355 | e80cfcfc | bellard | { |
356 | e80cfcfc | bellard | IOMMUState *s = opaque; |
357 | e80cfcfc | bellard | |
358 | 66321a11 | bellard | memset(s->regs, 0, IOMMU_NREGS * 4); |
359 | e80cfcfc | bellard | s->iostart = 0;
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360 | 7fbfb139 | blueswir1 | s->regs[IOMMU_CTRL] = s->version; |
361 | 7fbfb139 | blueswir1 | s->regs[IOMMU_ARBEN] = IOMMU_MID; |
362 | 5ad6bb97 | blueswir1 | s->regs[IOMMU_AFSR] = IOMMU_AFSR_RESV; |
363 | 7b169687 | blueswir1 | s->regs[IOMMU_AER] = IOMMU_AER_EN_P0_ARB | IOMMU_AER_EN_P1_ARB; |
364 | e5e38121 | blueswir1 | s->regs[IOMMU_MASK_ID] = IOMMU_TS_MASK; |
365 | ff403da6 | blueswir1 | qemu_irq_lower(s->irq); |
366 | e80cfcfc | bellard | } |
367 | e80cfcfc | bellard | |
368 | ff403da6 | blueswir1 | void *iommu_init(target_phys_addr_t addr, uint32_t version, qemu_irq irq)
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369 | 420557e8 | bellard | { |
370 | 420557e8 | bellard | IOMMUState *s; |
371 | 8d5f07fa | bellard | int iommu_io_memory;
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372 | 420557e8 | bellard | |
373 | 420557e8 | bellard | s = qemu_mallocz(sizeof(IOMMUState));
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374 | 420557e8 | bellard | |
375 | 7fbfb139 | blueswir1 | s->version = version; |
376 | ff403da6 | blueswir1 | s->irq = irq; |
377 | 8d5f07fa | bellard | |
378 | 5ad6bb97 | blueswir1 | iommu_io_memory = cpu_register_io_memory(0, iommu_mem_read,
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379 | 5ad6bb97 | blueswir1 | iommu_mem_write, s); |
380 | 66321a11 | bellard | cpu_register_physical_memory(addr, IOMMU_NREGS * 4, iommu_io_memory);
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381 | 3b46e624 | ths | |
382 | 5dcb6b91 | blueswir1 | register_savevm("iommu", addr, 2, iommu_save, iommu_load, s); |
383 | e80cfcfc | bellard | qemu_register_reset(iommu_reset, s); |
384 | 7fbfb139 | blueswir1 | iommu_reset(s); |
385 | e80cfcfc | bellard | return s;
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386 | 420557e8 | bellard | } |