Revision 72af9170 hw/etraxfs_ser.c
| b/hw/etraxfs_ser.c | ||
|---|---|---|
| 30 | 30 |
|
| 31 | 31 |
#define D(x) |
| 32 | 32 |
|
| 33 |
#define RW_TR_CTRL 0x00 |
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#define RW_TR_DMA_EN 0x04 |
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#define RW_REC_CTRL 0x08 |
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#define RW_DOUT 0x1c |
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#define RS_STAT_DIN 0x20 |
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#define R_STAT_DIN 0x24 |
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#define RW_INTR_MASK 0x2c |
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#define RW_ACK_INTR 0x30 |
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#define R_INTR 0x34 |
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#define R_MASKED_INTR 0x38 |
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#define RW_TR_CTRL (0x00 / 4) |
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#define RW_TR_DMA_EN (0x04 / 4) |
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#define RW_REC_CTRL (0x08 / 4) |
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#define RW_DOUT (0x1c / 4) |
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#define RS_STAT_DIN (0x20 / 4) |
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#define R_STAT_DIN (0x24 / 4) |
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#define RW_INTR_MASK (0x2c / 4) |
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#define RW_ACK_INTR (0x30 / 4) |
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#define R_INTR (0x34 / 4) |
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#define R_MASKED_INTR (0x38 / 4) |
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#define R_MAX (0x3c / 4) |
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| 43 | 44 |
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| 44 | 45 |
#define STAT_DAV 16 |
| 45 | 46 |
#define STAT_TR_IDLE 22 |
| ... | ... | |
| 51 | 52 |
CharDriverState *chr; |
| 52 | 53 |
qemu_irq *irq; |
| 53 | 54 |
|
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/* This pending thing is a hack. */ |
|
| 54 | 56 |
int pending_tx; |
| 55 | 57 |
|
| 56 | 58 |
/* Control registers. */ |
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uint32_t rw_tr_ctrl; |
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uint32_t rw_tr_dma_en; |
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uint32_t rw_rec_ctrl; |
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uint32_t rs_stat_din; |
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uint32_t r_stat_din; |
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uint32_t rw_intr_mask; |
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uint32_t rw_ack_intr; |
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uint32_t r_intr; |
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uint32_t r_masked_intr; |
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uint32_t regs[R_MAX]; |
|
| 66 | 60 |
}; |
| 67 | 61 |
|
| 68 | 62 |
static void ser_update_irq(struct etrax_serial *s) |
| 69 | 63 |
{
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s->r_intr &= ~(s->rw_ack_intr); |
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s->r_masked_intr = s->r_intr & s->rw_intr_mask; |
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|
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D(printf("irq_mask=%x r_intr=%x rmi=%x airq=%x \n",
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s->rw_intr_mask, s->r_intr, |
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s->r_masked_intr, s->rw_ack_intr)); |
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qemu_set_irq(s->irq[0], !!s->r_masked_intr); |
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s->rw_ack_intr = 0; |
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s->regs[R_INTR] &= ~(s->regs[RW_ACK_INTR]); |
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s->regs[R_MASKED_INTR] = s->regs[R_INTR] & s->regs[RW_INTR_MASK]; |
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|
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qemu_set_irq(s->irq[0], !!s->regs[R_MASKED_INTR]); |
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s->regs[RW_ACK_INTR] = 0; |
|
| 78 | 69 |
} |
| 79 | 70 |
|
| 80 | 71 |
static uint32_t ser_readl (void *opaque, target_phys_addr_t addr) |
| ... | ... | |
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D(CPUState *env = s->env); |
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uint32_t r = 0; |
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|
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addr >>= 2; |
|
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switch (addr) |
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{
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case RW_TR_CTRL: |
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r = s->rw_tr_ctrl; |
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break; |
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case RW_TR_DMA_EN: |
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r = s->rw_tr_dma_en; |
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break; |
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case RS_STAT_DIN: |
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r = s->rs_stat_din; |
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/* clear dav. */ |
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s->rs_stat_din &= ~(1 << STAT_DAV); |
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break; |
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| 99 | 80 |
case R_STAT_DIN: |
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r = s->rs_stat_din; |
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break; |
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case RW_ACK_INTR: |
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D(printf("load rw_ack_intr=%x\n", s->rw_ack_intr));
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r = s->rw_ack_intr; |
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r = s->regs[RS_STAT_DIN]; |
|
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break; |
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case RW_INTR_MASK: |
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r = s->rw_intr_mask; |
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break; |
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case R_INTR: |
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D(printf("load r_intr=%x\n", s->r_intr));
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r = s->r_intr; |
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break; |
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case R_MASKED_INTR: |
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D(printf("load r_maked_intr=%x\n", s->r_masked_intr));
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r = s->r_masked_intr; |
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case RS_STAT_DIN: |
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r = s->regs[addr]; |
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/* Read side-effect: clear dav. */ |
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s->regs[addr] &= ~(1 << STAT_DAV); |
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break; |
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|
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default: |
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D(printf ("%s %x\n", __func__, addr));
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r = s->regs[addr]; |
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D(printf ("%s %x=%x\n", __func__, addr, r));
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break; |
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} |
| 122 | 93 |
return r; |
| ... | ... | |
| 129 | 100 |
unsigned char ch = value; |
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D(CPUState *env = s->env); |
| 131 | 102 |
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D(printf ("%s %x %x\n", __func__, addr, value));
|
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addr >>= 2; |
|
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switch (addr) |
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{
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case RW_TR_CTRL: |
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D(printf("rw_tr_ctrl=%x\n", value));
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s->rw_tr_ctrl = value; |
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break; |
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case RW_TR_DMA_EN: |
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D(printf("rw_tr_dma_en=%x\n", value));
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s->rw_tr_dma_en = value; |
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break; |
|
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case RW_DOUT: |
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qemu_chr_write(s->chr, &ch, 1); |
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s->r_intr |= 1;
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s->regs[R_INTR] |= 1;
|
|
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s->pending_tx = 1; |
| 111 |
s->regs[addr] = value; |
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break; |
| 147 | 113 |
case RW_ACK_INTR: |
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D(printf("rw_ack_intr=%x\n", value));
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s->rw_ack_intr = value; |
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if (s->pending_tx && (s->rw_ack_intr & 1)) {
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s->r_intr |= 1; |
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s->regs[addr] = value; |
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if (s->pending_tx && (s->regs[addr] & 1)) {
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s->regs[R_INTR] |= 1; |
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s->pending_tx = 0; |
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s->rw_ack_intr &= ~1;
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s->regs[addr] &= ~1;
|
|
| 154 | 119 |
} |
| 155 | 120 |
break; |
| 156 |
case RW_INTR_MASK: |
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D(printf("r_intr_mask=%x\n", value));
|
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s->rw_intr_mask = value; |
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break; |
|
| 160 | 121 |
default: |
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D(printf ("%s %x %x\n", __func__, addr, value));
|
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s->regs[addr] = value;
|
|
| 162 | 123 |
break; |
| 163 | 124 |
} |
| 164 | 125 |
ser_update_irq(s); |
| ... | ... | |
| 178 | 139 |
{
|
| 179 | 140 |
struct etrax_serial *s = opaque; |
| 180 | 141 |
|
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s->r_intr |= 8;
|
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s->rs_stat_din &= ~0xff;
|
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s->rs_stat_din |= (buf[0] & 0xff);
|
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s->rs_stat_din |= (1 << STAT_DAV); /* dav. */
|
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s->regs[R_INTR] |= 8;
|
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s->regs[RS_STAT_DIN] &= ~0xff;
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s->regs[RS_STAT_DIN] |= (buf[0] & 0xff);
|
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s->regs[RS_STAT_DIN] |= (1 << STAT_DAV); /* dav. */
|
|
| 185 | 146 |
ser_update_irq(s); |
| 186 | 147 |
} |
| 187 | 148 |
|
| ... | ... | |
| 191 | 152 |
int r; |
| 192 | 153 |
|
| 193 | 154 |
/* Is the receiver enabled? */ |
| 194 |
r = s->rw_rec_ctrl & 1;
|
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r = s->regs[RW_REC_CTRL] & 1;
|
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| 195 | 156 |
|
| 196 | 157 |
/* Pending rx data? */ |
| 197 |
r |= !(s->r_intr & 8);
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r |= !(s->regs[R_INTR] & 8);
|
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return r; |
| 199 | 160 |
} |
| 200 | 161 |
|
| ... | ... | |
| 216 | 177 |
s->chr = chr; |
| 217 | 178 |
|
| 218 | 179 |
/* transmitter begins ready and idle. */ |
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s->rs_stat_din |= (1 << STAT_TR_RDY);
|
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s->rs_stat_din |= (1 << STAT_TR_IDLE);
|
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s->regs[RS_STAT_DIN] |= (1 << STAT_TR_RDY);
|
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s->regs[RS_STAT_DIN] |= (1 << STAT_TR_IDLE);
|
|
| 221 | 182 |
|
| 222 | 183 |
qemu_chr_add_handlers(chr, serial_can_receive, serial_receive, |
| 223 | 184 |
serial_event, s); |
| 224 | 185 |
|
| 225 | 186 |
ser_regs = cpu_register_io_memory(0, ser_read, ser_write, s); |
| 226 |
cpu_register_physical_memory (base, 0x3c, ser_regs);
|
|
| 187 |
cpu_register_physical_memory (base, R_MAX * 4, ser_regs);
|
|
| 227 | 188 |
} |
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