root / hw / slavio_misc.c @ 72cf2d4f
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1 | 3475187d | bellard | /*
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2 | 3475187d | bellard | * QEMU Sparc SLAVIO aux io port emulation
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3 | 5fafdf24 | ths | *
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4 | 3475187d | bellard | * Copyright (c) 2005 Fabrice Bellard
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5 | 5fafdf24 | ths | *
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6 | 3475187d | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | 3475187d | bellard | * of this software and associated documentation files (the "Software"), to deal
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8 | 3475187d | bellard | * in the Software without restriction, including without limitation the rights
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9 | 3475187d | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | 3475187d | bellard | * copies of the Software, and to permit persons to whom the Software is
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11 | 3475187d | bellard | * furnished to do so, subject to the following conditions:
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12 | 3475187d | bellard | *
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13 | 3475187d | bellard | * The above copyright notice and this permission notice shall be included in
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14 | 3475187d | bellard | * all copies or substantial portions of the Software.
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15 | 3475187d | bellard | *
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16 | 3475187d | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | 3475187d | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | 3475187d | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | 3475187d | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | 3475187d | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | 3475187d | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | 3475187d | bellard | * THE SOFTWARE.
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23 | 3475187d | bellard | */
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24 | 2582cfa0 | Blue Swirl | |
25 | 87ecb68b | pbrook | #include "sun4m.h" |
26 | 87ecb68b | pbrook | #include "sysemu.h" |
27 | 2582cfa0 | Blue Swirl | #include "sysbus.h" |
28 | 87ecb68b | pbrook | |
29 | 3475187d | bellard | /* debug misc */
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30 | 3475187d | bellard | //#define DEBUG_MISC
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31 | 3475187d | bellard | |
32 | 3475187d | bellard | /*
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33 | 3475187d | bellard | * This is the auxio port, chip control and system control part of
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34 | 3475187d | bellard | * chip STP2001 (Slave I/O), also produced as NCR89C105. See
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35 | 3475187d | bellard | * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt
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36 | 3475187d | bellard | *
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37 | 3475187d | bellard | * This also includes the PMC CPU idle controller.
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38 | 3475187d | bellard | */
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39 | 3475187d | bellard | |
40 | 3475187d | bellard | #ifdef DEBUG_MISC
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41 | 001faf32 | Blue Swirl | #define MISC_DPRINTF(fmt, ...) \
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42 | 001faf32 | Blue Swirl | do { printf("MISC: " fmt , ## __VA_ARGS__); } while (0) |
43 | 3475187d | bellard | #else
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44 | 001faf32 | Blue Swirl | #define MISC_DPRINTF(fmt, ...)
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45 | 3475187d | bellard | #endif
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46 | 3475187d | bellard | |
47 | 3475187d | bellard | typedef struct MiscState { |
48 | 2582cfa0 | Blue Swirl | SysBusDevice busdev; |
49 | d537cf6c | pbrook | qemu_irq irq; |
50 | d37adb09 | Blue Swirl | uint32_t dummy; |
51 | 3475187d | bellard | uint8_t config; |
52 | 3475187d | bellard | uint8_t aux1, aux2; |
53 | bfa30a38 | blueswir1 | uint8_t diag, mctrl; |
54 | d37adb09 | Blue Swirl | uint8_t sysctrl; |
55 | 6a3b9cc9 | blueswir1 | uint16_t leds; |
56 | 2be17ebd | blueswir1 | qemu_irq fdc_tc; |
57 | 3475187d | bellard | } MiscState; |
58 | 3475187d | bellard | |
59 | 2582cfa0 | Blue Swirl | typedef struct APCState { |
60 | 2582cfa0 | Blue Swirl | SysBusDevice busdev; |
61 | 2582cfa0 | Blue Swirl | qemu_irq cpu_halt; |
62 | 2582cfa0 | Blue Swirl | } APCState; |
63 | 2582cfa0 | Blue Swirl | |
64 | 5aca8c3b | blueswir1 | #define MISC_SIZE 1 |
65 | a8f48dcc | blueswir1 | #define SYSCTRL_SIZE 4 |
66 | 3475187d | bellard | |
67 | 2be17ebd | blueswir1 | #define AUX1_TC 0x02 |
68 | 2be17ebd | blueswir1 | |
69 | 7debeb82 | blueswir1 | #define AUX2_PWROFF 0x01 |
70 | 7debeb82 | blueswir1 | #define AUX2_PWRINTCLR 0x02 |
71 | 7debeb82 | blueswir1 | #define AUX2_PWRFAIL 0x20 |
72 | 7debeb82 | blueswir1 | |
73 | 7debeb82 | blueswir1 | #define CFG_PWRINTEN 0x08 |
74 | 7debeb82 | blueswir1 | |
75 | 7debeb82 | blueswir1 | #define SYS_RESET 0x01 |
76 | 7debeb82 | blueswir1 | #define SYS_RESETSTAT 0x02 |
77 | 7debeb82 | blueswir1 | |
78 | 3475187d | bellard | static void slavio_misc_update_irq(void *opaque) |
79 | 3475187d | bellard | { |
80 | 3475187d | bellard | MiscState *s = opaque; |
81 | 3475187d | bellard | |
82 | 7debeb82 | blueswir1 | if ((s->aux2 & AUX2_PWRFAIL) && (s->config & CFG_PWRINTEN)) {
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83 | d537cf6c | pbrook | MISC_DPRINTF("Raise IRQ\n");
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84 | d537cf6c | pbrook | qemu_irq_raise(s->irq); |
85 | 3475187d | bellard | } else {
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86 | d537cf6c | pbrook | MISC_DPRINTF("Lower IRQ\n");
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87 | d537cf6c | pbrook | qemu_irq_lower(s->irq); |
88 | 3475187d | bellard | } |
89 | 3475187d | bellard | } |
90 | 3475187d | bellard | |
91 | 3475187d | bellard | static void slavio_misc_reset(void *opaque) |
92 | 3475187d | bellard | { |
93 | 3475187d | bellard | MiscState *s = opaque; |
94 | 3475187d | bellard | |
95 | 4e3b1ea1 | bellard | // Diagnostic and system control registers not cleared in reset
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96 | 3475187d | bellard | s->config = s->aux1 = s->aux2 = s->mctrl = 0;
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97 | 3475187d | bellard | } |
98 | 3475187d | bellard | |
99 | b2b6f6ec | Blue Swirl | static void slavio_set_power_fail(void *opaque, int irq, int power_failing) |
100 | 3475187d | bellard | { |
101 | 3475187d | bellard | MiscState *s = opaque; |
102 | 3475187d | bellard | |
103 | 3475187d | bellard | MISC_DPRINTF("Power fail: %d, config: %d\n", power_failing, s->config);
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104 | 7debeb82 | blueswir1 | if (power_failing && (s->config & CFG_PWRINTEN)) {
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105 | 7debeb82 | blueswir1 | s->aux2 |= AUX2_PWRFAIL; |
106 | 3475187d | bellard | } else {
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107 | 7debeb82 | blueswir1 | s->aux2 &= ~AUX2_PWRFAIL; |
108 | 3475187d | bellard | } |
109 | 3475187d | bellard | slavio_misc_update_irq(s); |
110 | 3475187d | bellard | } |
111 | 3475187d | bellard | |
112 | a8f48dcc | blueswir1 | static void slavio_cfg_mem_writeb(void *opaque, target_phys_addr_t addr, |
113 | a8f48dcc | blueswir1 | uint32_t val) |
114 | a8f48dcc | blueswir1 | { |
115 | a8f48dcc | blueswir1 | MiscState *s = opaque; |
116 | a8f48dcc | blueswir1 | |
117 | a8f48dcc | blueswir1 | MISC_DPRINTF("Write config %2.2x\n", val & 0xff); |
118 | a8f48dcc | blueswir1 | s->config = val & 0xff;
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119 | a8f48dcc | blueswir1 | slavio_misc_update_irq(s); |
120 | a8f48dcc | blueswir1 | } |
121 | a8f48dcc | blueswir1 | |
122 | a8f48dcc | blueswir1 | static uint32_t slavio_cfg_mem_readb(void *opaque, target_phys_addr_t addr) |
123 | a8f48dcc | blueswir1 | { |
124 | a8f48dcc | blueswir1 | MiscState *s = opaque; |
125 | a8f48dcc | blueswir1 | uint32_t ret = 0;
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126 | a8f48dcc | blueswir1 | |
127 | a8f48dcc | blueswir1 | ret = s->config; |
128 | a8f48dcc | blueswir1 | MISC_DPRINTF("Read config %2.2x\n", ret);
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129 | a8f48dcc | blueswir1 | return ret;
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130 | a8f48dcc | blueswir1 | } |
131 | a8f48dcc | blueswir1 | |
132 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const slavio_cfg_mem_read[3] = { |
133 | a8f48dcc | blueswir1 | slavio_cfg_mem_readb, |
134 | a8f48dcc | blueswir1 | NULL,
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135 | a8f48dcc | blueswir1 | NULL,
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136 | a8f48dcc | blueswir1 | }; |
137 | a8f48dcc | blueswir1 | |
138 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const slavio_cfg_mem_write[3] = { |
139 | a8f48dcc | blueswir1 | slavio_cfg_mem_writeb, |
140 | a8f48dcc | blueswir1 | NULL,
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141 | a8f48dcc | blueswir1 | NULL,
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142 | a8f48dcc | blueswir1 | }; |
143 | a8f48dcc | blueswir1 | |
144 | a8f48dcc | blueswir1 | static void slavio_diag_mem_writeb(void *opaque, target_phys_addr_t addr, |
145 | bfa30a38 | blueswir1 | uint32_t val) |
146 | 3475187d | bellard | { |
147 | 3475187d | bellard | MiscState *s = opaque; |
148 | 3475187d | bellard | |
149 | a8f48dcc | blueswir1 | MISC_DPRINTF("Write diag %2.2x\n", val & 0xff); |
150 | a8f48dcc | blueswir1 | s->diag = val & 0xff;
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151 | 3475187d | bellard | } |
152 | 3475187d | bellard | |
153 | a8f48dcc | blueswir1 | static uint32_t slavio_diag_mem_readb(void *opaque, target_phys_addr_t addr) |
154 | 3475187d | bellard | { |
155 | 3475187d | bellard | MiscState *s = opaque; |
156 | 3475187d | bellard | uint32_t ret = 0;
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157 | 3475187d | bellard | |
158 | a8f48dcc | blueswir1 | ret = s->diag; |
159 | a8f48dcc | blueswir1 | MISC_DPRINTF("Read diag %2.2x\n", ret);
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160 | a8f48dcc | blueswir1 | return ret;
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161 | a8f48dcc | blueswir1 | } |
162 | a8f48dcc | blueswir1 | |
163 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const slavio_diag_mem_read[3] = { |
164 | a8f48dcc | blueswir1 | slavio_diag_mem_readb, |
165 | a8f48dcc | blueswir1 | NULL,
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166 | a8f48dcc | blueswir1 | NULL,
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167 | a8f48dcc | blueswir1 | }; |
168 | a8f48dcc | blueswir1 | |
169 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const slavio_diag_mem_write[3] = { |
170 | a8f48dcc | blueswir1 | slavio_diag_mem_writeb, |
171 | a8f48dcc | blueswir1 | NULL,
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172 | a8f48dcc | blueswir1 | NULL,
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173 | a8f48dcc | blueswir1 | }; |
174 | a8f48dcc | blueswir1 | |
175 | a8f48dcc | blueswir1 | static void slavio_mdm_mem_writeb(void *opaque, target_phys_addr_t addr, |
176 | a8f48dcc | blueswir1 | uint32_t val) |
177 | a8f48dcc | blueswir1 | { |
178 | a8f48dcc | blueswir1 | MiscState *s = opaque; |
179 | a8f48dcc | blueswir1 | |
180 | a8f48dcc | blueswir1 | MISC_DPRINTF("Write modem control %2.2x\n", val & 0xff); |
181 | a8f48dcc | blueswir1 | s->mctrl = val & 0xff;
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182 | a8f48dcc | blueswir1 | } |
183 | a8f48dcc | blueswir1 | |
184 | a8f48dcc | blueswir1 | static uint32_t slavio_mdm_mem_readb(void *opaque, target_phys_addr_t addr) |
185 | a8f48dcc | blueswir1 | { |
186 | a8f48dcc | blueswir1 | MiscState *s = opaque; |
187 | a8f48dcc | blueswir1 | uint32_t ret = 0;
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188 | a8f48dcc | blueswir1 | |
189 | a8f48dcc | blueswir1 | ret = s->mctrl; |
190 | a8f48dcc | blueswir1 | MISC_DPRINTF("Read modem control %2.2x\n", ret);
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191 | 3475187d | bellard | return ret;
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192 | 3475187d | bellard | } |
193 | 3475187d | bellard | |
194 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const slavio_mdm_mem_read[3] = { |
195 | a8f48dcc | blueswir1 | slavio_mdm_mem_readb, |
196 | 7c560456 | blueswir1 | NULL,
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197 | 7c560456 | blueswir1 | NULL,
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198 | 3475187d | bellard | }; |
199 | 3475187d | bellard | |
200 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const slavio_mdm_mem_write[3] = { |
201 | a8f48dcc | blueswir1 | slavio_mdm_mem_writeb, |
202 | 7c560456 | blueswir1 | NULL,
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203 | 7c560456 | blueswir1 | NULL,
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204 | 3475187d | bellard | }; |
205 | 3475187d | bellard | |
206 | 0019ad53 | blueswir1 | static void slavio_aux1_mem_writeb(void *opaque, target_phys_addr_t addr, |
207 | 0019ad53 | blueswir1 | uint32_t val) |
208 | 0019ad53 | blueswir1 | { |
209 | 0019ad53 | blueswir1 | MiscState *s = opaque; |
210 | 0019ad53 | blueswir1 | |
211 | 0019ad53 | blueswir1 | MISC_DPRINTF("Write aux1 %2.2x\n", val & 0xff); |
212 | 2be17ebd | blueswir1 | if (val & AUX1_TC) {
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213 | 2be17ebd | blueswir1 | // Send a pulse to floppy terminal count line
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214 | 2be17ebd | blueswir1 | if (s->fdc_tc) {
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215 | 2be17ebd | blueswir1 | qemu_irq_raise(s->fdc_tc); |
216 | 2be17ebd | blueswir1 | qemu_irq_lower(s->fdc_tc); |
217 | 2be17ebd | blueswir1 | } |
218 | 2be17ebd | blueswir1 | val &= ~AUX1_TC; |
219 | 2be17ebd | blueswir1 | } |
220 | 0019ad53 | blueswir1 | s->aux1 = val & 0xff;
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221 | 0019ad53 | blueswir1 | } |
222 | 0019ad53 | blueswir1 | |
223 | 0019ad53 | blueswir1 | static uint32_t slavio_aux1_mem_readb(void *opaque, target_phys_addr_t addr) |
224 | 0019ad53 | blueswir1 | { |
225 | 0019ad53 | blueswir1 | MiscState *s = opaque; |
226 | 0019ad53 | blueswir1 | uint32_t ret = 0;
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227 | 0019ad53 | blueswir1 | |
228 | 0019ad53 | blueswir1 | ret = s->aux1; |
229 | 0019ad53 | blueswir1 | MISC_DPRINTF("Read aux1 %2.2x\n", ret);
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230 | 0019ad53 | blueswir1 | |
231 | 0019ad53 | blueswir1 | return ret;
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232 | 0019ad53 | blueswir1 | } |
233 | 0019ad53 | blueswir1 | |
234 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const slavio_aux1_mem_read[3] = { |
235 | 0019ad53 | blueswir1 | slavio_aux1_mem_readb, |
236 | 0019ad53 | blueswir1 | NULL,
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237 | 0019ad53 | blueswir1 | NULL,
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238 | 0019ad53 | blueswir1 | }; |
239 | 0019ad53 | blueswir1 | |
240 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const slavio_aux1_mem_write[3] = { |
241 | 0019ad53 | blueswir1 | slavio_aux1_mem_writeb, |
242 | 0019ad53 | blueswir1 | NULL,
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243 | 0019ad53 | blueswir1 | NULL,
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244 | 0019ad53 | blueswir1 | }; |
245 | 0019ad53 | blueswir1 | |
246 | 0019ad53 | blueswir1 | static void slavio_aux2_mem_writeb(void *opaque, target_phys_addr_t addr, |
247 | 0019ad53 | blueswir1 | uint32_t val) |
248 | 0019ad53 | blueswir1 | { |
249 | 0019ad53 | blueswir1 | MiscState *s = opaque; |
250 | 0019ad53 | blueswir1 | |
251 | 0019ad53 | blueswir1 | val &= AUX2_PWRINTCLR | AUX2_PWROFF; |
252 | 0019ad53 | blueswir1 | MISC_DPRINTF("Write aux2 %2.2x\n", val);
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253 | 0019ad53 | blueswir1 | val |= s->aux2 & AUX2_PWRFAIL; |
254 | 0019ad53 | blueswir1 | if (val & AUX2_PWRINTCLR) // Clear Power Fail int |
255 | 0019ad53 | blueswir1 | val &= AUX2_PWROFF; |
256 | 0019ad53 | blueswir1 | s->aux2 = val; |
257 | 0019ad53 | blueswir1 | if (val & AUX2_PWROFF)
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258 | 0019ad53 | blueswir1 | qemu_system_shutdown_request(); |
259 | 0019ad53 | blueswir1 | slavio_misc_update_irq(s); |
260 | 0019ad53 | blueswir1 | } |
261 | 0019ad53 | blueswir1 | |
262 | 0019ad53 | blueswir1 | static uint32_t slavio_aux2_mem_readb(void *opaque, target_phys_addr_t addr) |
263 | 0019ad53 | blueswir1 | { |
264 | 0019ad53 | blueswir1 | MiscState *s = opaque; |
265 | 0019ad53 | blueswir1 | uint32_t ret = 0;
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266 | 0019ad53 | blueswir1 | |
267 | 0019ad53 | blueswir1 | ret = s->aux2; |
268 | 0019ad53 | blueswir1 | MISC_DPRINTF("Read aux2 %2.2x\n", ret);
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269 | 0019ad53 | blueswir1 | |
270 | 0019ad53 | blueswir1 | return ret;
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271 | 0019ad53 | blueswir1 | } |
272 | 0019ad53 | blueswir1 | |
273 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const slavio_aux2_mem_read[3] = { |
274 | 0019ad53 | blueswir1 | slavio_aux2_mem_readb, |
275 | 0019ad53 | blueswir1 | NULL,
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276 | 0019ad53 | blueswir1 | NULL,
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277 | 0019ad53 | blueswir1 | }; |
278 | 0019ad53 | blueswir1 | |
279 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const slavio_aux2_mem_write[3] = { |
280 | 0019ad53 | blueswir1 | slavio_aux2_mem_writeb, |
281 | 0019ad53 | blueswir1 | NULL,
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282 | 0019ad53 | blueswir1 | NULL,
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283 | 0019ad53 | blueswir1 | }; |
284 | 0019ad53 | blueswir1 | |
285 | 0019ad53 | blueswir1 | static void apc_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) |
286 | 0019ad53 | blueswir1 | { |
287 | 2582cfa0 | Blue Swirl | APCState *s = opaque; |
288 | 0019ad53 | blueswir1 | |
289 | 0019ad53 | blueswir1 | MISC_DPRINTF("Write power management %2.2x\n", val & 0xff); |
290 | 6d0c293d | blueswir1 | qemu_irq_raise(s->cpu_halt); |
291 | 0019ad53 | blueswir1 | } |
292 | 0019ad53 | blueswir1 | |
293 | 0019ad53 | blueswir1 | static uint32_t apc_mem_readb(void *opaque, target_phys_addr_t addr) |
294 | 0019ad53 | blueswir1 | { |
295 | 0019ad53 | blueswir1 | uint32_t ret = 0;
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296 | 0019ad53 | blueswir1 | |
297 | 0019ad53 | blueswir1 | MISC_DPRINTF("Read power management %2.2x\n", ret);
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298 | 0019ad53 | blueswir1 | return ret;
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299 | 0019ad53 | blueswir1 | } |
300 | 0019ad53 | blueswir1 | |
301 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const apc_mem_read[3] = { |
302 | 0019ad53 | blueswir1 | apc_mem_readb, |
303 | 0019ad53 | blueswir1 | NULL,
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304 | 0019ad53 | blueswir1 | NULL,
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305 | 0019ad53 | blueswir1 | }; |
306 | 0019ad53 | blueswir1 | |
307 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const apc_mem_write[3] = { |
308 | 0019ad53 | blueswir1 | apc_mem_writeb, |
309 | 0019ad53 | blueswir1 | NULL,
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310 | 0019ad53 | blueswir1 | NULL,
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311 | 0019ad53 | blueswir1 | }; |
312 | 0019ad53 | blueswir1 | |
313 | bfa30a38 | blueswir1 | static uint32_t slavio_sysctrl_mem_readl(void *opaque, target_phys_addr_t addr) |
314 | bfa30a38 | blueswir1 | { |
315 | bfa30a38 | blueswir1 | MiscState *s = opaque; |
316 | a8f48dcc | blueswir1 | uint32_t ret = 0;
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317 | bfa30a38 | blueswir1 | |
318 | a8f48dcc | blueswir1 | switch (addr) {
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319 | bfa30a38 | blueswir1 | case 0: |
320 | bfa30a38 | blueswir1 | ret = s->sysctrl; |
321 | bfa30a38 | blueswir1 | break;
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322 | bfa30a38 | blueswir1 | default:
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323 | bfa30a38 | blueswir1 | break;
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324 | bfa30a38 | blueswir1 | } |
325 | 5626b017 | blueswir1 | MISC_DPRINTF("Read system control %08x\n", ret);
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326 | bfa30a38 | blueswir1 | return ret;
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327 | bfa30a38 | blueswir1 | } |
328 | bfa30a38 | blueswir1 | |
329 | bfa30a38 | blueswir1 | static void slavio_sysctrl_mem_writel(void *opaque, target_phys_addr_t addr, |
330 | bfa30a38 | blueswir1 | uint32_t val) |
331 | bfa30a38 | blueswir1 | { |
332 | bfa30a38 | blueswir1 | MiscState *s = opaque; |
333 | bfa30a38 | blueswir1 | |
334 | 5626b017 | blueswir1 | MISC_DPRINTF("Write system control %08x\n", val);
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335 | a8f48dcc | blueswir1 | switch (addr) {
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336 | bfa30a38 | blueswir1 | case 0: |
337 | 7debeb82 | blueswir1 | if (val & SYS_RESET) {
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338 | 7debeb82 | blueswir1 | s->sysctrl = SYS_RESETSTAT; |
339 | bfa30a38 | blueswir1 | qemu_system_reset_request(); |
340 | bfa30a38 | blueswir1 | } |
341 | bfa30a38 | blueswir1 | break;
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342 | bfa30a38 | blueswir1 | default:
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343 | bfa30a38 | blueswir1 | break;
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344 | bfa30a38 | blueswir1 | } |
345 | bfa30a38 | blueswir1 | } |
346 | bfa30a38 | blueswir1 | |
347 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const slavio_sysctrl_mem_read[3] = { |
348 | 7c560456 | blueswir1 | NULL,
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349 | 7c560456 | blueswir1 | NULL,
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350 | bfa30a38 | blueswir1 | slavio_sysctrl_mem_readl, |
351 | bfa30a38 | blueswir1 | }; |
352 | bfa30a38 | blueswir1 | |
353 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const slavio_sysctrl_mem_write[3] = { |
354 | 7c560456 | blueswir1 | NULL,
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355 | 7c560456 | blueswir1 | NULL,
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356 | bfa30a38 | blueswir1 | slavio_sysctrl_mem_writel, |
357 | bfa30a38 | blueswir1 | }; |
358 | bfa30a38 | blueswir1 | |
359 | 7c560456 | blueswir1 | static uint32_t slavio_led_mem_readw(void *opaque, target_phys_addr_t addr) |
360 | 6a3b9cc9 | blueswir1 | { |
361 | 6a3b9cc9 | blueswir1 | MiscState *s = opaque; |
362 | a8f48dcc | blueswir1 | uint32_t ret = 0;
|
363 | 6a3b9cc9 | blueswir1 | |
364 | a8f48dcc | blueswir1 | switch (addr) {
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365 | 6a3b9cc9 | blueswir1 | case 0: |
366 | 6a3b9cc9 | blueswir1 | ret = s->leds; |
367 | 6a3b9cc9 | blueswir1 | break;
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368 | 6a3b9cc9 | blueswir1 | default:
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369 | 6a3b9cc9 | blueswir1 | break;
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370 | 6a3b9cc9 | blueswir1 | } |
371 | 5626b017 | blueswir1 | MISC_DPRINTF("Read diagnostic LED %04x\n", ret);
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372 | 6a3b9cc9 | blueswir1 | return ret;
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373 | 6a3b9cc9 | blueswir1 | } |
374 | 6a3b9cc9 | blueswir1 | |
375 | 7c560456 | blueswir1 | static void slavio_led_mem_writew(void *opaque, target_phys_addr_t addr, |
376 | 6a3b9cc9 | blueswir1 | uint32_t val) |
377 | 6a3b9cc9 | blueswir1 | { |
378 | 6a3b9cc9 | blueswir1 | MiscState *s = opaque; |
379 | 6a3b9cc9 | blueswir1 | |
380 | 5626b017 | blueswir1 | MISC_DPRINTF("Write diagnostic LED %04x\n", val & 0xffff); |
381 | a8f48dcc | blueswir1 | switch (addr) {
|
382 | 6a3b9cc9 | blueswir1 | case 0: |
383 | d5296cb5 | blueswir1 | s->leds = val; |
384 | 6a3b9cc9 | blueswir1 | break;
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385 | 6a3b9cc9 | blueswir1 | default:
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386 | 6a3b9cc9 | blueswir1 | break;
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387 | 6a3b9cc9 | blueswir1 | } |
388 | 6a3b9cc9 | blueswir1 | } |
389 | 6a3b9cc9 | blueswir1 | |
390 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const slavio_led_mem_read[3] = { |
391 | 7c560456 | blueswir1 | NULL,
|
392 | 7c560456 | blueswir1 | slavio_led_mem_readw, |
393 | 7c560456 | blueswir1 | NULL,
|
394 | 6a3b9cc9 | blueswir1 | }; |
395 | 6a3b9cc9 | blueswir1 | |
396 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const slavio_led_mem_write[3] = { |
397 | 7c560456 | blueswir1 | NULL,
|
398 | 7c560456 | blueswir1 | slavio_led_mem_writew, |
399 | 7c560456 | blueswir1 | NULL,
|
400 | 6a3b9cc9 | blueswir1 | }; |
401 | 6a3b9cc9 | blueswir1 | |
402 | d37adb09 | Blue Swirl | static const VMStateDescription vmstate_misc = { |
403 | d37adb09 | Blue Swirl | .name ="slavio_misc",
|
404 | d37adb09 | Blue Swirl | .version_id = 1,
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405 | d37adb09 | Blue Swirl | .minimum_version_id = 1,
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406 | d37adb09 | Blue Swirl | .minimum_version_id_old = 1,
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407 | d37adb09 | Blue Swirl | .fields = (VMStateField []) { |
408 | d37adb09 | Blue Swirl | VMSTATE_UINT32(dummy, MiscState), |
409 | d37adb09 | Blue Swirl | VMSTATE_UINT8(config, MiscState), |
410 | d37adb09 | Blue Swirl | VMSTATE_UINT8(aux1, MiscState), |
411 | d37adb09 | Blue Swirl | VMSTATE_UINT8(aux2, MiscState), |
412 | d37adb09 | Blue Swirl | VMSTATE_UINT8(diag, MiscState), |
413 | d37adb09 | Blue Swirl | VMSTATE_UINT8(mctrl, MiscState), |
414 | d37adb09 | Blue Swirl | VMSTATE_UINT8(sysctrl, MiscState), |
415 | d37adb09 | Blue Swirl | VMSTATE_END_OF_LIST() |
416 | d37adb09 | Blue Swirl | } |
417 | d37adb09 | Blue Swirl | }; |
418 | 3475187d | bellard | |
419 | 81a322d4 | Gerd Hoffmann | static int apc_init1(SysBusDevice *dev) |
420 | 2582cfa0 | Blue Swirl | { |
421 | 2582cfa0 | Blue Swirl | APCState *s = FROM_SYSBUS(APCState, dev); |
422 | 2582cfa0 | Blue Swirl | int io;
|
423 | 3475187d | bellard | |
424 | 2582cfa0 | Blue Swirl | sysbus_init_irq(dev, &s->cpu_halt); |
425 | 2582cfa0 | Blue Swirl | |
426 | 2582cfa0 | Blue Swirl | /* Power management (APC) XXX: not a Slavio device */
|
427 | 2582cfa0 | Blue Swirl | io = cpu_register_io_memory(apc_mem_read, apc_mem_write, s); |
428 | 2582cfa0 | Blue Swirl | sysbus_init_mmio(dev, MISC_SIZE, io); |
429 | 81a322d4 | Gerd Hoffmann | return 0; |
430 | 2582cfa0 | Blue Swirl | } |
431 | 2582cfa0 | Blue Swirl | |
432 | 81a322d4 | Gerd Hoffmann | static int slavio_misc_init1(SysBusDevice *dev) |
433 | 2582cfa0 | Blue Swirl | { |
434 | 2582cfa0 | Blue Swirl | MiscState *s = FROM_SYSBUS(MiscState, dev); |
435 | 2582cfa0 | Blue Swirl | int io;
|
436 | 2582cfa0 | Blue Swirl | |
437 | 2582cfa0 | Blue Swirl | sysbus_init_irq(dev, &s->irq); |
438 | 2582cfa0 | Blue Swirl | sysbus_init_irq(dev, &s->fdc_tc); |
439 | 2582cfa0 | Blue Swirl | |
440 | 2582cfa0 | Blue Swirl | /* 8 bit registers */
|
441 | 2582cfa0 | Blue Swirl | /* Slavio control */
|
442 | 2582cfa0 | Blue Swirl | io = cpu_register_io_memory(slavio_cfg_mem_read, |
443 | 2582cfa0 | Blue Swirl | slavio_cfg_mem_write, s); |
444 | 2582cfa0 | Blue Swirl | sysbus_init_mmio(dev, MISC_SIZE, io); |
445 | 2582cfa0 | Blue Swirl | |
446 | 2582cfa0 | Blue Swirl | /* Diagnostics */
|
447 | 2582cfa0 | Blue Swirl | io = cpu_register_io_memory(slavio_diag_mem_read, |
448 | 2582cfa0 | Blue Swirl | slavio_diag_mem_write, s); |
449 | 2582cfa0 | Blue Swirl | sysbus_init_mmio(dev, MISC_SIZE, io); |
450 | 2582cfa0 | Blue Swirl | |
451 | 2582cfa0 | Blue Swirl | /* Modem control */
|
452 | 2582cfa0 | Blue Swirl | io = cpu_register_io_memory(slavio_mdm_mem_read, |
453 | 2582cfa0 | Blue Swirl | slavio_mdm_mem_write, s); |
454 | 2582cfa0 | Blue Swirl | sysbus_init_mmio(dev, MISC_SIZE, io); |
455 | 2582cfa0 | Blue Swirl | |
456 | 2582cfa0 | Blue Swirl | /* 16 bit registers */
|
457 | 2582cfa0 | Blue Swirl | /* ss600mp diag LEDs */
|
458 | 2582cfa0 | Blue Swirl | io = cpu_register_io_memory(slavio_led_mem_read, |
459 | 2582cfa0 | Blue Swirl | slavio_led_mem_write, s); |
460 | 2582cfa0 | Blue Swirl | sysbus_init_mmio(dev, MISC_SIZE, io); |
461 | 2582cfa0 | Blue Swirl | |
462 | 2582cfa0 | Blue Swirl | /* 32 bit registers */
|
463 | 2582cfa0 | Blue Swirl | /* System control */
|
464 | 2582cfa0 | Blue Swirl | io = cpu_register_io_memory(slavio_sysctrl_mem_read, |
465 | 2582cfa0 | Blue Swirl | slavio_sysctrl_mem_write, s); |
466 | 2582cfa0 | Blue Swirl | sysbus_init_mmio(dev, SYSCTRL_SIZE, io); |
467 | 2582cfa0 | Blue Swirl | |
468 | 2582cfa0 | Blue Swirl | /* AUX 1 (Misc System Functions) */
|
469 | 2582cfa0 | Blue Swirl | io = cpu_register_io_memory(slavio_aux1_mem_read, |
470 | 2582cfa0 | Blue Swirl | slavio_aux1_mem_write, s); |
471 | 2582cfa0 | Blue Swirl | sysbus_init_mmio(dev, MISC_SIZE, io); |
472 | 2582cfa0 | Blue Swirl | |
473 | 2582cfa0 | Blue Swirl | /* AUX 2 (Software Powerdown Control) */
|
474 | 2582cfa0 | Blue Swirl | io = cpu_register_io_memory(slavio_aux2_mem_read, |
475 | 2582cfa0 | Blue Swirl | slavio_aux2_mem_write, s); |
476 | 2582cfa0 | Blue Swirl | sysbus_init_mmio(dev, MISC_SIZE, io); |
477 | 2582cfa0 | Blue Swirl | |
478 | b2b6f6ec | Blue Swirl | qdev_init_gpio_in(&dev->qdev, slavio_set_power_fail, 1);
|
479 | b2b6f6ec | Blue Swirl | |
480 | d37adb09 | Blue Swirl | vmstate_register(-1, &vmstate_misc, s);
|
481 | a08d4367 | Jan Kiszka | qemu_register_reset(slavio_misc_reset, s); |
482 | 3475187d | bellard | slavio_misc_reset(s); |
483 | 81a322d4 | Gerd Hoffmann | return 0; |
484 | 2582cfa0 | Blue Swirl | } |
485 | 0019ad53 | blueswir1 | |
486 | 2582cfa0 | Blue Swirl | static SysBusDeviceInfo slavio_misc_info = {
|
487 | 2582cfa0 | Blue Swirl | .init = slavio_misc_init1, |
488 | 2582cfa0 | Blue Swirl | .qdev.name = "slavio_misc",
|
489 | 2582cfa0 | Blue Swirl | .qdev.size = sizeof(MiscState),
|
490 | 2582cfa0 | Blue Swirl | }; |
491 | 2582cfa0 | Blue Swirl | |
492 | 2582cfa0 | Blue Swirl | static SysBusDeviceInfo apc_info = {
|
493 | 2582cfa0 | Blue Swirl | .init = apc_init1, |
494 | 2582cfa0 | Blue Swirl | .qdev.name = "apc",
|
495 | 2582cfa0 | Blue Swirl | .qdev.size = sizeof(MiscState),
|
496 | 2582cfa0 | Blue Swirl | }; |
497 | 2582cfa0 | Blue Swirl | |
498 | 2582cfa0 | Blue Swirl | static void slavio_misc_register_devices(void) |
499 | 2582cfa0 | Blue Swirl | { |
500 | 2582cfa0 | Blue Swirl | sysbus_register_withprop(&slavio_misc_info); |
501 | 2582cfa0 | Blue Swirl | sysbus_register_withprop(&apc_info); |
502 | 3475187d | bellard | } |
503 | 2582cfa0 | Blue Swirl | |
504 | 2582cfa0 | Blue Swirl | device_init(slavio_misc_register_devices) |