Revision 72f44c8c hw/apb_pci.c
| b/hw/apb_pci.c | ||
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Ultrasparc PCI host is called the PCI Bus Module (PBM). The APB is |
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the secondary PCI bridge. */ |
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#include "hw.h"
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#include "sysbus.h"
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#include "pci.h" |
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/* debug APB */ |
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typedef target_phys_addr_t pci_addr_t; |
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#include "pci_host.h" |
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typedef PCIHostState APBState; |
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typedef struct APBState {
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SysBusDevice busdev; |
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PCIHostState host_state; |
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} APBState; |
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static void pci_apb_config_writel (void *opaque, target_phys_addr_t addr, |
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uint32_t val) |
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#endif |
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APB_DPRINTF("config_writel addr " TARGET_FMT_plx " val %x\n", addr,
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val); |
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s->config_reg = val; |
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s->host_state.config_reg = val;
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} |
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static uint32_t pci_apb_config_readl (void *opaque, |
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APBState *s = opaque; |
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uint32_t val; |
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val = s->config_reg; |
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val = s->host_state.config_reg;
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#ifdef TARGET_WORDS_BIGENDIAN |
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val = bswap32(val); |
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#endif |
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target_phys_addr_t mem_base, |
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qemu_irq *pic, PCIBus **bus2, PCIBus **bus3) |
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{
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APBState *s;
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PCIDevice *d;
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int pci_mem_config, pci_mem_data, apb_config, pci_ioport;
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DeviceState *dev;
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SysBusDevice *s;
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APBState *d;
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s = qemu_mallocz(sizeof(APBState)); |
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/* Ultrasparc PBM main bus */ |
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s->bus = pci_register_bus(NULL, "pci", |
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pci_apb_set_irq, pci_pbm_map_irq, pic, 0, 32); |
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dev = qdev_create(NULL, "pbm"); |
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qdev_init(dev); |
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s = sysbus_from_qdev(dev); |
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/* apb_config */ |
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sysbus_mmio_map(s, 0, special_base + 0x2000ULL); |
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/* pci_ioport */ |
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sysbus_mmio_map(s, 1, special_base + 0x2000000ULL); |
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/* mem_config: XXX size should be 4G-prom */ |
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sysbus_mmio_map(s, 2, special_base + 0x1000000ULL); |
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/* mem_data */ |
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sysbus_mmio_map(s, 3, mem_base); |
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d = FROM_SYSBUS(APBState, s); |
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d->host_state.bus = pci_register_bus(NULL, "pci", |
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pci_apb_set_irq, pci_pbm_map_irq, pic, |
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0, 32); |
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pci_create_simple(d->host_state.bus, 0, "pbm"); |
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/* APB secondary busses */ |
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*bus2 = pci_bridge_init(d->host_state.bus, 8, PCI_VENDOR_ID_SUN, |
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PCI_DEVICE_ID_SUN_SIMBA, pci_apb_map_irq, |
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"Advanced PCI Bus secondary bridge 1"); |
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*bus3 = pci_bridge_init(d->host_state.bus, 9, PCI_VENDOR_ID_SUN, |
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PCI_DEVICE_ID_SUN_SIMBA, pci_apb_map_irq, |
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"Advanced PCI Bus secondary bridge 2"); |
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pci_mem_config = cpu_register_io_memory(pci_apb_config_read, |
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pci_apb_config_write, s); |
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return d->host_state.bus; |
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} |
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static void pci_pbm_init_device(SysBusDevice *dev) |
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{
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APBState *s; |
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int pci_mem_config, pci_mem_data, apb_config, pci_ioport; |
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s = FROM_SYSBUS(APBState, dev); |
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/* apb_config */ |
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apb_config = cpu_register_io_memory(apb_config_read, |
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apb_config_write, s); |
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pci_mem_data = cpu_register_io_memory(pci_apb_read,
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pci_apb_write, s);
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sysbus_init_mmio(dev, 0x40ULL, apb_config);
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/* pci_ioport */
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pci_ioport = cpu_register_io_memory(pci_apb_ioread, |
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pci_apb_iowrite, s); |
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sysbus_init_mmio(dev, 0x10000ULL, pci_ioport); |
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/* mem_config */ |
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pci_mem_config = cpu_register_io_memory(pci_apb_config_read, |
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pci_apb_config_write, s); |
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sysbus_init_mmio(dev, 0x10ULL, pci_mem_config); |
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/* mem_data */ |
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pci_mem_data = cpu_register_io_memory(pci_apb_read, |
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pci_apb_write, &s->host_state); |
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sysbus_init_mmio(dev, 0x10000000ULL, pci_mem_data); |
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} |
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cpu_register_physical_memory(special_base + 0x2000ULL, 0x40, apb_config); |
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cpu_register_physical_memory(special_base + 0x1000000ULL, 0x10, |
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pci_mem_config); |
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cpu_register_physical_memory(special_base + 0x2000000ULL, 0x10000, |
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pci_ioport); |
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cpu_register_physical_memory(mem_base, 0x10000000, |
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pci_mem_data); // XXX size should be 4G-prom |
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d = pci_register_device(s->bus, "Advanced PCI Bus", sizeof(PCIDevice), |
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0, NULL, NULL); |
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static void pbm_pci_host_init(PCIDevice *d) |
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{
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pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_SUN); |
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pci_config_set_device_id(d->config, PCI_DEVICE_ID_SUN_SABRE); |
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d->config[0x04] = 0x06; // command = bus master, pci mem |
| ... | ... | |
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pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST); |
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d->config[0x0D] = 0x10; // latency_timer |
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d->config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type |
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} |
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/* APB secondary busses */ |
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*bus2 = pci_bridge_init(s->bus, 8, PCI_VENDOR_ID_SUN, |
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PCI_DEVICE_ID_SUN_SIMBA, pci_apb_map_irq, |
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"Advanced PCI Bus secondary bridge 1"); |
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*bus3 = pci_bridge_init(s->bus, 9, PCI_VENDOR_ID_SUN, |
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PCI_DEVICE_ID_SUN_SIMBA, pci_apb_map_irq, |
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"Advanced PCI Bus secondary bridge 2"); |
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return s->bus; |
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static PCIDeviceInfo pbm_pci_host_info = {
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.qdev.name = "pbm", |
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.qdev.size = sizeof(PCIDevice), |
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.init = pbm_pci_host_init, |
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}; |
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static void pbm_register_devices(void) |
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{
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sysbus_register_dev("pbm", sizeof(APBState), pci_pbm_init_device);
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pci_qdev_register(&pbm_pci_host_info); |
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} |
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device_init(pbm_register_devices) |
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