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1 | 574bbf7b | bellard | /*
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2 | 574bbf7b | bellard | * APIC support
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3 | 5fafdf24 | ths | *
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4 | 574bbf7b | bellard | * Copyright (c) 2004-2005 Fabrice Bellard
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5 | 574bbf7b | bellard | *
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6 | 574bbf7b | bellard | * This library is free software; you can redistribute it and/or
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7 | 574bbf7b | bellard | * modify it under the terms of the GNU Lesser General Public
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8 | 574bbf7b | bellard | * License as published by the Free Software Foundation; either
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9 | 574bbf7b | bellard | * version 2 of the License, or (at your option) any later version.
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10 | 574bbf7b | bellard | *
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11 | 574bbf7b | bellard | * This library is distributed in the hope that it will be useful,
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12 | 574bbf7b | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | 574bbf7b | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | 574bbf7b | bellard | * Lesser General Public License for more details.
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15 | 574bbf7b | bellard | *
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16 | 574bbf7b | bellard | * You should have received a copy of the GNU Lesser General Public
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17 | 8167ee88 | Blue Swirl | * License along with this library; if not, see <http://www.gnu.org/licenses/>
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18 | 574bbf7b | bellard | */
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19 | 87ecb68b | pbrook | #include "hw.h" |
20 | 87ecb68b | pbrook | #include "pc.h" |
21 | aa28b9bf | Blue Swirl | #include "apic.h" |
22 | 54c96da7 | Michael S. Tsirkin | #include "pci.h" |
23 | 54c96da7 | Michael S. Tsirkin | #include "msix.h" |
24 | 87ecb68b | pbrook | #include "qemu-timer.h" |
25 | bb7e7293 | aurel32 | #include "host-utils.h" |
26 | 8d2ba1fb | Jan Kiszka | #include "kvm.h" |
27 | 574bbf7b | bellard | |
28 | 574bbf7b | bellard | //#define DEBUG_APIC
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29 | 0a3c5921 | Blue Swirl | //#define DEBUG_COALESCING
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30 | 0a3c5921 | Blue Swirl | |
31 | 0a3c5921 | Blue Swirl | #ifdef DEBUG_APIC
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32 | 0a3c5921 | Blue Swirl | #define DPRINTF(fmt, ...) \
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33 | 0a3c5921 | Blue Swirl | do { printf("apic: " fmt , ## __VA_ARGS__); } while (0) |
34 | 0a3c5921 | Blue Swirl | #else
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35 | 0a3c5921 | Blue Swirl | #define DPRINTF(fmt, ...)
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36 | 0a3c5921 | Blue Swirl | #endif
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37 | 0a3c5921 | Blue Swirl | |
38 | 0a3c5921 | Blue Swirl | #ifdef DEBUG_COALESCING
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39 | 0a3c5921 | Blue Swirl | #define DPRINTF_C(fmt, ...) \
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40 | 0a3c5921 | Blue Swirl | do { printf("apic: " fmt , ## __VA_ARGS__); } while (0) |
41 | 0a3c5921 | Blue Swirl | #else
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42 | 0a3c5921 | Blue Swirl | #define DPRINTF_C(fmt, ...)
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43 | 0a3c5921 | Blue Swirl | #endif
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44 | 574bbf7b | bellard | |
45 | 574bbf7b | bellard | /* APIC Local Vector Table */
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46 | 574bbf7b | bellard | #define APIC_LVT_TIMER 0 |
47 | 574bbf7b | bellard | #define APIC_LVT_THERMAL 1 |
48 | 574bbf7b | bellard | #define APIC_LVT_PERFORM 2 |
49 | 574bbf7b | bellard | #define APIC_LVT_LINT0 3 |
50 | 574bbf7b | bellard | #define APIC_LVT_LINT1 4 |
51 | 574bbf7b | bellard | #define APIC_LVT_ERROR 5 |
52 | 574bbf7b | bellard | #define APIC_LVT_NB 6 |
53 | 574bbf7b | bellard | |
54 | 574bbf7b | bellard | /* APIC delivery modes */
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55 | 574bbf7b | bellard | #define APIC_DM_FIXED 0 |
56 | 574bbf7b | bellard | #define APIC_DM_LOWPRI 1 |
57 | 574bbf7b | bellard | #define APIC_DM_SMI 2 |
58 | 574bbf7b | bellard | #define APIC_DM_NMI 4 |
59 | 574bbf7b | bellard | #define APIC_DM_INIT 5 |
60 | 574bbf7b | bellard | #define APIC_DM_SIPI 6 |
61 | 574bbf7b | bellard | #define APIC_DM_EXTINT 7 |
62 | 574bbf7b | bellard | |
63 | d592d303 | bellard | /* APIC destination mode */
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64 | d592d303 | bellard | #define APIC_DESTMODE_FLAT 0xf |
65 | d592d303 | bellard | #define APIC_DESTMODE_CLUSTER 1 |
66 | d592d303 | bellard | |
67 | 574bbf7b | bellard | #define APIC_TRIGGER_EDGE 0 |
68 | 574bbf7b | bellard | #define APIC_TRIGGER_LEVEL 1 |
69 | 574bbf7b | bellard | |
70 | 574bbf7b | bellard | #define APIC_LVT_TIMER_PERIODIC (1<<17) |
71 | 574bbf7b | bellard | #define APIC_LVT_MASKED (1<<16) |
72 | 574bbf7b | bellard | #define APIC_LVT_LEVEL_TRIGGER (1<<15) |
73 | 574bbf7b | bellard | #define APIC_LVT_REMOTE_IRR (1<<14) |
74 | 574bbf7b | bellard | #define APIC_INPUT_POLARITY (1<<13) |
75 | 574bbf7b | bellard | #define APIC_SEND_PENDING (1<<12) |
76 | 574bbf7b | bellard | |
77 | 574bbf7b | bellard | #define ESR_ILLEGAL_ADDRESS (1 << 7) |
78 | 574bbf7b | bellard | |
79 | 574bbf7b | bellard | #define APIC_SV_ENABLE (1 << 8) |
80 | 574bbf7b | bellard | |
81 | d3e9db93 | bellard | #define MAX_APICS 255 |
82 | d3e9db93 | bellard | #define MAX_APIC_WORDS 8 |
83 | d3e9db93 | bellard | |
84 | 54c96da7 | Michael S. Tsirkin | /* Intel APIC constants: from include/asm/msidef.h */
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85 | 54c96da7 | Michael S. Tsirkin | #define MSI_DATA_VECTOR_SHIFT 0 |
86 | 54c96da7 | Michael S. Tsirkin | #define MSI_DATA_VECTOR_MASK 0x000000ff |
87 | 54c96da7 | Michael S. Tsirkin | #define MSI_DATA_DELIVERY_MODE_SHIFT 8 |
88 | 54c96da7 | Michael S. Tsirkin | #define MSI_DATA_TRIGGER_SHIFT 15 |
89 | 54c96da7 | Michael S. Tsirkin | #define MSI_DATA_LEVEL_SHIFT 14 |
90 | 54c96da7 | Michael S. Tsirkin | #define MSI_ADDR_DEST_MODE_SHIFT 2 |
91 | 54c96da7 | Michael S. Tsirkin | #define MSI_ADDR_DEST_ID_SHIFT 12 |
92 | 54c96da7 | Michael S. Tsirkin | #define MSI_ADDR_DEST_ID_MASK 0x00ffff0 |
93 | 54c96da7 | Michael S. Tsirkin | |
94 | 54c96da7 | Michael S. Tsirkin | #define MSI_ADDR_BASE 0xfee00000 |
95 | 54c96da7 | Michael S. Tsirkin | #define MSI_ADDR_SIZE 0x100000 |
96 | 54c96da7 | Michael S. Tsirkin | |
97 | 574bbf7b | bellard | typedef struct APICState { |
98 | 574bbf7b | bellard | CPUState *cpu_env; |
99 | 574bbf7b | bellard | uint32_t apicbase; |
100 | 574bbf7b | bellard | uint8_t id; |
101 | d592d303 | bellard | uint8_t arb_id; |
102 | 574bbf7b | bellard | uint8_t tpr; |
103 | 574bbf7b | bellard | uint32_t spurious_vec; |
104 | d592d303 | bellard | uint8_t log_dest; |
105 | d592d303 | bellard | uint8_t dest_mode; |
106 | 574bbf7b | bellard | uint32_t isr[8]; /* in service register */ |
107 | 574bbf7b | bellard | uint32_t tmr[8]; /* trigger mode register */ |
108 | 574bbf7b | bellard | uint32_t irr[8]; /* interrupt request register */ |
109 | 574bbf7b | bellard | uint32_t lvt[APIC_LVT_NB]; |
110 | 574bbf7b | bellard | uint32_t esr; /* error register */
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111 | 574bbf7b | bellard | uint32_t icr[2];
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112 | 574bbf7b | bellard | |
113 | 574bbf7b | bellard | uint32_t divide_conf; |
114 | 574bbf7b | bellard | int count_shift;
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115 | 574bbf7b | bellard | uint32_t initial_count; |
116 | 574bbf7b | bellard | int64_t initial_count_load_time, next_time; |
117 | 678e12cc | Gleb Natapov | uint32_t idx; |
118 | 574bbf7b | bellard | QEMUTimer *timer; |
119 | b09ea7d5 | Gleb Natapov | int sipi_vector;
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120 | b09ea7d5 | Gleb Natapov | int wait_for_sipi;
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121 | 574bbf7b | bellard | } APICState; |
122 | 574bbf7b | bellard | |
123 | 574bbf7b | bellard | static int apic_io_memory; |
124 | d3e9db93 | bellard | static APICState *local_apics[MAX_APICS + 1]; |
125 | 678e12cc | Gleb Natapov | static int last_apic_idx = 0; |
126 | 73822ec8 | aliguori | static int apic_irq_delivered; |
127 | 73822ec8 | aliguori | |
128 | d592d303 | bellard | |
129 | d592d303 | bellard | static void apic_set_irq(APICState *s, int vector_num, int trigger_mode); |
130 | d592d303 | bellard | static void apic_update_irq(APICState *s); |
131 | 610626af | aliguori | static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask, |
132 | 610626af | aliguori | uint8_t dest, uint8_t dest_mode); |
133 | d592d303 | bellard | |
134 | 3b63c04e | aurel32 | /* Find first bit starting from msb */
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135 | 3b63c04e | aurel32 | static int fls_bit(uint32_t value) |
136 | 3b63c04e | aurel32 | { |
137 | 3b63c04e | aurel32 | return 31 - clz32(value); |
138 | 3b63c04e | aurel32 | } |
139 | 3b63c04e | aurel32 | |
140 | e95f5491 | aurel32 | /* Find first bit starting from lsb */
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141 | d3e9db93 | bellard | static int ffs_bit(uint32_t value) |
142 | d3e9db93 | bellard | { |
143 | bb7e7293 | aurel32 | return ctz32(value);
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144 | d3e9db93 | bellard | } |
145 | d3e9db93 | bellard | |
146 | d3e9db93 | bellard | static inline void set_bit(uint32_t *tab, int index) |
147 | d3e9db93 | bellard | { |
148 | d3e9db93 | bellard | int i, mask;
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149 | d3e9db93 | bellard | i = index >> 5;
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150 | d3e9db93 | bellard | mask = 1 << (index & 0x1f); |
151 | d3e9db93 | bellard | tab[i] |= mask; |
152 | d3e9db93 | bellard | } |
153 | d3e9db93 | bellard | |
154 | d3e9db93 | bellard | static inline void reset_bit(uint32_t *tab, int index) |
155 | d3e9db93 | bellard | { |
156 | d3e9db93 | bellard | int i, mask;
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157 | d3e9db93 | bellard | i = index >> 5;
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158 | d3e9db93 | bellard | mask = 1 << (index & 0x1f); |
159 | d3e9db93 | bellard | tab[i] &= ~mask; |
160 | d3e9db93 | bellard | } |
161 | d3e9db93 | bellard | |
162 | 73822ec8 | aliguori | static inline int get_bit(uint32_t *tab, int index) |
163 | 73822ec8 | aliguori | { |
164 | 73822ec8 | aliguori | int i, mask;
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165 | 73822ec8 | aliguori | i = index >> 5;
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166 | 73822ec8 | aliguori | mask = 1 << (index & 0x1f); |
167 | 73822ec8 | aliguori | return !!(tab[i] & mask);
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168 | 73822ec8 | aliguori | } |
169 | 73822ec8 | aliguori | |
170 | 1a7de94a | aurel32 | static void apic_local_deliver(CPUState *env, int vector) |
171 | a5b38b51 | aurel32 | { |
172 | a5b38b51 | aurel32 | APICState *s = env->apic_state; |
173 | a5b38b51 | aurel32 | uint32_t lvt = s->lvt[vector]; |
174 | a5b38b51 | aurel32 | int trigger_mode;
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175 | a5b38b51 | aurel32 | |
176 | 0a3c5921 | Blue Swirl | DPRINTF("%s: vector %d delivery mode %d\n", __func__, vector,
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177 | 0a3c5921 | Blue Swirl | (lvt >> 8) & 7); |
178 | a5b38b51 | aurel32 | if (lvt & APIC_LVT_MASKED)
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179 | a5b38b51 | aurel32 | return;
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180 | a5b38b51 | aurel32 | |
181 | a5b38b51 | aurel32 | switch ((lvt >> 8) & 7) { |
182 | a5b38b51 | aurel32 | case APIC_DM_SMI:
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183 | a5b38b51 | aurel32 | cpu_interrupt(env, CPU_INTERRUPT_SMI); |
184 | a5b38b51 | aurel32 | break;
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185 | a5b38b51 | aurel32 | |
186 | a5b38b51 | aurel32 | case APIC_DM_NMI:
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187 | a5b38b51 | aurel32 | cpu_interrupt(env, CPU_INTERRUPT_NMI); |
188 | a5b38b51 | aurel32 | break;
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189 | a5b38b51 | aurel32 | |
190 | a5b38b51 | aurel32 | case APIC_DM_EXTINT:
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191 | a5b38b51 | aurel32 | cpu_interrupt(env, CPU_INTERRUPT_HARD); |
192 | a5b38b51 | aurel32 | break;
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193 | a5b38b51 | aurel32 | |
194 | a5b38b51 | aurel32 | case APIC_DM_FIXED:
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195 | a5b38b51 | aurel32 | trigger_mode = APIC_TRIGGER_EDGE; |
196 | a5b38b51 | aurel32 | if ((vector == APIC_LVT_LINT0 || vector == APIC_LVT_LINT1) &&
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197 | a5b38b51 | aurel32 | (lvt & APIC_LVT_LEVEL_TRIGGER)) |
198 | a5b38b51 | aurel32 | trigger_mode = APIC_TRIGGER_LEVEL; |
199 | a5b38b51 | aurel32 | apic_set_irq(s, lvt & 0xff, trigger_mode);
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200 | a5b38b51 | aurel32 | } |
201 | a5b38b51 | aurel32 | } |
202 | a5b38b51 | aurel32 | |
203 | 1a7de94a | aurel32 | void apic_deliver_pic_intr(CPUState *env, int level) |
204 | 1a7de94a | aurel32 | { |
205 | 1a7de94a | aurel32 | if (level)
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206 | 1a7de94a | aurel32 | apic_local_deliver(env, APIC_LVT_LINT0); |
207 | 1a7de94a | aurel32 | else {
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208 | 1a7de94a | aurel32 | APICState *s = env->apic_state; |
209 | 1a7de94a | aurel32 | uint32_t lvt = s->lvt[APIC_LVT_LINT0]; |
210 | 1a7de94a | aurel32 | |
211 | 1a7de94a | aurel32 | switch ((lvt >> 8) & 7) { |
212 | 1a7de94a | aurel32 | case APIC_DM_FIXED:
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213 | 1a7de94a | aurel32 | if (!(lvt & APIC_LVT_LEVEL_TRIGGER))
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214 | 1a7de94a | aurel32 | break;
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215 | 1a7de94a | aurel32 | reset_bit(s->irr, lvt & 0xff);
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216 | 1a7de94a | aurel32 | /* fall through */
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217 | 1a7de94a | aurel32 | case APIC_DM_EXTINT:
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218 | 1a7de94a | aurel32 | cpu_reset_interrupt(env, CPU_INTERRUPT_HARD); |
219 | 1a7de94a | aurel32 | break;
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220 | 1a7de94a | aurel32 | } |
221 | 1a7de94a | aurel32 | } |
222 | 1a7de94a | aurel32 | } |
223 | 1a7de94a | aurel32 | |
224 | d3e9db93 | bellard | #define foreach_apic(apic, deliver_bitmask, code) \
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225 | d3e9db93 | bellard | {\ |
226 | d3e9db93 | bellard | int __i, __j, __mask;\
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227 | d3e9db93 | bellard | for(__i = 0; __i < MAX_APIC_WORDS; __i++) {\ |
228 | d3e9db93 | bellard | __mask = deliver_bitmask[__i];\ |
229 | d3e9db93 | bellard | if (__mask) {\
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230 | d3e9db93 | bellard | for(__j = 0; __j < 32; __j++) {\ |
231 | d3e9db93 | bellard | if (__mask & (1 << __j)) {\ |
232 | d3e9db93 | bellard | apic = local_apics[__i * 32 + __j];\
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233 | d3e9db93 | bellard | if (apic) {\
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234 | d3e9db93 | bellard | code;\ |
235 | d3e9db93 | bellard | }\ |
236 | d3e9db93 | bellard | }\ |
237 | d3e9db93 | bellard | }\ |
238 | d3e9db93 | bellard | }\ |
239 | d3e9db93 | bellard | }\ |
240 | d3e9db93 | bellard | } |
241 | d3e9db93 | bellard | |
242 | 5fafdf24 | ths | static void apic_bus_deliver(const uint32_t *deliver_bitmask, |
243 | d3e9db93 | bellard | uint8_t delivery_mode, |
244 | d592d303 | bellard | uint8_t vector_num, uint8_t polarity, |
245 | d592d303 | bellard | uint8_t trigger_mode) |
246 | d592d303 | bellard | { |
247 | d592d303 | bellard | APICState *apic_iter; |
248 | d592d303 | bellard | |
249 | d592d303 | bellard | switch (delivery_mode) {
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250 | d592d303 | bellard | case APIC_DM_LOWPRI:
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251 | 8dd69b8f | bellard | /* XXX: search for focus processor, arbitration */
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252 | d3e9db93 | bellard | { |
253 | d3e9db93 | bellard | int i, d;
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254 | d3e9db93 | bellard | d = -1;
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255 | d3e9db93 | bellard | for(i = 0; i < MAX_APIC_WORDS; i++) { |
256 | d3e9db93 | bellard | if (deliver_bitmask[i]) {
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257 | d3e9db93 | bellard | d = i * 32 + ffs_bit(deliver_bitmask[i]);
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258 | d3e9db93 | bellard | break;
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259 | d3e9db93 | bellard | } |
260 | d3e9db93 | bellard | } |
261 | d3e9db93 | bellard | if (d >= 0) { |
262 | d3e9db93 | bellard | apic_iter = local_apics[d]; |
263 | d3e9db93 | bellard | if (apic_iter) {
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264 | d3e9db93 | bellard | apic_set_irq(apic_iter, vector_num, trigger_mode); |
265 | d3e9db93 | bellard | } |
266 | d3e9db93 | bellard | } |
267 | 8dd69b8f | bellard | } |
268 | d3e9db93 | bellard | return;
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269 | 8dd69b8f | bellard | |
270 | d592d303 | bellard | case APIC_DM_FIXED:
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271 | d592d303 | bellard | break;
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272 | d592d303 | bellard | |
273 | d592d303 | bellard | case APIC_DM_SMI:
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274 | e2eb9d3e | aurel32 | foreach_apic(apic_iter, deliver_bitmask, |
275 | e2eb9d3e | aurel32 | cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_SMI) ); |
276 | e2eb9d3e | aurel32 | return;
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277 | e2eb9d3e | aurel32 | |
278 | d592d303 | bellard | case APIC_DM_NMI:
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279 | e2eb9d3e | aurel32 | foreach_apic(apic_iter, deliver_bitmask, |
280 | e2eb9d3e | aurel32 | cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_NMI) ); |
281 | e2eb9d3e | aurel32 | return;
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282 | d592d303 | bellard | |
283 | d592d303 | bellard | case APIC_DM_INIT:
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284 | d592d303 | bellard | /* normal INIT IPI sent to processors */
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285 | 5fafdf24 | ths | foreach_apic(apic_iter, deliver_bitmask, |
286 | b09ea7d5 | Gleb Natapov | cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_INIT) ); |
287 | d592d303 | bellard | return;
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288 | 3b46e624 | ths | |
289 | d592d303 | bellard | case APIC_DM_EXTINT:
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290 | b1fc0348 | bellard | /* handled in I/O APIC code */
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291 | d592d303 | bellard | break;
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292 | d592d303 | bellard | |
293 | d592d303 | bellard | default:
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294 | d592d303 | bellard | return;
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295 | d592d303 | bellard | } |
296 | d592d303 | bellard | |
297 | 5fafdf24 | ths | foreach_apic(apic_iter, deliver_bitmask, |
298 | d3e9db93 | bellard | apic_set_irq(apic_iter, vector_num, trigger_mode) ); |
299 | d592d303 | bellard | } |
300 | 574bbf7b | bellard | |
301 | 610626af | aliguori | void apic_deliver_irq(uint8_t dest, uint8_t dest_mode,
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302 | 610626af | aliguori | uint8_t delivery_mode, uint8_t vector_num, |
303 | 610626af | aliguori | uint8_t polarity, uint8_t trigger_mode) |
304 | 610626af | aliguori | { |
305 | 610626af | aliguori | uint32_t deliver_bitmask[MAX_APIC_WORDS]; |
306 | 610626af | aliguori | |
307 | 0a3c5921 | Blue Swirl | DPRINTF("%s: dest %d dest_mode %d delivery_mode %d vector %d"
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308 | 0a3c5921 | Blue Swirl | " polarity %d trigger_mode %d\n", __func__, dest, dest_mode,
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309 | 0a3c5921 | Blue Swirl | delivery_mode, vector_num, polarity, trigger_mode); |
310 | 610626af | aliguori | apic_get_delivery_bitmask(deliver_bitmask, dest, dest_mode); |
311 | 610626af | aliguori | apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, polarity, |
312 | 610626af | aliguori | trigger_mode); |
313 | 610626af | aliguori | } |
314 | 610626af | aliguori | |
315 | 574bbf7b | bellard | void cpu_set_apic_base(CPUState *env, uint64_t val)
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316 | 574bbf7b | bellard | { |
317 | 574bbf7b | bellard | APICState *s = env->apic_state; |
318 | 0a3c5921 | Blue Swirl | |
319 | 0a3c5921 | Blue Swirl | DPRINTF("cpu_set_apic_base: %016" PRIx64 "\n", val); |
320 | 2c7c13d4 | aurel32 | if (!s)
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321 | 2c7c13d4 | aurel32 | return;
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322 | 5fafdf24 | ths | s->apicbase = (val & 0xfffff000) |
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323 | 574bbf7b | bellard | (s->apicbase & (MSR_IA32_APICBASE_BSP | MSR_IA32_APICBASE_ENABLE)); |
324 | 574bbf7b | bellard | /* if disabled, cannot be enabled again */
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325 | 574bbf7b | bellard | if (!(val & MSR_IA32_APICBASE_ENABLE)) {
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326 | 574bbf7b | bellard | s->apicbase &= ~MSR_IA32_APICBASE_ENABLE; |
327 | 574bbf7b | bellard | env->cpuid_features &= ~CPUID_APIC; |
328 | 574bbf7b | bellard | s->spurious_vec &= ~APIC_SV_ENABLE; |
329 | 574bbf7b | bellard | } |
330 | 574bbf7b | bellard | } |
331 | 574bbf7b | bellard | |
332 | 574bbf7b | bellard | uint64_t cpu_get_apic_base(CPUState *env) |
333 | 574bbf7b | bellard | { |
334 | 574bbf7b | bellard | APICState *s = env->apic_state; |
335 | 0a3c5921 | Blue Swirl | |
336 | 0a3c5921 | Blue Swirl | DPRINTF("cpu_get_apic_base: %016" PRIx64 "\n", |
337 | 0a3c5921 | Blue Swirl | s ? (uint64_t)s->apicbase: 0);
|
338 | 2c7c13d4 | aurel32 | return s ? s->apicbase : 0; |
339 | 574bbf7b | bellard | } |
340 | 574bbf7b | bellard | |
341 | 9230e66e | bellard | void cpu_set_apic_tpr(CPUX86State *env, uint8_t val)
|
342 | 9230e66e | bellard | { |
343 | 9230e66e | bellard | APICState *s = env->apic_state; |
344 | 2c7c13d4 | aurel32 | if (!s)
|
345 | 2c7c13d4 | aurel32 | return;
|
346 | 9230e66e | bellard | s->tpr = (val & 0x0f) << 4; |
347 | d592d303 | bellard | apic_update_irq(s); |
348 | 9230e66e | bellard | } |
349 | 9230e66e | bellard | |
350 | 9230e66e | bellard | uint8_t cpu_get_apic_tpr(CPUX86State *env) |
351 | 9230e66e | bellard | { |
352 | 9230e66e | bellard | APICState *s = env->apic_state; |
353 | 2c7c13d4 | aurel32 | return s ? s->tpr >> 4 : 0; |
354 | 9230e66e | bellard | } |
355 | 9230e66e | bellard | |
356 | d592d303 | bellard | /* return -1 if no bit is set */
|
357 | d592d303 | bellard | static int get_highest_priority_int(uint32_t *tab) |
358 | d592d303 | bellard | { |
359 | d592d303 | bellard | int i;
|
360 | d592d303 | bellard | for(i = 7; i >= 0; i--) { |
361 | d592d303 | bellard | if (tab[i] != 0) { |
362 | 3b63c04e | aurel32 | return i * 32 + fls_bit(tab[i]); |
363 | d592d303 | bellard | } |
364 | d592d303 | bellard | } |
365 | d592d303 | bellard | return -1; |
366 | d592d303 | bellard | } |
367 | d592d303 | bellard | |
368 | 574bbf7b | bellard | static int apic_get_ppr(APICState *s) |
369 | 574bbf7b | bellard | { |
370 | 574bbf7b | bellard | int tpr, isrv, ppr;
|
371 | 574bbf7b | bellard | |
372 | 574bbf7b | bellard | tpr = (s->tpr >> 4);
|
373 | 574bbf7b | bellard | isrv = get_highest_priority_int(s->isr); |
374 | 574bbf7b | bellard | if (isrv < 0) |
375 | 574bbf7b | bellard | isrv = 0;
|
376 | 574bbf7b | bellard | isrv >>= 4;
|
377 | 574bbf7b | bellard | if (tpr >= isrv)
|
378 | 574bbf7b | bellard | ppr = s->tpr; |
379 | 574bbf7b | bellard | else
|
380 | 574bbf7b | bellard | ppr = isrv << 4;
|
381 | 574bbf7b | bellard | return ppr;
|
382 | 574bbf7b | bellard | } |
383 | 574bbf7b | bellard | |
384 | d592d303 | bellard | static int apic_get_arb_pri(APICState *s) |
385 | d592d303 | bellard | { |
386 | d592d303 | bellard | /* XXX: arbitration */
|
387 | d592d303 | bellard | return 0; |
388 | d592d303 | bellard | } |
389 | d592d303 | bellard | |
390 | 574bbf7b | bellard | /* signal the CPU if an irq is pending */
|
391 | 574bbf7b | bellard | static void apic_update_irq(APICState *s) |
392 | 574bbf7b | bellard | { |
393 | d592d303 | bellard | int irrv, ppr;
|
394 | d592d303 | bellard | if (!(s->spurious_vec & APIC_SV_ENABLE))
|
395 | d592d303 | bellard | return;
|
396 | 574bbf7b | bellard | irrv = get_highest_priority_int(s->irr); |
397 | 574bbf7b | bellard | if (irrv < 0) |
398 | 574bbf7b | bellard | return;
|
399 | d592d303 | bellard | ppr = apic_get_ppr(s); |
400 | d592d303 | bellard | if (ppr && (irrv & 0xf0) <= (ppr & 0xf0)) |
401 | 574bbf7b | bellard | return;
|
402 | 574bbf7b | bellard | cpu_interrupt(s->cpu_env, CPU_INTERRUPT_HARD); |
403 | 574bbf7b | bellard | } |
404 | 574bbf7b | bellard | |
405 | 73822ec8 | aliguori | void apic_reset_irq_delivered(void) |
406 | 73822ec8 | aliguori | { |
407 | 0a3c5921 | Blue Swirl | DPRINTF_C("%s: old coalescing %d\n", __func__, apic_irq_delivered);
|
408 | 73822ec8 | aliguori | apic_irq_delivered = 0;
|
409 | 73822ec8 | aliguori | } |
410 | 73822ec8 | aliguori | |
411 | 73822ec8 | aliguori | int apic_get_irq_delivered(void) |
412 | 73822ec8 | aliguori | { |
413 | 0a3c5921 | Blue Swirl | DPRINTF_C("%s: returning coalescing %d\n", __func__, apic_irq_delivered);
|
414 | 73822ec8 | aliguori | return apic_irq_delivered;
|
415 | 73822ec8 | aliguori | } |
416 | 73822ec8 | aliguori | |
417 | 574bbf7b | bellard | static void apic_set_irq(APICState *s, int vector_num, int trigger_mode) |
418 | 574bbf7b | bellard | { |
419 | 73822ec8 | aliguori | apic_irq_delivered += !get_bit(s->irr, vector_num); |
420 | 0a3c5921 | Blue Swirl | DPRINTF_C("%s: coalescing %d\n", __func__, apic_irq_delivered);
|
421 | 73822ec8 | aliguori | |
422 | 574bbf7b | bellard | set_bit(s->irr, vector_num); |
423 | 574bbf7b | bellard | if (trigger_mode)
|
424 | 574bbf7b | bellard | set_bit(s->tmr, vector_num); |
425 | 574bbf7b | bellard | else
|
426 | 574bbf7b | bellard | reset_bit(s->tmr, vector_num); |
427 | 574bbf7b | bellard | apic_update_irq(s); |
428 | 574bbf7b | bellard | } |
429 | 574bbf7b | bellard | |
430 | 574bbf7b | bellard | static void apic_eoi(APICState *s) |
431 | 574bbf7b | bellard | { |
432 | 574bbf7b | bellard | int isrv;
|
433 | 574bbf7b | bellard | isrv = get_highest_priority_int(s->isr); |
434 | 574bbf7b | bellard | if (isrv < 0) |
435 | 574bbf7b | bellard | return;
|
436 | 574bbf7b | bellard | reset_bit(s->isr, isrv); |
437 | d592d303 | bellard | /* XXX: send the EOI packet to the APIC bus to allow the I/O APIC to
|
438 | d592d303 | bellard | set the remote IRR bit for level triggered interrupts. */
|
439 | 574bbf7b | bellard | apic_update_irq(s); |
440 | 574bbf7b | bellard | } |
441 | 574bbf7b | bellard | |
442 | 678e12cc | Gleb Natapov | static int apic_find_dest(uint8_t dest) |
443 | 678e12cc | Gleb Natapov | { |
444 | 678e12cc | Gleb Natapov | APICState *apic = local_apics[dest]; |
445 | 678e12cc | Gleb Natapov | int i;
|
446 | 678e12cc | Gleb Natapov | |
447 | 678e12cc | Gleb Natapov | if (apic && apic->id == dest)
|
448 | 678e12cc | Gleb Natapov | return dest; /* shortcut in case apic->id == apic->idx */ |
449 | 678e12cc | Gleb Natapov | |
450 | 678e12cc | Gleb Natapov | for (i = 0; i < MAX_APICS; i++) { |
451 | 678e12cc | Gleb Natapov | apic = local_apics[i]; |
452 | 678e12cc | Gleb Natapov | if (apic && apic->id == dest)
|
453 | 678e12cc | Gleb Natapov | return i;
|
454 | 678e12cc | Gleb Natapov | } |
455 | 678e12cc | Gleb Natapov | |
456 | 678e12cc | Gleb Natapov | return -1; |
457 | 678e12cc | Gleb Natapov | } |
458 | 678e12cc | Gleb Natapov | |
459 | d3e9db93 | bellard | static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask, |
460 | d3e9db93 | bellard | uint8_t dest, uint8_t dest_mode) |
461 | d592d303 | bellard | { |
462 | d592d303 | bellard | APICState *apic_iter; |
463 | d3e9db93 | bellard | int i;
|
464 | d592d303 | bellard | |
465 | d592d303 | bellard | if (dest_mode == 0) { |
466 | d3e9db93 | bellard | if (dest == 0xff) { |
467 | d3e9db93 | bellard | memset(deliver_bitmask, 0xff, MAX_APIC_WORDS * sizeof(uint32_t)); |
468 | d3e9db93 | bellard | } else {
|
469 | 678e12cc | Gleb Natapov | int idx = apic_find_dest(dest);
|
470 | d3e9db93 | bellard | memset(deliver_bitmask, 0x00, MAX_APIC_WORDS * sizeof(uint32_t)); |
471 | 678e12cc | Gleb Natapov | if (idx >= 0) |
472 | 678e12cc | Gleb Natapov | set_bit(deliver_bitmask, idx); |
473 | d3e9db93 | bellard | } |
474 | d592d303 | bellard | } else {
|
475 | d592d303 | bellard | /* XXX: cluster mode */
|
476 | d3e9db93 | bellard | memset(deliver_bitmask, 0x00, MAX_APIC_WORDS * sizeof(uint32_t)); |
477 | d3e9db93 | bellard | for(i = 0; i < MAX_APICS; i++) { |
478 | d3e9db93 | bellard | apic_iter = local_apics[i]; |
479 | d3e9db93 | bellard | if (apic_iter) {
|
480 | d3e9db93 | bellard | if (apic_iter->dest_mode == 0xf) { |
481 | d3e9db93 | bellard | if (dest & apic_iter->log_dest)
|
482 | d3e9db93 | bellard | set_bit(deliver_bitmask, i); |
483 | d3e9db93 | bellard | } else if (apic_iter->dest_mode == 0x0) { |
484 | d3e9db93 | bellard | if ((dest & 0xf0) == (apic_iter->log_dest & 0xf0) && |
485 | d3e9db93 | bellard | (dest & apic_iter->log_dest & 0x0f)) {
|
486 | d3e9db93 | bellard | set_bit(deliver_bitmask, i); |
487 | d3e9db93 | bellard | } |
488 | d3e9db93 | bellard | } |
489 | d3e9db93 | bellard | } |
490 | d592d303 | bellard | } |
491 | d592d303 | bellard | } |
492 | d592d303 | bellard | } |
493 | d592d303 | bellard | |
494 | d592d303 | bellard | |
495 | b09ea7d5 | Gleb Natapov | void apic_init_reset(CPUState *env)
|
496 | d592d303 | bellard | { |
497 | b09ea7d5 | Gleb Natapov | APICState *s = env->apic_state; |
498 | d592d303 | bellard | int i;
|
499 | d592d303 | bellard | |
500 | b09ea7d5 | Gleb Natapov | if (!s)
|
501 | b09ea7d5 | Gleb Natapov | return;
|
502 | b09ea7d5 | Gleb Natapov | |
503 | d592d303 | bellard | s->tpr = 0;
|
504 | d592d303 | bellard | s->spurious_vec = 0xff;
|
505 | d592d303 | bellard | s->log_dest = 0;
|
506 | e0fd8781 | bellard | s->dest_mode = 0xf;
|
507 | d592d303 | bellard | memset(s->isr, 0, sizeof(s->isr)); |
508 | d592d303 | bellard | memset(s->tmr, 0, sizeof(s->tmr)); |
509 | d592d303 | bellard | memset(s->irr, 0, sizeof(s->irr)); |
510 | b4511723 | bellard | for(i = 0; i < APIC_LVT_NB; i++) |
511 | b4511723 | bellard | s->lvt[i] = 1 << 16; /* mask LVT */ |
512 | d592d303 | bellard | s->esr = 0;
|
513 | d592d303 | bellard | memset(s->icr, 0, sizeof(s->icr)); |
514 | d592d303 | bellard | s->divide_conf = 0;
|
515 | d592d303 | bellard | s->count_shift = 0;
|
516 | d592d303 | bellard | s->initial_count = 0;
|
517 | d592d303 | bellard | s->initial_count_load_time = 0;
|
518 | d592d303 | bellard | s->next_time = 0;
|
519 | b09ea7d5 | Gleb Natapov | s->wait_for_sipi = 1;
|
520 | 3003b8bb | aurel32 | |
521 | b09ea7d5 | Gleb Natapov | env->halted = !(s->apicbase & MSR_IA32_APICBASE_BSP); |
522 | d592d303 | bellard | } |
523 | d592d303 | bellard | |
524 | e0fd8781 | bellard | static void apic_startup(APICState *s, int vector_num) |
525 | e0fd8781 | bellard | { |
526 | b09ea7d5 | Gleb Natapov | s->sipi_vector = vector_num; |
527 | b09ea7d5 | Gleb Natapov | cpu_interrupt(s->cpu_env, CPU_INTERRUPT_SIPI); |
528 | b09ea7d5 | Gleb Natapov | } |
529 | b09ea7d5 | Gleb Natapov | |
530 | b09ea7d5 | Gleb Natapov | void apic_sipi(CPUState *env)
|
531 | b09ea7d5 | Gleb Natapov | { |
532 | b09ea7d5 | Gleb Natapov | APICState *s = env->apic_state; |
533 | b09ea7d5 | Gleb Natapov | |
534 | b09ea7d5 | Gleb Natapov | cpu_reset_interrupt(env, CPU_INTERRUPT_SIPI); |
535 | b09ea7d5 | Gleb Natapov | |
536 | b09ea7d5 | Gleb Natapov | if (!s->wait_for_sipi)
|
537 | e0fd8781 | bellard | return;
|
538 | b09ea7d5 | Gleb Natapov | |
539 | e0fd8781 | bellard | env->eip = 0;
|
540 | b09ea7d5 | Gleb Natapov | cpu_x86_load_seg_cache(env, R_CS, s->sipi_vector << 8, s->sipi_vector << 12, |
541 | 19a2223f | Gleb Natapov | env->segs[R_CS].limit, env->segs[R_CS].flags); |
542 | ce5232c5 | bellard | env->halted = 0;
|
543 | b09ea7d5 | Gleb Natapov | s->wait_for_sipi = 0;
|
544 | e0fd8781 | bellard | } |
545 | e0fd8781 | bellard | |
546 | d592d303 | bellard | static void apic_deliver(APICState *s, uint8_t dest, uint8_t dest_mode, |
547 | d592d303 | bellard | uint8_t delivery_mode, uint8_t vector_num, |
548 | d592d303 | bellard | uint8_t polarity, uint8_t trigger_mode) |
549 | d592d303 | bellard | { |
550 | d3e9db93 | bellard | uint32_t deliver_bitmask[MAX_APIC_WORDS]; |
551 | d592d303 | bellard | int dest_shorthand = (s->icr[0] >> 18) & 3; |
552 | d592d303 | bellard | APICState *apic_iter; |
553 | d592d303 | bellard | |
554 | e0fd8781 | bellard | switch (dest_shorthand) {
|
555 | d3e9db93 | bellard | case 0: |
556 | d3e9db93 | bellard | apic_get_delivery_bitmask(deliver_bitmask, dest, dest_mode); |
557 | d3e9db93 | bellard | break;
|
558 | d3e9db93 | bellard | case 1: |
559 | d3e9db93 | bellard | memset(deliver_bitmask, 0x00, sizeof(deliver_bitmask)); |
560 | 678e12cc | Gleb Natapov | set_bit(deliver_bitmask, s->idx); |
561 | d3e9db93 | bellard | break;
|
562 | d3e9db93 | bellard | case 2: |
563 | d3e9db93 | bellard | memset(deliver_bitmask, 0xff, sizeof(deliver_bitmask)); |
564 | d3e9db93 | bellard | break;
|
565 | d3e9db93 | bellard | case 3: |
566 | d3e9db93 | bellard | memset(deliver_bitmask, 0xff, sizeof(deliver_bitmask)); |
567 | 678e12cc | Gleb Natapov | reset_bit(deliver_bitmask, s->idx); |
568 | d3e9db93 | bellard | break;
|
569 | e0fd8781 | bellard | } |
570 | e0fd8781 | bellard | |
571 | d592d303 | bellard | switch (delivery_mode) {
|
572 | d592d303 | bellard | case APIC_DM_INIT:
|
573 | d592d303 | bellard | { |
574 | d592d303 | bellard | int trig_mode = (s->icr[0] >> 15) & 1; |
575 | d592d303 | bellard | int level = (s->icr[0] >> 14) & 1; |
576 | d592d303 | bellard | if (level == 0 && trig_mode == 1) { |
577 | 5fafdf24 | ths | foreach_apic(apic_iter, deliver_bitmask, |
578 | d3e9db93 | bellard | apic_iter->arb_id = apic_iter->id ); |
579 | d592d303 | bellard | return;
|
580 | d592d303 | bellard | } |
581 | d592d303 | bellard | } |
582 | d592d303 | bellard | break;
|
583 | d592d303 | bellard | |
584 | d592d303 | bellard | case APIC_DM_SIPI:
|
585 | 5fafdf24 | ths | foreach_apic(apic_iter, deliver_bitmask, |
586 | d3e9db93 | bellard | apic_startup(apic_iter, vector_num) ); |
587 | d592d303 | bellard | return;
|
588 | d592d303 | bellard | } |
589 | d592d303 | bellard | |
590 | d592d303 | bellard | apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, polarity, |
591 | d592d303 | bellard | trigger_mode); |
592 | d592d303 | bellard | } |
593 | d592d303 | bellard | |
594 | 574bbf7b | bellard | int apic_get_interrupt(CPUState *env)
|
595 | 574bbf7b | bellard | { |
596 | 574bbf7b | bellard | APICState *s = env->apic_state; |
597 | 574bbf7b | bellard | int intno;
|
598 | 574bbf7b | bellard | |
599 | 574bbf7b | bellard | /* if the APIC is installed or enabled, we let the 8259 handle the
|
600 | 574bbf7b | bellard | IRQs */
|
601 | 574bbf7b | bellard | if (!s)
|
602 | 574bbf7b | bellard | return -1; |
603 | 574bbf7b | bellard | if (!(s->spurious_vec & APIC_SV_ENABLE))
|
604 | 574bbf7b | bellard | return -1; |
605 | 3b46e624 | ths | |
606 | 574bbf7b | bellard | /* XXX: spurious IRQ handling */
|
607 | 574bbf7b | bellard | intno = get_highest_priority_int(s->irr); |
608 | 574bbf7b | bellard | if (intno < 0) |
609 | 574bbf7b | bellard | return -1; |
610 | d592d303 | bellard | if (s->tpr && intno <= s->tpr)
|
611 | d592d303 | bellard | return s->spurious_vec & 0xff; |
612 | b4511723 | bellard | reset_bit(s->irr, intno); |
613 | 574bbf7b | bellard | set_bit(s->isr, intno); |
614 | 574bbf7b | bellard | apic_update_irq(s); |
615 | 574bbf7b | bellard | return intno;
|
616 | 574bbf7b | bellard | } |
617 | 574bbf7b | bellard | |
618 | 0e21e12b | ths | int apic_accept_pic_intr(CPUState *env)
|
619 | 0e21e12b | ths | { |
620 | 0e21e12b | ths | APICState *s = env->apic_state; |
621 | 0e21e12b | ths | uint32_t lvt0; |
622 | 0e21e12b | ths | |
623 | 0e21e12b | ths | if (!s)
|
624 | 0e21e12b | ths | return -1; |
625 | 0e21e12b | ths | |
626 | 0e21e12b | ths | lvt0 = s->lvt[APIC_LVT_LINT0]; |
627 | 0e21e12b | ths | |
628 | a5b38b51 | aurel32 | if ((s->apicbase & MSR_IA32_APICBASE_ENABLE) == 0 || |
629 | a5b38b51 | aurel32 | (lvt0 & APIC_LVT_MASKED) == 0)
|
630 | 0e21e12b | ths | return 1; |
631 | 0e21e12b | ths | |
632 | 0e21e12b | ths | return 0; |
633 | 0e21e12b | ths | } |
634 | 0e21e12b | ths | |
635 | 574bbf7b | bellard | static uint32_t apic_get_current_count(APICState *s)
|
636 | 574bbf7b | bellard | { |
637 | 574bbf7b | bellard | int64_t d; |
638 | 574bbf7b | bellard | uint32_t val; |
639 | 5fafdf24 | ths | d = (qemu_get_clock(vm_clock) - s->initial_count_load_time) >> |
640 | 574bbf7b | bellard | s->count_shift; |
641 | 574bbf7b | bellard | if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
|
642 | 574bbf7b | bellard | /* periodic */
|
643 | d592d303 | bellard | val = s->initial_count - (d % ((uint64_t)s->initial_count + 1));
|
644 | 574bbf7b | bellard | } else {
|
645 | 574bbf7b | bellard | if (d >= s->initial_count)
|
646 | 574bbf7b | bellard | val = 0;
|
647 | 574bbf7b | bellard | else
|
648 | 574bbf7b | bellard | val = s->initial_count - d; |
649 | 574bbf7b | bellard | } |
650 | 574bbf7b | bellard | return val;
|
651 | 574bbf7b | bellard | } |
652 | 574bbf7b | bellard | |
653 | 574bbf7b | bellard | static void apic_timer_update(APICState *s, int64_t current_time) |
654 | 574bbf7b | bellard | { |
655 | 574bbf7b | bellard | int64_t next_time, d; |
656 | 3b46e624 | ths | |
657 | 574bbf7b | bellard | if (!(s->lvt[APIC_LVT_TIMER] & APIC_LVT_MASKED)) {
|
658 | 5fafdf24 | ths | d = (current_time - s->initial_count_load_time) >> |
659 | 574bbf7b | bellard | s->count_shift; |
660 | 574bbf7b | bellard | if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
|
661 | 681f8c29 | aliguori | if (!s->initial_count)
|
662 | 681f8c29 | aliguori | goto no_timer;
|
663 | d592d303 | bellard | d = ((d / ((uint64_t)s->initial_count + 1)) + 1) * ((uint64_t)s->initial_count + 1); |
664 | 574bbf7b | bellard | } else {
|
665 | 574bbf7b | bellard | if (d >= s->initial_count)
|
666 | 574bbf7b | bellard | goto no_timer;
|
667 | d592d303 | bellard | d = (uint64_t)s->initial_count + 1;
|
668 | 574bbf7b | bellard | } |
669 | 574bbf7b | bellard | next_time = s->initial_count_load_time + (d << s->count_shift); |
670 | 574bbf7b | bellard | qemu_mod_timer(s->timer, next_time); |
671 | 574bbf7b | bellard | s->next_time = next_time; |
672 | 574bbf7b | bellard | } else {
|
673 | 574bbf7b | bellard | no_timer:
|
674 | 574bbf7b | bellard | qemu_del_timer(s->timer); |
675 | 574bbf7b | bellard | } |
676 | 574bbf7b | bellard | } |
677 | 574bbf7b | bellard | |
678 | 574bbf7b | bellard | static void apic_timer(void *opaque) |
679 | 574bbf7b | bellard | { |
680 | 574bbf7b | bellard | APICState *s = opaque; |
681 | 574bbf7b | bellard | |
682 | a5b38b51 | aurel32 | apic_local_deliver(s->cpu_env, APIC_LVT_TIMER); |
683 | 574bbf7b | bellard | apic_timer_update(s, s->next_time); |
684 | 574bbf7b | bellard | } |
685 | 574bbf7b | bellard | |
686 | c227f099 | Anthony Liguori | static uint32_t apic_mem_readb(void *opaque, target_phys_addr_t addr) |
687 | 574bbf7b | bellard | { |
688 | 574bbf7b | bellard | return 0; |
689 | 574bbf7b | bellard | } |
690 | 574bbf7b | bellard | |
691 | c227f099 | Anthony Liguori | static uint32_t apic_mem_readw(void *opaque, target_phys_addr_t addr) |
692 | 574bbf7b | bellard | { |
693 | 574bbf7b | bellard | return 0; |
694 | 574bbf7b | bellard | } |
695 | 574bbf7b | bellard | |
696 | c227f099 | Anthony Liguori | static void apic_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) |
697 | 574bbf7b | bellard | { |
698 | 574bbf7b | bellard | } |
699 | 574bbf7b | bellard | |
700 | c227f099 | Anthony Liguori | static void apic_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val) |
701 | 574bbf7b | bellard | { |
702 | 574bbf7b | bellard | } |
703 | 574bbf7b | bellard | |
704 | c227f099 | Anthony Liguori | static uint32_t apic_mem_readl(void *opaque, target_phys_addr_t addr) |
705 | 574bbf7b | bellard | { |
706 | 574bbf7b | bellard | CPUState *env; |
707 | 574bbf7b | bellard | APICState *s; |
708 | 574bbf7b | bellard | uint32_t val; |
709 | 574bbf7b | bellard | int index;
|
710 | 574bbf7b | bellard | |
711 | 574bbf7b | bellard | env = cpu_single_env; |
712 | 574bbf7b | bellard | if (!env)
|
713 | 574bbf7b | bellard | return 0; |
714 | 574bbf7b | bellard | s = env->apic_state; |
715 | 574bbf7b | bellard | |
716 | 574bbf7b | bellard | index = (addr >> 4) & 0xff; |
717 | 574bbf7b | bellard | switch(index) {
|
718 | 574bbf7b | bellard | case 0x02: /* id */ |
719 | 574bbf7b | bellard | val = s->id << 24;
|
720 | 574bbf7b | bellard | break;
|
721 | 574bbf7b | bellard | case 0x03: /* version */ |
722 | 574bbf7b | bellard | val = 0x11 | ((APIC_LVT_NB - 1) << 16); /* version 0x11 */ |
723 | 574bbf7b | bellard | break;
|
724 | 574bbf7b | bellard | case 0x08: |
725 | 574bbf7b | bellard | val = s->tpr; |
726 | 574bbf7b | bellard | break;
|
727 | d592d303 | bellard | case 0x09: |
728 | d592d303 | bellard | val = apic_get_arb_pri(s); |
729 | d592d303 | bellard | break;
|
730 | 574bbf7b | bellard | case 0x0a: |
731 | 574bbf7b | bellard | /* ppr */
|
732 | 574bbf7b | bellard | val = apic_get_ppr(s); |
733 | 574bbf7b | bellard | break;
|
734 | b237db36 | aurel32 | case 0x0b: |
735 | b237db36 | aurel32 | val = 0;
|
736 | b237db36 | aurel32 | break;
|
737 | d592d303 | bellard | case 0x0d: |
738 | d592d303 | bellard | val = s->log_dest << 24;
|
739 | d592d303 | bellard | break;
|
740 | d592d303 | bellard | case 0x0e: |
741 | d592d303 | bellard | val = s->dest_mode << 28;
|
742 | d592d303 | bellard | break;
|
743 | 574bbf7b | bellard | case 0x0f: |
744 | 574bbf7b | bellard | val = s->spurious_vec; |
745 | 574bbf7b | bellard | break;
|
746 | 574bbf7b | bellard | case 0x10 ... 0x17: |
747 | 574bbf7b | bellard | val = s->isr[index & 7];
|
748 | 574bbf7b | bellard | break;
|
749 | 574bbf7b | bellard | case 0x18 ... 0x1f: |
750 | 574bbf7b | bellard | val = s->tmr[index & 7];
|
751 | 574bbf7b | bellard | break;
|
752 | 574bbf7b | bellard | case 0x20 ... 0x27: |
753 | 574bbf7b | bellard | val = s->irr[index & 7];
|
754 | 574bbf7b | bellard | break;
|
755 | 574bbf7b | bellard | case 0x28: |
756 | 574bbf7b | bellard | val = s->esr; |
757 | 574bbf7b | bellard | break;
|
758 | 574bbf7b | bellard | case 0x30: |
759 | 574bbf7b | bellard | case 0x31: |
760 | 574bbf7b | bellard | val = s->icr[index & 1];
|
761 | 574bbf7b | bellard | break;
|
762 | e0fd8781 | bellard | case 0x32 ... 0x37: |
763 | e0fd8781 | bellard | val = s->lvt[index - 0x32];
|
764 | e0fd8781 | bellard | break;
|
765 | 574bbf7b | bellard | case 0x38: |
766 | 574bbf7b | bellard | val = s->initial_count; |
767 | 574bbf7b | bellard | break;
|
768 | 574bbf7b | bellard | case 0x39: |
769 | 574bbf7b | bellard | val = apic_get_current_count(s); |
770 | 574bbf7b | bellard | break;
|
771 | 574bbf7b | bellard | case 0x3e: |
772 | 574bbf7b | bellard | val = s->divide_conf; |
773 | 574bbf7b | bellard | break;
|
774 | 574bbf7b | bellard | default:
|
775 | 574bbf7b | bellard | s->esr |= ESR_ILLEGAL_ADDRESS; |
776 | 574bbf7b | bellard | val = 0;
|
777 | 574bbf7b | bellard | break;
|
778 | 574bbf7b | bellard | } |
779 | 0a3c5921 | Blue Swirl | DPRINTF("read: " TARGET_FMT_plx " = %08x\n", addr, val); |
780 | 574bbf7b | bellard | return val;
|
781 | 574bbf7b | bellard | } |
782 | 574bbf7b | bellard | |
783 | c227f099 | Anthony Liguori | static void apic_send_msi(target_phys_addr_t addr, uint32 data) |
784 | 54c96da7 | Michael S. Tsirkin | { |
785 | 54c96da7 | Michael S. Tsirkin | uint8_t dest = (addr & MSI_ADDR_DEST_ID_MASK) >> MSI_ADDR_DEST_ID_SHIFT; |
786 | 54c96da7 | Michael S. Tsirkin | uint8_t vector = (data & MSI_DATA_VECTOR_MASK) >> MSI_DATA_VECTOR_SHIFT; |
787 | 54c96da7 | Michael S. Tsirkin | uint8_t dest_mode = (addr >> MSI_ADDR_DEST_MODE_SHIFT) & 0x1;
|
788 | 54c96da7 | Michael S. Tsirkin | uint8_t trigger_mode = (data >> MSI_DATA_TRIGGER_SHIFT) & 0x1;
|
789 | 54c96da7 | Michael S. Tsirkin | uint8_t delivery = (data >> MSI_DATA_DELIVERY_MODE_SHIFT) & 0x7;
|
790 | 54c96da7 | Michael S. Tsirkin | /* XXX: Ignore redirection hint. */
|
791 | 54c96da7 | Michael S. Tsirkin | apic_deliver_irq(dest, dest_mode, delivery, vector, 0, trigger_mode);
|
792 | 54c96da7 | Michael S. Tsirkin | } |
793 | 54c96da7 | Michael S. Tsirkin | |
794 | c227f099 | Anthony Liguori | static void apic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val) |
795 | 574bbf7b | bellard | { |
796 | 574bbf7b | bellard | CPUState *env; |
797 | 574bbf7b | bellard | APICState *s; |
798 | 54c96da7 | Michael S. Tsirkin | int index = (addr >> 4) & 0xff; |
799 | 54c96da7 | Michael S. Tsirkin | if (addr > 0xfff || !index) { |
800 | 54c96da7 | Michael S. Tsirkin | /* MSI and MMIO APIC are at the same memory location,
|
801 | 54c96da7 | Michael S. Tsirkin | * but actually not on the global bus: MSI is on PCI bus
|
802 | 54c96da7 | Michael S. Tsirkin | * APIC is connected directly to the CPU.
|
803 | 54c96da7 | Michael S. Tsirkin | * Mapping them on the global bus happens to work because
|
804 | 54c96da7 | Michael S. Tsirkin | * MSI registers are reserved in APIC MMIO and vice versa. */
|
805 | 54c96da7 | Michael S. Tsirkin | apic_send_msi(addr, val); |
806 | 54c96da7 | Michael S. Tsirkin | return;
|
807 | 54c96da7 | Michael S. Tsirkin | } |
808 | 574bbf7b | bellard | |
809 | 574bbf7b | bellard | env = cpu_single_env; |
810 | 574bbf7b | bellard | if (!env)
|
811 | 574bbf7b | bellard | return;
|
812 | 574bbf7b | bellard | s = env->apic_state; |
813 | 574bbf7b | bellard | |
814 | 0a3c5921 | Blue Swirl | DPRINTF("write: " TARGET_FMT_plx " = %08x\n", addr, val); |
815 | 574bbf7b | bellard | |
816 | 574bbf7b | bellard | switch(index) {
|
817 | 574bbf7b | bellard | case 0x02: |
818 | 574bbf7b | bellard | s->id = (val >> 24);
|
819 | 574bbf7b | bellard | break;
|
820 | e0fd8781 | bellard | case 0x03: |
821 | e0fd8781 | bellard | break;
|
822 | 574bbf7b | bellard | case 0x08: |
823 | 574bbf7b | bellard | s->tpr = val; |
824 | d592d303 | bellard | apic_update_irq(s); |
825 | 574bbf7b | bellard | break;
|
826 | e0fd8781 | bellard | case 0x09: |
827 | e0fd8781 | bellard | case 0x0a: |
828 | e0fd8781 | bellard | break;
|
829 | 574bbf7b | bellard | case 0x0b: /* EOI */ |
830 | 574bbf7b | bellard | apic_eoi(s); |
831 | 574bbf7b | bellard | break;
|
832 | d592d303 | bellard | case 0x0d: |
833 | d592d303 | bellard | s->log_dest = val >> 24;
|
834 | d592d303 | bellard | break;
|
835 | d592d303 | bellard | case 0x0e: |
836 | d592d303 | bellard | s->dest_mode = val >> 28;
|
837 | d592d303 | bellard | break;
|
838 | 574bbf7b | bellard | case 0x0f: |
839 | 574bbf7b | bellard | s->spurious_vec = val & 0x1ff;
|
840 | d592d303 | bellard | apic_update_irq(s); |
841 | 574bbf7b | bellard | break;
|
842 | e0fd8781 | bellard | case 0x10 ... 0x17: |
843 | e0fd8781 | bellard | case 0x18 ... 0x1f: |
844 | e0fd8781 | bellard | case 0x20 ... 0x27: |
845 | e0fd8781 | bellard | case 0x28: |
846 | e0fd8781 | bellard | break;
|
847 | 574bbf7b | bellard | case 0x30: |
848 | d592d303 | bellard | s->icr[0] = val;
|
849 | d592d303 | bellard | apic_deliver(s, (s->icr[1] >> 24) & 0xff, (s->icr[0] >> 11) & 1, |
850 | d592d303 | bellard | (s->icr[0] >> 8) & 7, (s->icr[0] & 0xff), |
851 | d592d303 | bellard | (s->icr[0] >> 14) & 1, (s->icr[0] >> 15) & 1); |
852 | d592d303 | bellard | break;
|
853 | 574bbf7b | bellard | case 0x31: |
854 | d592d303 | bellard | s->icr[1] = val;
|
855 | 574bbf7b | bellard | break;
|
856 | 574bbf7b | bellard | case 0x32 ... 0x37: |
857 | 574bbf7b | bellard | { |
858 | 574bbf7b | bellard | int n = index - 0x32; |
859 | 574bbf7b | bellard | s->lvt[n] = val; |
860 | 574bbf7b | bellard | if (n == APIC_LVT_TIMER)
|
861 | 574bbf7b | bellard | apic_timer_update(s, qemu_get_clock(vm_clock)); |
862 | 574bbf7b | bellard | } |
863 | 574bbf7b | bellard | break;
|
864 | 574bbf7b | bellard | case 0x38: |
865 | 574bbf7b | bellard | s->initial_count = val; |
866 | 574bbf7b | bellard | s->initial_count_load_time = qemu_get_clock(vm_clock); |
867 | 574bbf7b | bellard | apic_timer_update(s, s->initial_count_load_time); |
868 | 574bbf7b | bellard | break;
|
869 | e0fd8781 | bellard | case 0x39: |
870 | e0fd8781 | bellard | break;
|
871 | 574bbf7b | bellard | case 0x3e: |
872 | 574bbf7b | bellard | { |
873 | 574bbf7b | bellard | int v;
|
874 | 574bbf7b | bellard | s->divide_conf = val & 0xb;
|
875 | 574bbf7b | bellard | v = (s->divide_conf & 3) | ((s->divide_conf >> 1) & 4); |
876 | 574bbf7b | bellard | s->count_shift = (v + 1) & 7; |
877 | 574bbf7b | bellard | } |
878 | 574bbf7b | bellard | break;
|
879 | 574bbf7b | bellard | default:
|
880 | 574bbf7b | bellard | s->esr |= ESR_ILLEGAL_ADDRESS; |
881 | 574bbf7b | bellard | break;
|
882 | 574bbf7b | bellard | } |
883 | 574bbf7b | bellard | } |
884 | 574bbf7b | bellard | |
885 | 695dcf71 | Juan Quintela | /* This function is only used for old state version 1 and 2 */
|
886 | 695dcf71 | Juan Quintela | static int apic_load_old(QEMUFile *f, void *opaque, int version_id) |
887 | d592d303 | bellard | { |
888 | d592d303 | bellard | APICState *s = opaque; |
889 | d592d303 | bellard | int i;
|
890 | d592d303 | bellard | |
891 | e6cf6a8c | bellard | if (version_id > 2) |
892 | d592d303 | bellard | return -EINVAL;
|
893 | d592d303 | bellard | |
894 | d592d303 | bellard | /* XXX: what if the base changes? (registered memory regions) */
|
895 | d592d303 | bellard | qemu_get_be32s(f, &s->apicbase); |
896 | d592d303 | bellard | qemu_get_8s(f, &s->id); |
897 | d592d303 | bellard | qemu_get_8s(f, &s->arb_id); |
898 | d592d303 | bellard | qemu_get_8s(f, &s->tpr); |
899 | d592d303 | bellard | qemu_get_be32s(f, &s->spurious_vec); |
900 | d592d303 | bellard | qemu_get_8s(f, &s->log_dest); |
901 | d592d303 | bellard | qemu_get_8s(f, &s->dest_mode); |
902 | d592d303 | bellard | for (i = 0; i < 8; i++) { |
903 | d592d303 | bellard | qemu_get_be32s(f, &s->isr[i]); |
904 | d592d303 | bellard | qemu_get_be32s(f, &s->tmr[i]); |
905 | d592d303 | bellard | qemu_get_be32s(f, &s->irr[i]); |
906 | d592d303 | bellard | } |
907 | d592d303 | bellard | for (i = 0; i < APIC_LVT_NB; i++) { |
908 | d592d303 | bellard | qemu_get_be32s(f, &s->lvt[i]); |
909 | d592d303 | bellard | } |
910 | d592d303 | bellard | qemu_get_be32s(f, &s->esr); |
911 | d592d303 | bellard | qemu_get_be32s(f, &s->icr[0]);
|
912 | d592d303 | bellard | qemu_get_be32s(f, &s->icr[1]);
|
913 | d592d303 | bellard | qemu_get_be32s(f, &s->divide_conf); |
914 | bee8d684 | ths | s->count_shift=qemu_get_be32(f); |
915 | d592d303 | bellard | qemu_get_be32s(f, &s->initial_count); |
916 | bee8d684 | ths | s->initial_count_load_time=qemu_get_be64(f); |
917 | bee8d684 | ths | s->next_time=qemu_get_be64(f); |
918 | e6cf6a8c | bellard | |
919 | e6cf6a8c | bellard | if (version_id >= 2) |
920 | e6cf6a8c | bellard | qemu_get_timer(f, s->timer); |
921 | d592d303 | bellard | return 0; |
922 | d592d303 | bellard | } |
923 | 574bbf7b | bellard | |
924 | 695dcf71 | Juan Quintela | static const VMStateDescription vmstate_apic = { |
925 | 695dcf71 | Juan Quintela | .name = "apic",
|
926 | 695dcf71 | Juan Quintela | .version_id = 3,
|
927 | 695dcf71 | Juan Quintela | .minimum_version_id = 3,
|
928 | 695dcf71 | Juan Quintela | .minimum_version_id_old = 1,
|
929 | 695dcf71 | Juan Quintela | .load_state_old = apic_load_old, |
930 | 695dcf71 | Juan Quintela | .fields = (VMStateField []) { |
931 | 695dcf71 | Juan Quintela | VMSTATE_UINT32(apicbase, APICState), |
932 | 695dcf71 | Juan Quintela | VMSTATE_UINT8(id, APICState), |
933 | 695dcf71 | Juan Quintela | VMSTATE_UINT8(arb_id, APICState), |
934 | 695dcf71 | Juan Quintela | VMSTATE_UINT8(tpr, APICState), |
935 | 695dcf71 | Juan Quintela | VMSTATE_UINT32(spurious_vec, APICState), |
936 | 695dcf71 | Juan Quintela | VMSTATE_UINT8(log_dest, APICState), |
937 | 695dcf71 | Juan Quintela | VMSTATE_UINT8(dest_mode, APICState), |
938 | 695dcf71 | Juan Quintela | VMSTATE_UINT32_ARRAY(isr, APICState, 8),
|
939 | 695dcf71 | Juan Quintela | VMSTATE_UINT32_ARRAY(tmr, APICState, 8),
|
940 | 695dcf71 | Juan Quintela | VMSTATE_UINT32_ARRAY(irr, APICState, 8),
|
941 | 695dcf71 | Juan Quintela | VMSTATE_UINT32_ARRAY(lvt, APICState, APIC_LVT_NB), |
942 | 695dcf71 | Juan Quintela | VMSTATE_UINT32(esr, APICState), |
943 | 695dcf71 | Juan Quintela | VMSTATE_UINT32_ARRAY(icr, APICState, 2),
|
944 | 695dcf71 | Juan Quintela | VMSTATE_UINT32(divide_conf, APICState), |
945 | 695dcf71 | Juan Quintela | VMSTATE_INT32(count_shift, APICState), |
946 | 695dcf71 | Juan Quintela | VMSTATE_UINT32(initial_count, APICState), |
947 | 695dcf71 | Juan Quintela | VMSTATE_INT64(initial_count_load_time, APICState), |
948 | 695dcf71 | Juan Quintela | VMSTATE_INT64(next_time, APICState), |
949 | 695dcf71 | Juan Quintela | VMSTATE_TIMER(timer, APICState), |
950 | 695dcf71 | Juan Quintela | VMSTATE_END_OF_LIST() |
951 | 695dcf71 | Juan Quintela | } |
952 | 695dcf71 | Juan Quintela | }; |
953 | 695dcf71 | Juan Quintela | |
954 | d592d303 | bellard | static void apic_reset(void *opaque) |
955 | d592d303 | bellard | { |
956 | d592d303 | bellard | APICState *s = opaque; |
957 | 4c0960c0 | Avi Kivity | int bsp;
|
958 | fec5fa02 | aurel32 | |
959 | 4c0960c0 | Avi Kivity | bsp = cpu_is_bsp(s->cpu_env); |
960 | fec5fa02 | aurel32 | s->apicbase = 0xfee00000 |
|
961 | 678e12cc | Gleb Natapov | (bsp ? MSR_IA32_APICBASE_BSP : 0) | MSR_IA32_APICBASE_ENABLE;
|
962 | fec5fa02 | aurel32 | |
963 | b09ea7d5 | Gleb Natapov | cpu_reset(s->cpu_env); |
964 | b09ea7d5 | Gleb Natapov | apic_init_reset(s->cpu_env); |
965 | 0e21e12b | ths | |
966 | 678e12cc | Gleb Natapov | if (bsp) {
|
967 | a5b38b51 | aurel32 | /*
|
968 | a5b38b51 | aurel32 | * LINT0 delivery mode on CPU #0 is set to ExtInt at initialization
|
969 | a5b38b51 | aurel32 | * time typically by BIOS, so PIC interrupt can be delivered to the
|
970 | a5b38b51 | aurel32 | * processor when local APIC is enabled.
|
971 | a5b38b51 | aurel32 | */
|
972 | a5b38b51 | aurel32 | s->lvt[APIC_LVT_LINT0] = 0x700;
|
973 | a5b38b51 | aurel32 | } |
974 | d592d303 | bellard | } |
975 | 574bbf7b | bellard | |
976 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const apic_mem_read[3] = { |
977 | 574bbf7b | bellard | apic_mem_readb, |
978 | 574bbf7b | bellard | apic_mem_readw, |
979 | 574bbf7b | bellard | apic_mem_readl, |
980 | 574bbf7b | bellard | }; |
981 | 574bbf7b | bellard | |
982 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const apic_mem_write[3] = { |
983 | 574bbf7b | bellard | apic_mem_writeb, |
984 | 574bbf7b | bellard | apic_mem_writew, |
985 | 574bbf7b | bellard | apic_mem_writel, |
986 | 574bbf7b | bellard | }; |
987 | 574bbf7b | bellard | |
988 | 574bbf7b | bellard | int apic_init(CPUState *env)
|
989 | 574bbf7b | bellard | { |
990 | 574bbf7b | bellard | APICState *s; |
991 | 574bbf7b | bellard | |
992 | 678e12cc | Gleb Natapov | if (last_apic_idx >= MAX_APICS)
|
993 | d3e9db93 | bellard | return -1; |
994 | d592d303 | bellard | s = qemu_mallocz(sizeof(APICState));
|
995 | 574bbf7b | bellard | env->apic_state = s; |
996 | 678e12cc | Gleb Natapov | s->idx = last_apic_idx++; |
997 | 678e12cc | Gleb Natapov | s->id = env->cpuid_apic_id; |
998 | 574bbf7b | bellard | s->cpu_env = env; |
999 | 574bbf7b | bellard | |
1000 | 54c96da7 | Michael S. Tsirkin | msix_supported = 1;
|
1001 | 0e21e12b | ths | |
1002 | d592d303 | bellard | /* XXX: mapping more APICs at the same memory location */
|
1003 | 574bbf7b | bellard | if (apic_io_memory == 0) { |
1004 | 574bbf7b | bellard | /* NOTE: the APIC is directly connected to the CPU - it is not
|
1005 | 574bbf7b | bellard | on the global memory bus. */
|
1006 | 1eed09cb | Avi Kivity | apic_io_memory = cpu_register_io_memory(apic_mem_read, |
1007 | 574bbf7b | bellard | apic_mem_write, NULL);
|
1008 | 54c96da7 | Michael S. Tsirkin | /* XXX: what if the base changes? */
|
1009 | 54c96da7 | Michael S. Tsirkin | cpu_register_physical_memory(MSI_ADDR_BASE, MSI_ADDR_SIZE, |
1010 | d592d303 | bellard | apic_io_memory); |
1011 | 574bbf7b | bellard | } |
1012 | 574bbf7b | bellard | s->timer = qemu_new_timer(vm_clock, apic_timer, s); |
1013 | d592d303 | bellard | |
1014 | 695dcf71 | Juan Quintela | vmstate_register(s->idx, &vmstate_apic, s); |
1015 | a08d4367 | Jan Kiszka | qemu_register_reset(apic_reset, s); |
1016 | 3b46e624 | ths | |
1017 | 678e12cc | Gleb Natapov | local_apics[s->idx] = s; |
1018 | d592d303 | bellard | return 0; |
1019 | d592d303 | bellard | } |