Revision 73c69456
| b/hw/microblaze/Makefile.objs | ||
|---|---|---|
| 1 | 1 |
obj-y += petalogix_s3adsp1800_mmu.o |
| 2 | 2 |
obj-y += petalogix_ml605_mmu.o |
| 3 | 3 |
obj-y += boot.o |
| 4 |
obj-y += pic_cpu.o |
|
| b/hw/microblaze/petalogix_ml605_mmu.c | ||
|---|---|---|
| 39 | 39 |
#include "hw/ssi.h" |
| 40 | 40 |
|
| 41 | 41 |
#include "boot.h" |
| 42 |
#include "pic_cpu.h" |
|
| 43 | 42 |
|
| 44 | 43 |
#include "hw/stream.h" |
| 45 | 44 |
|
| ... | ... | |
| 82 | 81 |
Object *ds, *cs; |
| 83 | 82 |
MicroBlazeCPU *cpu; |
| 84 | 83 |
SysBusDevice *busdev; |
| 85 |
CPUMBState *env; |
|
| 86 | 84 |
DriveInfo *dinfo; |
| 87 | 85 |
int i; |
| 88 | 86 |
hwaddr ddr_base = MEMORY_BASEADDR; |
| 89 | 87 |
MemoryRegion *phys_lmb_bram = g_new(MemoryRegion, 1); |
| 90 | 88 |
MemoryRegion *phys_ram = g_new(MemoryRegion, 1); |
| 91 |
qemu_irq irq[32], *cpu_irq;
|
|
| 89 |
qemu_irq irq[32]; |
|
| 92 | 90 |
|
| 93 | 91 |
/* init CPUs */ |
| 94 | 92 |
if (cpu_model == NULL) {
|
| 95 | 93 |
cpu_model = "microblaze"; |
| 96 | 94 |
} |
| 97 | 95 |
cpu = cpu_mb_init(cpu_model); |
| 98 |
env = &cpu->env; |
|
| 99 | 96 |
|
| 100 | 97 |
/* Attach emulated BRAM through the LMB. */ |
| 101 | 98 |
memory_region_init_ram(phys_lmb_bram, NULL, "petalogix_ml605.lmb_bram", |
| ... | ... | |
| 117 | 114 |
2, 0x89, 0x18, 0x0000, 0x0, 0); |
| 118 | 115 |
|
| 119 | 116 |
|
| 120 |
cpu_irq = microblaze_pic_init_cpu(env);
|
|
| 121 |
dev = xilinx_intc_create(INTC_BASEADDR, cpu_irq[0], 4);
|
|
| 117 |
dev = xilinx_intc_create(INTC_BASEADDR, qdev_get_gpio_in(DEVICE(cpu),
|
|
| 118 |
MB_CPU_IRQ), 4);
|
|
| 122 | 119 |
for (i = 0; i < 32; i++) {
|
| 123 | 120 |
irq[i] = qdev_get_gpio_in(dev, i); |
| 124 | 121 |
} |
| b/hw/microblaze/petalogix_s3adsp1800_mmu.c | ||
|---|---|---|
| 35 | 35 |
#include "exec/address-spaces.h" |
| 36 | 36 |
|
| 37 | 37 |
#include "boot.h" |
| 38 |
#include "pic_cpu.h" |
|
| 39 | 38 |
|
| 40 | 39 |
#define LMB_BRAM_SIZE (128 * 1024) |
| 41 | 40 |
#define FLASH_SIZE (16 * 1024 * 1024) |
| ... | ... | |
| 63 | 62 |
const char *cpu_model = args->cpu_model; |
| 64 | 63 |
DeviceState *dev; |
| 65 | 64 |
MicroBlazeCPU *cpu; |
| 66 |
CPUMBState *env; |
|
| 67 | 65 |
DriveInfo *dinfo; |
| 68 | 66 |
int i; |
| 69 | 67 |
hwaddr ddr_base = MEMORY_BASEADDR; |
| 70 | 68 |
MemoryRegion *phys_lmb_bram = g_new(MemoryRegion, 1); |
| 71 | 69 |
MemoryRegion *phys_ram = g_new(MemoryRegion, 1); |
| 72 |
qemu_irq irq[32], *cpu_irq;
|
|
| 70 |
qemu_irq irq[32]; |
|
| 73 | 71 |
MemoryRegion *sysmem = get_system_memory(); |
| 74 | 72 |
|
| 75 | 73 |
/* init CPUs */ |
| ... | ... | |
| 77 | 75 |
cpu_model = "microblaze"; |
| 78 | 76 |
} |
| 79 | 77 |
cpu = cpu_mb_init(cpu_model); |
| 80 |
env = &cpu->env; |
|
| 81 | 78 |
|
| 82 | 79 |
/* Attach emulated BRAM through the LMB. */ |
| 83 | 80 |
memory_region_init_ram(phys_lmb_bram, NULL, |
| ... | ... | |
| 96 | 93 |
FLASH_SIZE >> 16, |
| 97 | 94 |
1, 0x89, 0x18, 0x0000, 0x0, 1); |
| 98 | 95 |
|
| 99 |
cpu_irq = microblaze_pic_init_cpu(env);
|
|
| 100 |
dev = xilinx_intc_create(INTC_BASEADDR, cpu_irq[0], 0xA);
|
|
| 96 |
dev = xilinx_intc_create(INTC_BASEADDR, qdev_get_gpio_in(DEVICE(cpu),
|
|
| 97 |
MB_CPU_IRQ), 0xA);
|
|
| 101 | 98 |
for (i = 0; i < 32; i++) {
|
| 102 | 99 |
irq[i] = qdev_get_gpio_in(dev, i); |
| 103 | 100 |
} |
| /dev/null | ||
|---|---|---|
| 1 |
/* |
|
| 2 |
* QEMU MicroBlaze CPU interrupt wrapper logic. |
|
| 3 |
* |
|
| 4 |
* Copyright (c) 2009 Edgar E. Iglesias, Axis Communications AB. |
|
| 5 |
* |
|
| 6 |
* Permission is hereby granted, free of charge, to any person obtaining a copy |
|
| 7 |
* of this software and associated documentation files (the "Software"), to deal |
|
| 8 |
* in the Software without restriction, including without limitation the rights |
|
| 9 |
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
|
| 10 |
* copies of the Software, and to permit persons to whom the Software is |
|
| 11 |
* furnished to do so, subject to the following conditions: |
|
| 12 |
* |
|
| 13 |
* The above copyright notice and this permission notice shall be included in |
|
| 14 |
* all copies or substantial portions of the Software. |
|
| 15 |
* |
|
| 16 |
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
|
| 17 |
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
|
| 18 |
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
|
| 19 |
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
|
| 20 |
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
|
| 21 |
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
|
| 22 |
* THE SOFTWARE. |
|
| 23 |
*/ |
|
| 24 |
|
|
| 25 |
#include "hw/hw.h" |
|
| 26 |
#include "pic_cpu.h" |
|
| 27 |
|
|
| 28 |
#define D(x) |
|
| 29 |
|
|
| 30 |
static void microblaze_pic_cpu_handler(void *opaque, int irq, int level) |
|
| 31 |
{
|
|
| 32 |
MicroBlazeCPU *cpu = opaque; |
|
| 33 |
CPUState *cs = CPU(cpu); |
|
| 34 |
int type = irq ? CPU_INTERRUPT_NMI : CPU_INTERRUPT_HARD; |
|
| 35 |
|
|
| 36 |
if (level) {
|
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| 37 |
cpu_interrupt(cs, type); |
|
| 38 |
} else {
|
|
| 39 |
cpu_reset_interrupt(cs, type); |
|
| 40 |
} |
|
| 41 |
} |
|
| 42 |
|
|
| 43 |
qemu_irq *microblaze_pic_init_cpu(CPUMBState *env) |
|
| 44 |
{
|
|
| 45 |
return qemu_allocate_irqs(microblaze_pic_cpu_handler, mb_env_get_cpu(env), |
|
| 46 |
2); |
|
| 47 |
} |
|
| /dev/null | ||
|---|---|---|
| 1 |
#ifndef MICROBLAZE_PIC_CPU_H |
|
| 2 |
#define MICROBLAZE_PIC_CPU_H |
|
| 3 |
|
|
| 4 |
#include "qemu-common.h" |
|
| 5 |
|
|
| 6 |
qemu_irq *microblaze_pic_init_cpu(CPUMBState *env); |
|
| 7 |
|
|
| 8 |
#endif /* MICROBLAZE_PIC_CPU_H */ |
|
| b/target-microblaze/cpu.c | ||
|---|---|---|
| 4 | 4 |
* Copyright (c) 2009 Edgar E. Iglesias |
| 5 | 5 |
* Copyright (c) 2009-2012 PetaLogix Qld Pty Ltd. |
| 6 | 6 |
* Copyright (c) 2012 SUSE LINUX Products GmbH |
| 7 |
* Copyright (c) 2009 Edgar E. Iglesias, Axis Communications AB. |
|
| 7 | 8 |
* |
| 8 | 9 |
* This library is free software; you can redistribute it and/or |
| 9 | 10 |
* modify it under the terms of the GNU Lesser General Public |
| ... | ... | |
| 33 | 34 |
cpu->env.sregs[SR_PC] = value; |
| 34 | 35 |
} |
| 35 | 36 |
|
| 37 |
#ifndef CONFIG_USER_ONLY |
|
| 38 |
static void microblaze_cpu_set_irq(void *opaque, int irq, int level) |
|
| 39 |
{
|
|
| 40 |
MicroBlazeCPU *cpu = opaque; |
|
| 41 |
CPUState *cs = CPU(cpu); |
|
| 42 |
int type = irq ? CPU_INTERRUPT_NMI : CPU_INTERRUPT_HARD; |
|
| 43 |
|
|
| 44 |
if (level) {
|
|
| 45 |
cpu_interrupt(cs, type); |
|
| 46 |
} else {
|
|
| 47 |
cpu_reset_interrupt(cs, type); |
|
| 48 |
} |
|
| 49 |
} |
|
| 50 |
#endif |
|
| 51 |
|
|
| 36 | 52 |
/* CPUClass::reset() */ |
| 37 | 53 |
static void mb_cpu_reset(CPUState *s) |
| 38 | 54 |
{
|
| ... | ... | |
| 111 | 127 |
|
| 112 | 128 |
set_float_rounding_mode(float_round_nearest_even, &env->fp_status); |
| 113 | 129 |
|
| 130 |
#ifndef CONFIG_USER_ONLY |
|
| 131 |
/* Inbound IRQ and FIR lines */ |
|
| 132 |
qdev_init_gpio_in(DEVICE(cpu), microblaze_cpu_set_irq, 2); |
|
| 133 |
#endif |
|
| 134 |
|
|
| 114 | 135 |
if (tcg_enabled() && !tcg_initialized) {
|
| 115 | 136 |
tcg_initialized = true; |
| 116 | 137 |
mb_tcg_init(); |
| b/target-microblaze/cpu.h | ||
|---|---|---|
| 48 | 48 |
/* MicroBlaze-specific interrupt pending bits. */ |
| 49 | 49 |
#define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_3 |
| 50 | 50 |
|
| 51 |
/* Meanings of the MBCPU object's two inbound GPIO lines */ |
|
| 52 |
#define MB_CPU_IRQ 0 |
|
| 53 |
#define MB_CPU_FIR 1 |
|
| 54 |
|
|
| 51 | 55 |
/* Register aliases. R0 - R15 */ |
| 52 | 56 |
#define R_SP 1 |
| 53 | 57 |
#define SR_PC 0 |
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