Revision 73e5716c
| b/target-sh4/cpu.h | ||
|---|---|---|
| 240 | 240 |
#define MMU_MODE0_SUFFIX _kernel |
| 241 | 241 |
#define MMU_MODE1_SUFFIX _user |
| 242 | 242 |
#define MMU_USER_IDX 1 |
| 243 |
static inline int cpu_mmu_index (CPUState *env) |
|
| 243 |
static inline int cpu_mmu_index (CPUSH4State *env)
|
|
| 244 | 244 |
{
|
| 245 | 245 |
return (env->sr & SR_MD) == 0 ? 1 : 0; |
| 246 | 246 |
} |
| 247 | 247 |
|
| 248 | 248 |
#if defined(CONFIG_USER_ONLY) |
| 249 |
static inline void cpu_clone_regs(CPUState *env, target_ulong newsp) |
|
| 249 |
static inline void cpu_clone_regs(CPUSH4State *env, target_ulong newsp)
|
|
| 250 | 250 |
{
|
| 251 | 251 |
if (newsp) |
| 252 | 252 |
env->gregs[15] = newsp; |
| ... | ... | |
| 348 | 348 |
|
| 349 | 349 |
#define TB_FLAG_PENDING_MOVCA (1 << 4) |
| 350 | 350 |
|
| 351 |
static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc, |
|
| 351 |
static inline void cpu_get_tb_cpu_state(CPUSH4State *env, target_ulong *pc,
|
|
| 352 | 352 |
target_ulong *cs_base, int *flags) |
| 353 | 353 |
{
|
| 354 | 354 |
*pc = env->pc; |
| ... | ... | |
| 361 | 361 |
| (env->movcal_backup ? TB_FLAG_PENDING_MOVCA : 0); /* Bit 4 */ |
| 362 | 362 |
} |
| 363 | 363 |
|
| 364 |
static inline bool cpu_has_work(CPUState *env) |
|
| 364 |
static inline bool cpu_has_work(CPUSH4State *env)
|
|
| 365 | 365 |
{
|
| 366 | 366 |
return env->interrupt_request & CPU_INTERRUPT_HARD; |
| 367 | 367 |
} |
| 368 | 368 |
|
| 369 | 369 |
#include "exec-all.h" |
| 370 | 370 |
|
| 371 |
static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb) |
|
| 371 |
static inline void cpu_pc_from_tb(CPUSH4State *env, TranslationBlock *tb)
|
|
| 372 | 372 |
{
|
| 373 | 373 |
env->pc = tb->pc; |
| 374 | 374 |
env->flags = tb->flags; |
| b/target-sh4/helper.c | ||
|---|---|---|
| 31 | 31 |
|
| 32 | 32 |
#if defined(CONFIG_USER_ONLY) |
| 33 | 33 |
|
| 34 |
void do_interrupt (CPUState *env) |
|
| 34 |
void do_interrupt (CPUSH4State *env)
|
|
| 35 | 35 |
{
|
| 36 | 36 |
env->exception_index = -1; |
| 37 | 37 |
} |
| 38 | 38 |
|
| 39 |
int cpu_sh4_handle_mmu_fault(CPUState * env, target_ulong address, int rw, |
|
| 39 |
int cpu_sh4_handle_mmu_fault(CPUSH4State * env, target_ulong address, int rw,
|
|
| 40 | 40 |
int mmu_idx) |
| 41 | 41 |
{
|
| 42 | 42 |
env->tea = address; |
| ... | ... | |
| 78 | 78 |
#define MMU_DADDR_ERROR_READ (-12) |
| 79 | 79 |
#define MMU_DADDR_ERROR_WRITE (-13) |
| 80 | 80 |
|
| 81 |
void do_interrupt(CPUState * env) |
|
| 81 |
void do_interrupt(CPUSH4State * env)
|
|
| 82 | 82 |
{
|
| 83 | 83 |
int do_irq = env->interrupt_request & CPU_INTERRUPT_HARD; |
| 84 | 84 |
int do_exp, irq_vector = env->exception_index; |
| ... | ... | |
| 202 | 202 |
} |
| 203 | 203 |
} |
| 204 | 204 |
|
| 205 |
static void update_itlb_use(CPUState * env, int itlbnb) |
|
| 205 |
static void update_itlb_use(CPUSH4State * env, int itlbnb)
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|
| 206 | 206 |
{
|
| 207 | 207 |
uint8_t or_mask = 0, and_mask = (uint8_t) - 1; |
| 208 | 208 |
|
| ... | ... | |
| 227 | 227 |
env->mmucr |= (or_mask << 24); |
| 228 | 228 |
} |
| 229 | 229 |
|
| 230 |
static int itlb_replacement(CPUState * env) |
|
| 230 |
static int itlb_replacement(CPUSH4State * env)
|
|
| 231 | 231 |
{
|
| 232 | 232 |
if ((env->mmucr & 0xe0000000) == 0xe0000000) |
| 233 | 233 |
return 0; |
| ... | ... | |
| 243 | 243 |
/* Find the corresponding entry in the right TLB |
| 244 | 244 |
Return entry, MMU_DTLB_MISS or MMU_DTLB_MULTIPLE |
| 245 | 245 |
*/ |
| 246 |
static int find_tlb_entry(CPUState * env, target_ulong address, |
|
| 246 |
static int find_tlb_entry(CPUSH4State * env, target_ulong address,
|
|
| 247 | 247 |
tlb_t * entries, uint8_t nbtlb, int use_asid) |
| 248 | 248 |
{
|
| 249 | 249 |
int match = MMU_DTLB_MISS; |
| ... | ... | |
| 269 | 269 |
return match; |
| 270 | 270 |
} |
| 271 | 271 |
|
| 272 |
static void increment_urc(CPUState * env) |
|
| 272 |
static void increment_urc(CPUSH4State * env)
|
|
| 273 | 273 |
{
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| 274 | 274 |
uint8_t urb, urc; |
| 275 | 275 |
|
| ... | ... | |
| 285 | 285 |
/* Copy and utlb entry into itlb |
| 286 | 286 |
Return entry |
| 287 | 287 |
*/ |
| 288 |
static int copy_utlb_entry_itlb(CPUState *env, int utlb) |
|
| 288 |
static int copy_utlb_entry_itlb(CPUSH4State *env, int utlb)
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| 289 | 289 |
{
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| 290 | 290 |
int itlb; |
| 291 | 291 |
|
| ... | ... | |
| 303 | 303 |
/* Find itlb entry |
| 304 | 304 |
Return entry, MMU_ITLB_MISS, MMU_ITLB_MULTIPLE or MMU_DTLB_MULTIPLE |
| 305 | 305 |
*/ |
| 306 |
static int find_itlb_entry(CPUState * env, target_ulong address, |
|
| 306 |
static int find_itlb_entry(CPUSH4State * env, target_ulong address,
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| 307 | 307 |
int use_asid) |
| 308 | 308 |
{
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| 309 | 309 |
int e; |
| ... | ... | |
| 321 | 321 |
|
| 322 | 322 |
/* Find utlb entry |
| 323 | 323 |
Return entry, MMU_DTLB_MISS, MMU_DTLB_MULTIPLE */ |
| 324 |
static int find_utlb_entry(CPUState * env, target_ulong address, int use_asid) |
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| 324 |
static int find_utlb_entry(CPUSH4State * env, target_ulong address, int use_asid)
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| 325 | 325 |
{
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| 326 | 326 |
/* per utlb access */ |
| 327 | 327 |
increment_urc(env); |
| ... | ... | |
| 337 | 337 |
MMU_ITLB_MULTIPLE, MMU_ITLB_VIOLATION, |
| 338 | 338 |
MMU_IADDR_ERROR, MMU_DADDR_ERROR_READ, MMU_DADDR_ERROR_WRITE. |
| 339 | 339 |
*/ |
| 340 |
static int get_mmu_address(CPUState * env, target_ulong * physical, |
|
| 340 |
static int get_mmu_address(CPUSH4State * env, target_ulong * physical,
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| 341 | 341 |
int *prot, target_ulong address, |
| 342 | 342 |
int rw, int access_type) |
| 343 | 343 |
{
|
| ... | ... | |
| 403 | 403 |
return n; |
| 404 | 404 |
} |
| 405 | 405 |
|
| 406 |
static int get_physical_address(CPUState * env, target_ulong * physical, |
|
| 406 |
static int get_physical_address(CPUSH4State * env, target_ulong * physical,
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| 407 | 407 |
int *prot, target_ulong address, |
| 408 | 408 |
int rw, int access_type) |
| 409 | 409 |
{
|
| ... | ... | |
| 442 | 442 |
return get_mmu_address(env, physical, prot, address, rw, access_type); |
| 443 | 443 |
} |
| 444 | 444 |
|
| 445 |
int cpu_sh4_handle_mmu_fault(CPUState * env, target_ulong address, int rw, |
|
| 445 |
int cpu_sh4_handle_mmu_fault(CPUSH4State * env, target_ulong address, int rw,
|
|
| 446 | 446 |
int mmu_idx) |
| 447 | 447 |
{
|
| 448 | 448 |
target_ulong physical; |
| ... | ... | |
| 503 | 503 |
return 0; |
| 504 | 504 |
} |
| 505 | 505 |
|
| 506 |
target_phys_addr_t cpu_get_phys_page_debug(CPUState * env, target_ulong addr) |
|
| 506 |
target_phys_addr_t cpu_get_phys_page_debug(CPUSH4State * env, target_ulong addr)
|
|
| 507 | 507 |
{
|
| 508 | 508 |
target_ulong physical; |
| 509 | 509 |
int prot; |
| b/target-sh4/op_helper.c | ||
|---|---|---|
| 55 | 55 |
#define SHIFT 3 |
| 56 | 56 |
#include "softmmu_template.h" |
| 57 | 57 |
|
| 58 |
void tlb_fill(CPUState *env1, target_ulong addr, int is_write, int mmu_idx, |
|
| 58 |
void tlb_fill(CPUSH4State *env1, target_ulong addr, int is_write, int mmu_idx,
|
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| 59 | 59 |
void *retaddr) |
| 60 | 60 |
{
|
| 61 |
CPUState *saved_env; |
|
| 61 |
CPUSH4State *saved_env;
|
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| 62 | 62 |
int ret; |
| 63 | 63 |
|
| 64 | 64 |
saved_env = env; |
| b/target-sh4/translate.c | ||
|---|---|---|
| 103 | 103 |
|
| 104 | 104 |
for (i = 0; i < 24; i++) |
| 105 | 105 |
cpu_gregs[i] = tcg_global_mem_new_i32(TCG_AREG0, |
| 106 |
offsetof(CPUState, gregs[i]), |
|
| 106 |
offsetof(CPUSH4State, gregs[i]),
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|
| 107 | 107 |
gregnames[i]); |
| 108 | 108 |
|
| 109 | 109 |
cpu_pc = tcg_global_mem_new_i32(TCG_AREG0, |
| 110 |
offsetof(CPUState, pc), "PC"); |
|
| 110 |
offsetof(CPUSH4State, pc), "PC");
|
|
| 111 | 111 |
cpu_sr = tcg_global_mem_new_i32(TCG_AREG0, |
| 112 |
offsetof(CPUState, sr), "SR"); |
|
| 112 |
offsetof(CPUSH4State, sr), "SR");
|
|
| 113 | 113 |
cpu_ssr = tcg_global_mem_new_i32(TCG_AREG0, |
| 114 |
offsetof(CPUState, ssr), "SSR"); |
|
| 114 |
offsetof(CPUSH4State, ssr), "SSR");
|
|
| 115 | 115 |
cpu_spc = tcg_global_mem_new_i32(TCG_AREG0, |
| 116 |
offsetof(CPUState, spc), "SPC"); |
|
| 116 |
offsetof(CPUSH4State, spc), "SPC");
|
|
| 117 | 117 |
cpu_gbr = tcg_global_mem_new_i32(TCG_AREG0, |
| 118 |
offsetof(CPUState, gbr), "GBR"); |
|
| 118 |
offsetof(CPUSH4State, gbr), "GBR");
|
|
| 119 | 119 |
cpu_vbr = tcg_global_mem_new_i32(TCG_AREG0, |
| 120 |
offsetof(CPUState, vbr), "VBR"); |
|
| 120 |
offsetof(CPUSH4State, vbr), "VBR");
|
|
| 121 | 121 |
cpu_sgr = tcg_global_mem_new_i32(TCG_AREG0, |
| 122 |
offsetof(CPUState, sgr), "SGR"); |
|
| 122 |
offsetof(CPUSH4State, sgr), "SGR");
|
|
| 123 | 123 |
cpu_dbr = tcg_global_mem_new_i32(TCG_AREG0, |
| 124 |
offsetof(CPUState, dbr), "DBR"); |
|
| 124 |
offsetof(CPUSH4State, dbr), "DBR");
|
|
| 125 | 125 |
cpu_mach = tcg_global_mem_new_i32(TCG_AREG0, |
| 126 |
offsetof(CPUState, mach), "MACH"); |
|
| 126 |
offsetof(CPUSH4State, mach), "MACH");
|
|
| 127 | 127 |
cpu_macl = tcg_global_mem_new_i32(TCG_AREG0, |
| 128 |
offsetof(CPUState, macl), "MACL"); |
|
| 128 |
offsetof(CPUSH4State, macl), "MACL");
|
|
| 129 | 129 |
cpu_pr = tcg_global_mem_new_i32(TCG_AREG0, |
| 130 |
offsetof(CPUState, pr), "PR"); |
|
| 130 |
offsetof(CPUSH4State, pr), "PR");
|
|
| 131 | 131 |
cpu_fpscr = tcg_global_mem_new_i32(TCG_AREG0, |
| 132 |
offsetof(CPUState, fpscr), "FPSCR"); |
|
| 132 |
offsetof(CPUSH4State, fpscr), "FPSCR");
|
|
| 133 | 133 |
cpu_fpul = tcg_global_mem_new_i32(TCG_AREG0, |
| 134 |
offsetof(CPUState, fpul), "FPUL"); |
|
| 134 |
offsetof(CPUSH4State, fpul), "FPUL");
|
|
| 135 | 135 |
|
| 136 | 136 |
cpu_flags = tcg_global_mem_new_i32(TCG_AREG0, |
| 137 |
offsetof(CPUState, flags), "_flags_"); |
|
| 137 |
offsetof(CPUSH4State, flags), "_flags_");
|
|
| 138 | 138 |
cpu_delayed_pc = tcg_global_mem_new_i32(TCG_AREG0, |
| 139 |
offsetof(CPUState, delayed_pc), |
|
| 139 |
offsetof(CPUSH4State, delayed_pc),
|
|
| 140 | 140 |
"_delayed_pc_"); |
| 141 | 141 |
cpu_ldst = tcg_global_mem_new_i32(TCG_AREG0, |
| 142 |
offsetof(CPUState, ldst), "_ldst_"); |
|
| 142 |
offsetof(CPUSH4State, ldst), "_ldst_");
|
|
| 143 | 143 |
|
| 144 | 144 |
for (i = 0; i < 32; i++) |
| 145 | 145 |
cpu_fregs[i] = tcg_global_mem_new_i32(TCG_AREG0, |
| 146 |
offsetof(CPUState, fregs[i]), |
|
| 146 |
offsetof(CPUSH4State, fregs[i]),
|
|
| 147 | 147 |
fregnames[i]); |
| 148 | 148 |
|
| 149 | 149 |
/* register helpers */ |
| ... | ... | |
| 153 | 153 |
done_init = 1; |
| 154 | 154 |
} |
| 155 | 155 |
|
| 156 |
void cpu_dump_state(CPUState * env, FILE * f, |
|
| 156 |
void cpu_dump_state(CPUSH4State * env, FILE * f,
|
|
| 157 | 157 |
int (*cpu_fprintf) (FILE * f, const char *fmt, ...), |
| 158 | 158 |
int flags) |
| 159 | 159 |
{
|
| ... | ... | |
| 1918 | 1918 |
} |
| 1919 | 1919 |
|
| 1920 | 1920 |
static inline void |
| 1921 |
gen_intermediate_code_internal(CPUState * env, TranslationBlock * tb, |
|
| 1921 |
gen_intermediate_code_internal(CPUSH4State * env, TranslationBlock * tb,
|
|
| 1922 | 1922 |
int search_pc) |
| 1923 | 1923 |
{
|
| 1924 | 1924 |
DisasContext ctx; |
| ... | ... | |
| 2044 | 2044 |
#endif |
| 2045 | 2045 |
} |
| 2046 | 2046 |
|
| 2047 |
void gen_intermediate_code(CPUState * env, struct TranslationBlock *tb) |
|
| 2047 |
void gen_intermediate_code(CPUSH4State * env, struct TranslationBlock *tb)
|
|
| 2048 | 2048 |
{
|
| 2049 | 2049 |
gen_intermediate_code_internal(env, tb, 0); |
| 2050 | 2050 |
} |
| 2051 | 2051 |
|
| 2052 |
void gen_intermediate_code_pc(CPUState * env, struct TranslationBlock *tb) |
|
| 2052 |
void gen_intermediate_code_pc(CPUSH4State * env, struct TranslationBlock *tb)
|
|
| 2053 | 2053 |
{
|
| 2054 | 2054 |
gen_intermediate_code_internal(env, tb, 1); |
| 2055 | 2055 |
} |
| 2056 | 2056 |
|
| 2057 |
void restore_state_to_opc(CPUState *env, TranslationBlock *tb, int pc_pos) |
|
| 2057 |
void restore_state_to_opc(CPUSH4State *env, TranslationBlock *tb, int pc_pos)
|
|
| 2058 | 2058 |
{
|
| 2059 | 2059 |
env->pc = gen_opc_pc[pc_pos]; |
| 2060 | 2060 |
env->flags = gen_opc_hflags[pc_pos]; |
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