root / hw / parallel.c @ 746d6de7
History | View | Annotate | Download (16 kB)
1 | 6508fe59 | bellard | /*
|
---|---|---|---|
2 | 6508fe59 | bellard | * QEMU Parallel PORT emulation
|
3 | 5fafdf24 | ths | *
|
4 | e57a8c0e | bellard | * Copyright (c) 2003-2005 Fabrice Bellard
|
5 | 5867c88a | ths | * Copyright (c) 2007 Marko Kohtala
|
6 | 5fafdf24 | ths | *
|
7 | 6508fe59 | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
|
8 | 6508fe59 | bellard | * of this software and associated documentation files (the "Software"), to deal
|
9 | 6508fe59 | bellard | * in the Software without restriction, including without limitation the rights
|
10 | 6508fe59 | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
11 | 6508fe59 | bellard | * copies of the Software, and to permit persons to whom the Software is
|
12 | 6508fe59 | bellard | * furnished to do so, subject to the following conditions:
|
13 | 6508fe59 | bellard | *
|
14 | 6508fe59 | bellard | * The above copyright notice and this permission notice shall be included in
|
15 | 6508fe59 | bellard | * all copies or substantial portions of the Software.
|
16 | 6508fe59 | bellard | *
|
17 | 6508fe59 | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
18 | 6508fe59 | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
19 | 6508fe59 | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
20 | 6508fe59 | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
21 | 6508fe59 | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
22 | 6508fe59 | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
23 | 6508fe59 | bellard | * THE SOFTWARE.
|
24 | 6508fe59 | bellard | */
|
25 | 87ecb68b | pbrook | #include "hw.h" |
26 | 87ecb68b | pbrook | #include "qemu-char.h" |
27 | 87ecb68b | pbrook | #include "isa.h" |
28 | 87ecb68b | pbrook | #include "pc.h" |
29 | 6508fe59 | bellard | |
30 | 6508fe59 | bellard | //#define DEBUG_PARALLEL
|
31 | 6508fe59 | bellard | |
32 | 5867c88a | ths | #ifdef DEBUG_PARALLEL
|
33 | 5867c88a | ths | #define pdebug(fmt, arg...) printf("pp: " fmt, ##arg) |
34 | 5867c88a | ths | #else
|
35 | 5867c88a | ths | #define pdebug(fmt, arg...) ((void)0) |
36 | 5867c88a | ths | #endif
|
37 | 5867c88a | ths | |
38 | 5867c88a | ths | #define PARA_REG_DATA 0 |
39 | 5867c88a | ths | #define PARA_REG_STS 1 |
40 | 5867c88a | ths | #define PARA_REG_CTR 2 |
41 | 5867c88a | ths | #define PARA_REG_EPP_ADDR 3 |
42 | 5867c88a | ths | #define PARA_REG_EPP_DATA 4 |
43 | 5867c88a | ths | |
44 | 6508fe59 | bellard | /*
|
45 | 6508fe59 | bellard | * These are the definitions for the Printer Status Register
|
46 | 6508fe59 | bellard | */
|
47 | 6508fe59 | bellard | #define PARA_STS_BUSY 0x80 /* Busy complement */ |
48 | 6508fe59 | bellard | #define PARA_STS_ACK 0x40 /* Acknowledge */ |
49 | 6508fe59 | bellard | #define PARA_STS_PAPER 0x20 /* Out of paper */ |
50 | 6508fe59 | bellard | #define PARA_STS_ONLINE 0x10 /* Online */ |
51 | 6508fe59 | bellard | #define PARA_STS_ERROR 0x08 /* Error complement */ |
52 | 5867c88a | ths | #define PARA_STS_TMOUT 0x01 /* EPP timeout */ |
53 | 6508fe59 | bellard | |
54 | 6508fe59 | bellard | /*
|
55 | 6508fe59 | bellard | * These are the definitions for the Printer Control Register
|
56 | 6508fe59 | bellard | */
|
57 | 5867c88a | ths | #define PARA_CTR_DIR 0x20 /* Direction (1=read, 0=write) */ |
58 | 6508fe59 | bellard | #define PARA_CTR_INTEN 0x10 /* IRQ Enable */ |
59 | 6508fe59 | bellard | #define PARA_CTR_SELECT 0x08 /* Select In complement */ |
60 | 6508fe59 | bellard | #define PARA_CTR_INIT 0x04 /* Initialize Printer complement */ |
61 | 6508fe59 | bellard | #define PARA_CTR_AUTOLF 0x02 /* Auto linefeed complement */ |
62 | 6508fe59 | bellard | #define PARA_CTR_STROBE 0x01 /* Strobe complement */ |
63 | 6508fe59 | bellard | |
64 | 5867c88a | ths | #define PARA_CTR_SIGNAL (PARA_CTR_SELECT|PARA_CTR_INIT|PARA_CTR_AUTOLF|PARA_CTR_STROBE)
|
65 | 5867c88a | ths | |
66 | 6508fe59 | bellard | struct ParallelState {
|
67 | 5867c88a | ths | uint8_t dataw; |
68 | 5867c88a | ths | uint8_t datar; |
69 | 5867c88a | ths | uint8_t status; |
70 | 6508fe59 | bellard | uint8_t control; |
71 | d537cf6c | pbrook | qemu_irq irq; |
72 | 6508fe59 | bellard | int irq_pending;
|
73 | 6508fe59 | bellard | CharDriverState *chr; |
74 | e57a8c0e | bellard | int hw_driver;
|
75 | 5867c88a | ths | int epp_timeout;
|
76 | 5867c88a | ths | uint32_t last_read_offset; /* For debugging */
|
77 | d60532ca | ths | /* Memory-mapped interface */
|
78 | d60532ca | ths | target_phys_addr_t base; |
79 | d60532ca | ths | int it_shift;
|
80 | 6508fe59 | bellard | }; |
81 | 6508fe59 | bellard | |
82 | 6508fe59 | bellard | static void parallel_update_irq(ParallelState *s) |
83 | 6508fe59 | bellard | { |
84 | 6508fe59 | bellard | if (s->irq_pending)
|
85 | d537cf6c | pbrook | qemu_irq_raise(s->irq); |
86 | 6508fe59 | bellard | else
|
87 | d537cf6c | pbrook | qemu_irq_lower(s->irq); |
88 | 6508fe59 | bellard | } |
89 | 6508fe59 | bellard | |
90 | 5867c88a | ths | static void |
91 | 5867c88a | ths | parallel_ioport_write_sw(void *opaque, uint32_t addr, uint32_t val)
|
92 | 6508fe59 | bellard | { |
93 | 6508fe59 | bellard | ParallelState *s = opaque; |
94 | 3b46e624 | ths | |
95 | 5867c88a | ths | pdebug("write addr=0x%02x val=0x%02x\n", addr, val);
|
96 | 5867c88a | ths | |
97 | 5867c88a | ths | addr &= 7;
|
98 | 5867c88a | ths | switch(addr) {
|
99 | 5867c88a | ths | case PARA_REG_DATA:
|
100 | 0fa7f157 | ths | s->dataw = val; |
101 | 0fa7f157 | ths | parallel_update_irq(s); |
102 | 5867c88a | ths | break;
|
103 | 5867c88a | ths | case PARA_REG_CTR:
|
104 | 52ccc5e0 | balrog | val |= 0xc0;
|
105 | 0fa7f157 | ths | if ((val & PARA_CTR_INIT) == 0 ) { |
106 | 0fa7f157 | ths | s->status = PARA_STS_BUSY; |
107 | 0fa7f157 | ths | s->status |= PARA_STS_ACK; |
108 | 0fa7f157 | ths | s->status |= PARA_STS_ONLINE; |
109 | 0fa7f157 | ths | s->status |= PARA_STS_ERROR; |
110 | 0fa7f157 | ths | } |
111 | 0fa7f157 | ths | else if (val & PARA_CTR_SELECT) { |
112 | 0fa7f157 | ths | if (val & PARA_CTR_STROBE) {
|
113 | 0fa7f157 | ths | s->status &= ~PARA_STS_BUSY; |
114 | 0fa7f157 | ths | if ((s->control & PARA_CTR_STROBE) == 0) |
115 | 0fa7f157 | ths | qemu_chr_write(s->chr, &s->dataw, 1);
|
116 | 0fa7f157 | ths | } else {
|
117 | 0fa7f157 | ths | if (s->control & PARA_CTR_INTEN) {
|
118 | 0fa7f157 | ths | s->irq_pending = 1;
|
119 | 0fa7f157 | ths | } |
120 | 0fa7f157 | ths | } |
121 | 0fa7f157 | ths | } |
122 | 0fa7f157 | ths | parallel_update_irq(s); |
123 | 0fa7f157 | ths | s->control = val; |
124 | 5867c88a | ths | break;
|
125 | 5867c88a | ths | } |
126 | 5867c88a | ths | } |
127 | 5867c88a | ths | |
128 | 5867c88a | ths | static void parallel_ioport_write_hw(void *opaque, uint32_t addr, uint32_t val) |
129 | 5867c88a | ths | { |
130 | 5867c88a | ths | ParallelState *s = opaque; |
131 | 5867c88a | ths | uint8_t parm = val; |
132 | 5867c88a | ths | |
133 | 5867c88a | ths | /* Sometimes programs do several writes for timing purposes on old
|
134 | 5867c88a | ths | HW. Take care not to waste time on writes that do nothing. */
|
135 | 5867c88a | ths | |
136 | 5867c88a | ths | s->last_read_offset = ~0U;
|
137 | 5867c88a | ths | |
138 | 6508fe59 | bellard | addr &= 7;
|
139 | 6508fe59 | bellard | switch(addr) {
|
140 | 5867c88a | ths | case PARA_REG_DATA:
|
141 | 5867c88a | ths | if (s->dataw == val)
|
142 | 0fa7f157 | ths | return;
|
143 | 0fa7f157 | ths | pdebug("wd%02x\n", val);
|
144 | 0fa7f157 | ths | qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_WRITE_DATA, &parm); |
145 | 0fa7f157 | ths | s->dataw = val; |
146 | 6508fe59 | bellard | break;
|
147 | 5867c88a | ths | case PARA_REG_STS:
|
148 | 0fa7f157 | ths | pdebug("ws%02x\n", val);
|
149 | 0fa7f157 | ths | if (val & PARA_STS_TMOUT)
|
150 | 0fa7f157 | ths | s->epp_timeout = 0;
|
151 | 0fa7f157 | ths | break;
|
152 | 5867c88a | ths | case PARA_REG_CTR:
|
153 | 5867c88a | ths | val |= 0xc0;
|
154 | 5867c88a | ths | if (s->control == val)
|
155 | 0fa7f157 | ths | return;
|
156 | 0fa7f157 | ths | pdebug("wc%02x\n", val);
|
157 | 0fa7f157 | ths | qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_WRITE_CONTROL, &parm); |
158 | 0fa7f157 | ths | s->control = val; |
159 | 6508fe59 | bellard | break;
|
160 | 5867c88a | ths | case PARA_REG_EPP_ADDR:
|
161 | 0fa7f157 | ths | if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT)
|
162 | 0fa7f157 | ths | /* Controls not correct for EPP address cycle, so do nothing */
|
163 | 0fa7f157 | ths | pdebug("wa%02x s\n", val);
|
164 | 0fa7f157 | ths | else {
|
165 | 0fa7f157 | ths | struct ParallelIOArg ioarg = { .buffer = &parm, .count = 1 }; |
166 | 0fa7f157 | ths | if (qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE_ADDR, &ioarg)) {
|
167 | 0fa7f157 | ths | s->epp_timeout = 1;
|
168 | 0fa7f157 | ths | pdebug("wa%02x t\n", val);
|
169 | 0fa7f157 | ths | } |
170 | 0fa7f157 | ths | else
|
171 | 0fa7f157 | ths | pdebug("wa%02x\n", val);
|
172 | 0fa7f157 | ths | } |
173 | 0fa7f157 | ths | break;
|
174 | 5867c88a | ths | case PARA_REG_EPP_DATA:
|
175 | 0fa7f157 | ths | if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT)
|
176 | 0fa7f157 | ths | /* Controls not correct for EPP data cycle, so do nothing */
|
177 | 0fa7f157 | ths | pdebug("we%02x s\n", val);
|
178 | 0fa7f157 | ths | else {
|
179 | 0fa7f157 | ths | struct ParallelIOArg ioarg = { .buffer = &parm, .count = 1 }; |
180 | 0fa7f157 | ths | if (qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg)) {
|
181 | 0fa7f157 | ths | s->epp_timeout = 1;
|
182 | 0fa7f157 | ths | pdebug("we%02x t\n", val);
|
183 | 0fa7f157 | ths | } |
184 | 0fa7f157 | ths | else
|
185 | 0fa7f157 | ths | pdebug("we%02x\n", val);
|
186 | 0fa7f157 | ths | } |
187 | 0fa7f157 | ths | break;
|
188 | 5867c88a | ths | } |
189 | 5867c88a | ths | } |
190 | 5867c88a | ths | |
191 | 5867c88a | ths | static void |
192 | 5867c88a | ths | parallel_ioport_eppdata_write_hw2(void *opaque, uint32_t addr, uint32_t val)
|
193 | 5867c88a | ths | { |
194 | 5867c88a | ths | ParallelState *s = opaque; |
195 | 5867c88a | ths | uint16_t eppdata = cpu_to_le16(val); |
196 | 5867c88a | ths | int err;
|
197 | 5867c88a | ths | struct ParallelIOArg ioarg = {
|
198 | 0fa7f157 | ths | .buffer = &eppdata, .count = sizeof(eppdata)
|
199 | 5867c88a | ths | }; |
200 | 5867c88a | ths | if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT) {
|
201 | 0fa7f157 | ths | /* Controls not correct for EPP data cycle, so do nothing */
|
202 | 0fa7f157 | ths | pdebug("we%04x s\n", val);
|
203 | 0fa7f157 | ths | return;
|
204 | 5867c88a | ths | } |
205 | 5867c88a | ths | err = qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg); |
206 | 5867c88a | ths | if (err) {
|
207 | 0fa7f157 | ths | s->epp_timeout = 1;
|
208 | 0fa7f157 | ths | pdebug("we%04x t\n", val);
|
209 | 5867c88a | ths | } |
210 | 5867c88a | ths | else
|
211 | 0fa7f157 | ths | pdebug("we%04x\n", val);
|
212 | 5867c88a | ths | } |
213 | 5867c88a | ths | |
214 | 5867c88a | ths | static void |
215 | 5867c88a | ths | parallel_ioport_eppdata_write_hw4(void *opaque, uint32_t addr, uint32_t val)
|
216 | 5867c88a | ths | { |
217 | 5867c88a | ths | ParallelState *s = opaque; |
218 | 5867c88a | ths | uint32_t eppdata = cpu_to_le32(val); |
219 | 5867c88a | ths | int err;
|
220 | 5867c88a | ths | struct ParallelIOArg ioarg = {
|
221 | 0fa7f157 | ths | .buffer = &eppdata, .count = sizeof(eppdata)
|
222 | 5867c88a | ths | }; |
223 | 5867c88a | ths | if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT) {
|
224 | 0fa7f157 | ths | /* Controls not correct for EPP data cycle, so do nothing */
|
225 | 0fa7f157 | ths | pdebug("we%08x s\n", val);
|
226 | 0fa7f157 | ths | return;
|
227 | 5867c88a | ths | } |
228 | 5867c88a | ths | err = qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg); |
229 | 5867c88a | ths | if (err) {
|
230 | 0fa7f157 | ths | s->epp_timeout = 1;
|
231 | 0fa7f157 | ths | pdebug("we%08x t\n", val);
|
232 | 6508fe59 | bellard | } |
233 | 5867c88a | ths | else
|
234 | 0fa7f157 | ths | pdebug("we%08x\n", val);
|
235 | 6508fe59 | bellard | } |
236 | 6508fe59 | bellard | |
237 | 5867c88a | ths | static uint32_t parallel_ioport_read_sw(void *opaque, uint32_t addr) |
238 | 6508fe59 | bellard | { |
239 | 6508fe59 | bellard | ParallelState *s = opaque; |
240 | 6508fe59 | bellard | uint32_t ret = 0xff;
|
241 | 6508fe59 | bellard | |
242 | 6508fe59 | bellard | addr &= 7;
|
243 | 6508fe59 | bellard | switch(addr) {
|
244 | 5867c88a | ths | case PARA_REG_DATA:
|
245 | 0fa7f157 | ths | if (s->control & PARA_CTR_DIR)
|
246 | 0fa7f157 | ths | ret = s->datar; |
247 | 0fa7f157 | ths | else
|
248 | 0fa7f157 | ths | ret = s->dataw; |
249 | 6508fe59 | bellard | break;
|
250 | 5867c88a | ths | case PARA_REG_STS:
|
251 | 0fa7f157 | ths | ret = s->status; |
252 | 0fa7f157 | ths | s->irq_pending = 0;
|
253 | 0fa7f157 | ths | if ((s->status & PARA_STS_BUSY) == 0 && (s->control & PARA_CTR_STROBE) == 0) { |
254 | 0fa7f157 | ths | /* XXX Fixme: wait 5 microseconds */
|
255 | 0fa7f157 | ths | if (s->status & PARA_STS_ACK)
|
256 | 0fa7f157 | ths | s->status &= ~PARA_STS_ACK; |
257 | 0fa7f157 | ths | else {
|
258 | 0fa7f157 | ths | /* XXX Fixme: wait 5 microseconds */
|
259 | 0fa7f157 | ths | s->status |= PARA_STS_ACK; |
260 | 0fa7f157 | ths | s->status |= PARA_STS_BUSY; |
261 | 0fa7f157 | ths | } |
262 | 0fa7f157 | ths | } |
263 | 0fa7f157 | ths | parallel_update_irq(s); |
264 | 6508fe59 | bellard | break;
|
265 | 5867c88a | ths | case PARA_REG_CTR:
|
266 | 6508fe59 | bellard | ret = s->control; |
267 | 6508fe59 | bellard | break;
|
268 | 6508fe59 | bellard | } |
269 | 5867c88a | ths | pdebug("read addr=0x%02x val=0x%02x\n", addr, ret);
|
270 | 5867c88a | ths | return ret;
|
271 | 5867c88a | ths | } |
272 | 5867c88a | ths | |
273 | 5867c88a | ths | static uint32_t parallel_ioport_read_hw(void *opaque, uint32_t addr) |
274 | 5867c88a | ths | { |
275 | 5867c88a | ths | ParallelState *s = opaque; |
276 | 5867c88a | ths | uint8_t ret = 0xff;
|
277 | 5867c88a | ths | addr &= 7;
|
278 | 5867c88a | ths | switch(addr) {
|
279 | 5867c88a | ths | case PARA_REG_DATA:
|
280 | 0fa7f157 | ths | qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_READ_DATA, &ret); |
281 | 0fa7f157 | ths | if (s->last_read_offset != addr || s->datar != ret)
|
282 | 0fa7f157 | ths | pdebug("rd%02x\n", ret);
|
283 | 5867c88a | ths | s->datar = ret; |
284 | 5867c88a | ths | break;
|
285 | 5867c88a | ths | case PARA_REG_STS:
|
286 | 0fa7f157 | ths | qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_READ_STATUS, &ret); |
287 | 0fa7f157 | ths | ret &= ~PARA_STS_TMOUT; |
288 | 0fa7f157 | ths | if (s->epp_timeout)
|
289 | 0fa7f157 | ths | ret |= PARA_STS_TMOUT; |
290 | 0fa7f157 | ths | if (s->last_read_offset != addr || s->status != ret)
|
291 | 0fa7f157 | ths | pdebug("rs%02x\n", ret);
|
292 | 0fa7f157 | ths | s->status = ret; |
293 | 5867c88a | ths | break;
|
294 | 5867c88a | ths | case PARA_REG_CTR:
|
295 | 5867c88a | ths | /* s->control has some bits fixed to 1. It is zero only when
|
296 | 0fa7f157 | ths | it has not been yet written to. */
|
297 | 0fa7f157 | ths | if (s->control == 0) { |
298 | 0fa7f157 | ths | qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_READ_CONTROL, &ret); |
299 | 0fa7f157 | ths | if (s->last_read_offset != addr)
|
300 | 0fa7f157 | ths | pdebug("rc%02x\n", ret);
|
301 | 0fa7f157 | ths | s->control = ret; |
302 | 0fa7f157 | ths | } |
303 | 0fa7f157 | ths | else {
|
304 | 0fa7f157 | ths | ret = s->control; |
305 | 0fa7f157 | ths | if (s->last_read_offset != addr)
|
306 | 0fa7f157 | ths | pdebug("rc%02x\n", ret);
|
307 | 0fa7f157 | ths | } |
308 | 5867c88a | ths | break;
|
309 | 5867c88a | ths | case PARA_REG_EPP_ADDR:
|
310 | 0fa7f157 | ths | if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR|PARA_CTR_INIT))
|
311 | 0fa7f157 | ths | /* Controls not correct for EPP addr cycle, so do nothing */
|
312 | 0fa7f157 | ths | pdebug("ra%02x s\n", ret);
|
313 | 0fa7f157 | ths | else {
|
314 | 0fa7f157 | ths | struct ParallelIOArg ioarg = { .buffer = &ret, .count = 1 }; |
315 | 0fa7f157 | ths | if (qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ_ADDR, &ioarg)) {
|
316 | 0fa7f157 | ths | s->epp_timeout = 1;
|
317 | 0fa7f157 | ths | pdebug("ra%02x t\n", ret);
|
318 | 0fa7f157 | ths | } |
319 | 0fa7f157 | ths | else
|
320 | 0fa7f157 | ths | pdebug("ra%02x\n", ret);
|
321 | 0fa7f157 | ths | } |
322 | 0fa7f157 | ths | break;
|
323 | 5867c88a | ths | case PARA_REG_EPP_DATA:
|
324 | 0fa7f157 | ths | if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR|PARA_CTR_INIT))
|
325 | 0fa7f157 | ths | /* Controls not correct for EPP data cycle, so do nothing */
|
326 | 0fa7f157 | ths | pdebug("re%02x s\n", ret);
|
327 | 0fa7f157 | ths | else {
|
328 | 0fa7f157 | ths | struct ParallelIOArg ioarg = { .buffer = &ret, .count = 1 }; |
329 | 0fa7f157 | ths | if (qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg)) {
|
330 | 0fa7f157 | ths | s->epp_timeout = 1;
|
331 | 0fa7f157 | ths | pdebug("re%02x t\n", ret);
|
332 | 0fa7f157 | ths | } |
333 | 0fa7f157 | ths | else
|
334 | 0fa7f157 | ths | pdebug("re%02x\n", ret);
|
335 | 0fa7f157 | ths | } |
336 | 0fa7f157 | ths | break;
|
337 | 5867c88a | ths | } |
338 | 5867c88a | ths | s->last_read_offset = addr; |
339 | 5867c88a | ths | return ret;
|
340 | 5867c88a | ths | } |
341 | 5867c88a | ths | |
342 | 5867c88a | ths | static uint32_t
|
343 | 5867c88a | ths | parallel_ioport_eppdata_read_hw2(void *opaque, uint32_t addr)
|
344 | 5867c88a | ths | { |
345 | 5867c88a | ths | ParallelState *s = opaque; |
346 | 5867c88a | ths | uint32_t ret; |
347 | 5867c88a | ths | uint16_t eppdata = ~0;
|
348 | 5867c88a | ths | int err;
|
349 | 5867c88a | ths | struct ParallelIOArg ioarg = {
|
350 | 0fa7f157 | ths | .buffer = &eppdata, .count = sizeof(eppdata)
|
351 | 5867c88a | ths | }; |
352 | 5867c88a | ths | if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR|PARA_CTR_INIT)) {
|
353 | 0fa7f157 | ths | /* Controls not correct for EPP data cycle, so do nothing */
|
354 | 0fa7f157 | ths | pdebug("re%04x s\n", eppdata);
|
355 | 0fa7f157 | ths | return eppdata;
|
356 | 5867c88a | ths | } |
357 | 5867c88a | ths | err = qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg); |
358 | 5867c88a | ths | ret = le16_to_cpu(eppdata); |
359 | 5867c88a | ths | |
360 | 5867c88a | ths | if (err) {
|
361 | 0fa7f157 | ths | s->epp_timeout = 1;
|
362 | 0fa7f157 | ths | pdebug("re%04x t\n", ret);
|
363 | 5867c88a | ths | } |
364 | 5867c88a | ths | else
|
365 | 0fa7f157 | ths | pdebug("re%04x\n", ret);
|
366 | 5867c88a | ths | return ret;
|
367 | 5867c88a | ths | } |
368 | 5867c88a | ths | |
369 | 5867c88a | ths | static uint32_t
|
370 | 5867c88a | ths | parallel_ioport_eppdata_read_hw4(void *opaque, uint32_t addr)
|
371 | 5867c88a | ths | { |
372 | 5867c88a | ths | ParallelState *s = opaque; |
373 | 5867c88a | ths | uint32_t ret; |
374 | 5867c88a | ths | uint32_t eppdata = ~0U;
|
375 | 5867c88a | ths | int err;
|
376 | 5867c88a | ths | struct ParallelIOArg ioarg = {
|
377 | 0fa7f157 | ths | .buffer = &eppdata, .count = sizeof(eppdata)
|
378 | 5867c88a | ths | }; |
379 | 5867c88a | ths | if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR|PARA_CTR_INIT)) {
|
380 | 0fa7f157 | ths | /* Controls not correct for EPP data cycle, so do nothing */
|
381 | 0fa7f157 | ths | pdebug("re%08x s\n", eppdata);
|
382 | 0fa7f157 | ths | return eppdata;
|
383 | 5867c88a | ths | } |
384 | 5867c88a | ths | err = qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg); |
385 | 5867c88a | ths | ret = le32_to_cpu(eppdata); |
386 | 5867c88a | ths | |
387 | 5867c88a | ths | if (err) {
|
388 | 0fa7f157 | ths | s->epp_timeout = 1;
|
389 | 0fa7f157 | ths | pdebug("re%08x t\n", ret);
|
390 | 5867c88a | ths | } |
391 | 5867c88a | ths | else
|
392 | 0fa7f157 | ths | pdebug("re%08x\n", ret);
|
393 | 5867c88a | ths | return ret;
|
394 | 5867c88a | ths | } |
395 | 5867c88a | ths | |
396 | 5867c88a | ths | static void parallel_ioport_ecp_write(void *opaque, uint32_t addr, uint32_t val) |
397 | 5867c88a | ths | { |
398 | 5867c88a | ths | addr &= 7;
|
399 | 5867c88a | ths | pdebug("wecp%d=%02x\n", addr, val);
|
400 | 5867c88a | ths | } |
401 | 5867c88a | ths | |
402 | 5867c88a | ths | static uint32_t parallel_ioport_ecp_read(void *opaque, uint32_t addr) |
403 | 5867c88a | ths | { |
404 | 5867c88a | ths | uint8_t ret = 0xff;
|
405 | 5867c88a | ths | addr &= 7;
|
406 | 5867c88a | ths | pdebug("recp%d:%02x\n", addr, ret);
|
407 | 6508fe59 | bellard | return ret;
|
408 | 6508fe59 | bellard | } |
409 | 6508fe59 | bellard | |
410 | d60532ca | ths | static void parallel_reset(ParallelState *s, qemu_irq irq, CharDriverState *chr) |
411 | 6508fe59 | bellard | { |
412 | 5867c88a | ths | s->datar = ~0;
|
413 | 5867c88a | ths | s->dataw = ~0;
|
414 | 6508fe59 | bellard | s->status = PARA_STS_BUSY; |
415 | 6508fe59 | bellard | s->status |= PARA_STS_ACK; |
416 | 6508fe59 | bellard | s->status |= PARA_STS_ONLINE; |
417 | 6508fe59 | bellard | s->status |= PARA_STS_ERROR; |
418 | 52ccc5e0 | balrog | s->status |= PARA_STS_TMOUT; |
419 | 6508fe59 | bellard | s->control = PARA_CTR_SELECT; |
420 | 6508fe59 | bellard | s->control |= PARA_CTR_INIT; |
421 | 52ccc5e0 | balrog | s->control |= 0xc0;
|
422 | 5867c88a | ths | s->irq = irq; |
423 | 5867c88a | ths | s->irq_pending = 0;
|
424 | 5867c88a | ths | s->chr = chr; |
425 | 5867c88a | ths | s->hw_driver = 0;
|
426 | 5867c88a | ths | s->epp_timeout = 0;
|
427 | 5867c88a | ths | s->last_read_offset = ~0U;
|
428 | d60532ca | ths | } |
429 | d60532ca | ths | |
430 | d60532ca | ths | /* If fd is zero, it means that the parallel device uses the console */
|
431 | d60532ca | ths | ParallelState *parallel_init(int base, qemu_irq irq, CharDriverState *chr)
|
432 | d60532ca | ths | { |
433 | d60532ca | ths | ParallelState *s; |
434 | d60532ca | ths | uint8_t dummy; |
435 | d60532ca | ths | |
436 | d60532ca | ths | s = qemu_mallocz(sizeof(ParallelState));
|
437 | d60532ca | ths | if (!s)
|
438 | d60532ca | ths | return NULL; |
439 | d60532ca | ths | parallel_reset(s, irq, chr); |
440 | 6508fe59 | bellard | |
441 | 5867c88a | ths | if (qemu_chr_ioctl(chr, CHR_IOCTL_PP_READ_STATUS, &dummy) == 0) { |
442 | 5867c88a | ths | s->hw_driver = 1;
|
443 | 0fa7f157 | ths | s->status = dummy; |
444 | 5867c88a | ths | } |
445 | 5867c88a | ths | |
446 | 5867c88a | ths | if (s->hw_driver) {
|
447 | 0fa7f157 | ths | register_ioport_write(base, 8, 1, parallel_ioport_write_hw, s); |
448 | 0fa7f157 | ths | register_ioport_read(base, 8, 1, parallel_ioport_read_hw, s); |
449 | 0fa7f157 | ths | register_ioport_write(base+4, 1, 2, parallel_ioport_eppdata_write_hw2, s); |
450 | 0fa7f157 | ths | register_ioport_read(base+4, 1, 2, parallel_ioport_eppdata_read_hw2, s); |
451 | 0fa7f157 | ths | register_ioport_write(base+4, 1, 4, parallel_ioport_eppdata_write_hw4, s); |
452 | 0fa7f157 | ths | register_ioport_read(base+4, 1, 4, parallel_ioport_eppdata_read_hw4, s); |
453 | 0fa7f157 | ths | register_ioport_write(base+0x400, 8, 1, parallel_ioport_ecp_write, s); |
454 | 0fa7f157 | ths | register_ioport_read(base+0x400, 8, 1, parallel_ioport_ecp_read, s); |
455 | 5867c88a | ths | } |
456 | 5867c88a | ths | else {
|
457 | 0fa7f157 | ths | register_ioport_write(base, 8, 1, parallel_ioport_write_sw, s); |
458 | 0fa7f157 | ths | register_ioport_read(base, 8, 1, parallel_ioport_read_sw, s); |
459 | 5867c88a | ths | } |
460 | 6508fe59 | bellard | return s;
|
461 | 6508fe59 | bellard | } |
462 | d60532ca | ths | |
463 | d60532ca | ths | /* Memory mapped interface */
|
464 | 9596ebb7 | pbrook | static uint32_t parallel_mm_readb (void *opaque, target_phys_addr_t addr) |
465 | d60532ca | ths | { |
466 | d60532ca | ths | ParallelState *s = opaque; |
467 | d60532ca | ths | |
468 | d60532ca | ths | return parallel_ioport_read_sw(s, (addr - s->base) >> s->it_shift) & 0xFF; |
469 | d60532ca | ths | } |
470 | d60532ca | ths | |
471 | 9596ebb7 | pbrook | static void parallel_mm_writeb (void *opaque, |
472 | 9596ebb7 | pbrook | target_phys_addr_t addr, uint32_t value) |
473 | d60532ca | ths | { |
474 | d60532ca | ths | ParallelState *s = opaque; |
475 | d60532ca | ths | |
476 | d60532ca | ths | parallel_ioport_write_sw(s, (addr - s->base) >> s->it_shift, value & 0xFF);
|
477 | d60532ca | ths | } |
478 | d60532ca | ths | |
479 | 9596ebb7 | pbrook | static uint32_t parallel_mm_readw (void *opaque, target_phys_addr_t addr) |
480 | d60532ca | ths | { |
481 | d60532ca | ths | ParallelState *s = opaque; |
482 | d60532ca | ths | |
483 | d60532ca | ths | return parallel_ioport_read_sw(s, (addr - s->base) >> s->it_shift) & 0xFFFF; |
484 | d60532ca | ths | } |
485 | d60532ca | ths | |
486 | 9596ebb7 | pbrook | static void parallel_mm_writew (void *opaque, |
487 | 9596ebb7 | pbrook | target_phys_addr_t addr, uint32_t value) |
488 | d60532ca | ths | { |
489 | d60532ca | ths | ParallelState *s = opaque; |
490 | d60532ca | ths | |
491 | d60532ca | ths | parallel_ioport_write_sw(s, (addr - s->base) >> s->it_shift, value & 0xFFFF);
|
492 | d60532ca | ths | } |
493 | d60532ca | ths | |
494 | 9596ebb7 | pbrook | static uint32_t parallel_mm_readl (void *opaque, target_phys_addr_t addr) |
495 | d60532ca | ths | { |
496 | d60532ca | ths | ParallelState *s = opaque; |
497 | d60532ca | ths | |
498 | d60532ca | ths | return parallel_ioport_read_sw(s, (addr - s->base) >> s->it_shift);
|
499 | d60532ca | ths | } |
500 | d60532ca | ths | |
501 | 9596ebb7 | pbrook | static void parallel_mm_writel (void *opaque, |
502 | 9596ebb7 | pbrook | target_phys_addr_t addr, uint32_t value) |
503 | d60532ca | ths | { |
504 | d60532ca | ths | ParallelState *s = opaque; |
505 | d60532ca | ths | |
506 | d60532ca | ths | parallel_ioport_write_sw(s, (addr - s->base) >> s->it_shift, value); |
507 | d60532ca | ths | } |
508 | d60532ca | ths | |
509 | d60532ca | ths | static CPUReadMemoryFunc *parallel_mm_read_sw[] = {
|
510 | d60532ca | ths | ¶llel_mm_readb, |
511 | d60532ca | ths | ¶llel_mm_readw, |
512 | d60532ca | ths | ¶llel_mm_readl, |
513 | d60532ca | ths | }; |
514 | d60532ca | ths | |
515 | d60532ca | ths | static CPUWriteMemoryFunc *parallel_mm_write_sw[] = {
|
516 | d60532ca | ths | ¶llel_mm_writeb, |
517 | d60532ca | ths | ¶llel_mm_writew, |
518 | d60532ca | ths | ¶llel_mm_writel, |
519 | d60532ca | ths | }; |
520 | d60532ca | ths | |
521 | d60532ca | ths | /* If fd is zero, it means that the parallel device uses the console */
|
522 | d60532ca | ths | ParallelState *parallel_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq, CharDriverState *chr)
|
523 | d60532ca | ths | { |
524 | d60532ca | ths | ParallelState *s; |
525 | d60532ca | ths | int io_sw;
|
526 | d60532ca | ths | |
527 | d60532ca | ths | s = qemu_mallocz(sizeof(ParallelState));
|
528 | d60532ca | ths | if (!s)
|
529 | d60532ca | ths | return NULL; |
530 | d60532ca | ths | parallel_reset(s, irq, chr); |
531 | d60532ca | ths | s->base = base; |
532 | d60532ca | ths | s->it_shift = it_shift; |
533 | d60532ca | ths | |
534 | d60532ca | ths | io_sw = cpu_register_io_memory(0, parallel_mm_read_sw, parallel_mm_write_sw, s);
|
535 | d60532ca | ths | cpu_register_physical_memory(base, 8 << it_shift, io_sw);
|
536 | d60532ca | ths | return s;
|
537 | d60532ca | ths | } |