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1 | 80cabfad | bellard | /*
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2 | 80cabfad | bellard | * QEMU PC System Emulator
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3 | 5fafdf24 | ths | *
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4 | 80cabfad | bellard | * Copyright (c) 2003-2004 Fabrice Bellard
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5 | 5fafdf24 | ths | *
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6 | 80cabfad | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | 80cabfad | bellard | * of this software and associated documentation files (the "Software"), to deal
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8 | 80cabfad | bellard | * in the Software without restriction, including without limitation the rights
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9 | 80cabfad | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | 80cabfad | bellard | * copies of the Software, and to permit persons to whom the Software is
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11 | 80cabfad | bellard | * furnished to do so, subject to the following conditions:
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12 | 80cabfad | bellard | *
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13 | 80cabfad | bellard | * The above copyright notice and this permission notice shall be included in
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14 | 80cabfad | bellard | * all copies or substantial portions of the Software.
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15 | 80cabfad | bellard | *
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16 | 80cabfad | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | 80cabfad | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | 80cabfad | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | 80cabfad | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | 80cabfad | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | 80cabfad | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | 80cabfad | bellard | * THE SOFTWARE.
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23 | 80cabfad | bellard | */
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24 | 87ecb68b | pbrook | #include "hw.h" |
25 | 87ecb68b | pbrook | #include "pc.h" |
26 | 87ecb68b | pbrook | #include "fdc.h" |
27 | 87ecb68b | pbrook | #include "pci.h" |
28 | 87ecb68b | pbrook | #include "block.h" |
29 | 87ecb68b | pbrook | #include "sysemu.h" |
30 | 87ecb68b | pbrook | #include "audio/audio.h" |
31 | 87ecb68b | pbrook | #include "net.h" |
32 | 87ecb68b | pbrook | #include "smbus.h" |
33 | 87ecb68b | pbrook | #include "boards.h" |
34 | 80cabfad | bellard | |
35 | b41a2cd1 | bellard | /* output Bochs bios info messages */
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36 | b41a2cd1 | bellard | //#define DEBUG_BIOS
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37 | b41a2cd1 | bellard | |
38 | 80cabfad | bellard | #define BIOS_FILENAME "bios.bin" |
39 | 80cabfad | bellard | #define VGABIOS_FILENAME "vgabios.bin" |
40 | de9258a8 | bellard | #define VGABIOS_CIRRUS_FILENAME "vgabios-cirrus.bin" |
41 | 80cabfad | bellard | |
42 | 7fb4fdcf | balrog | #define PC_MAX_BIOS_SIZE (4 * 1024 * 1024) |
43 | 7fb4fdcf | balrog | |
44 | a80274c3 | pbrook | /* Leave a chunk of memory at the top of RAM for the BIOS ACPI tables. */
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45 | a80274c3 | pbrook | #define ACPI_DATA_SIZE 0x10000 |
46 | 80cabfad | bellard | |
47 | e4bcb14c | ths | #define MAX_IDE_BUS 2 |
48 | e4bcb14c | ths | |
49 | baca51fa | bellard | static fdctrl_t *floppy_controller;
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50 | b0a21b53 | bellard | static RTCState *rtc_state;
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51 | ec844b96 | bellard | static PITState *pit;
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52 | d592d303 | bellard | static IOAPICState *ioapic;
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53 | a5954d5c | bellard | static PCIDevice *i440fx_state;
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54 | 80cabfad | bellard | |
55 | b41a2cd1 | bellard | static void ioport80_write(void *opaque, uint32_t addr, uint32_t data) |
56 | 80cabfad | bellard | { |
57 | 80cabfad | bellard | } |
58 | 80cabfad | bellard | |
59 | f929aad6 | bellard | /* MSDOS compatibility mode FPU exception support */
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60 | d537cf6c | pbrook | static qemu_irq ferr_irq;
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61 | f929aad6 | bellard | /* XXX: add IGNNE support */
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62 | f929aad6 | bellard | void cpu_set_ferr(CPUX86State *s)
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63 | f929aad6 | bellard | { |
64 | d537cf6c | pbrook | qemu_irq_raise(ferr_irq); |
65 | f929aad6 | bellard | } |
66 | f929aad6 | bellard | |
67 | f929aad6 | bellard | static void ioportF0_write(void *opaque, uint32_t addr, uint32_t data) |
68 | f929aad6 | bellard | { |
69 | d537cf6c | pbrook | qemu_irq_lower(ferr_irq); |
70 | f929aad6 | bellard | } |
71 | f929aad6 | bellard | |
72 | 28ab0e2e | bellard | /* TSC handling */
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73 | 28ab0e2e | bellard | uint64_t cpu_get_tsc(CPUX86State *env) |
74 | 28ab0e2e | bellard | { |
75 | 1dce7c3c | bellard | /* Note: when using kqemu, it is more logical to return the host TSC
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76 | 1dce7c3c | bellard | because kqemu does not trap the RDTSC instruction for
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77 | 1dce7c3c | bellard | performance reasons */
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78 | 1dce7c3c | bellard | #if USE_KQEMU
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79 | 1dce7c3c | bellard | if (env->kqemu_enabled) {
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80 | 1dce7c3c | bellard | return cpu_get_real_ticks();
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81 | 5fafdf24 | ths | } else
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82 | 1dce7c3c | bellard | #endif
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83 | 1dce7c3c | bellard | { |
84 | 1dce7c3c | bellard | return cpu_get_ticks();
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85 | 1dce7c3c | bellard | } |
86 | 28ab0e2e | bellard | } |
87 | 28ab0e2e | bellard | |
88 | a5954d5c | bellard | /* SMM support */
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89 | a5954d5c | bellard | void cpu_smm_update(CPUState *env)
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90 | a5954d5c | bellard | { |
91 | a5954d5c | bellard | if (i440fx_state && env == first_cpu)
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92 | a5954d5c | bellard | i440fx_set_smm(i440fx_state, (env->hflags >> HF_SMM_SHIFT) & 1);
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93 | a5954d5c | bellard | } |
94 | a5954d5c | bellard | |
95 | a5954d5c | bellard | |
96 | 3de388f6 | bellard | /* IRQ handling */
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97 | 3de388f6 | bellard | int cpu_get_pic_interrupt(CPUState *env)
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98 | 3de388f6 | bellard | { |
99 | 3de388f6 | bellard | int intno;
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100 | 3de388f6 | bellard | |
101 | 3de388f6 | bellard | intno = apic_get_interrupt(env); |
102 | 3de388f6 | bellard | if (intno >= 0) { |
103 | 3de388f6 | bellard | /* set irq request if a PIC irq is still pending */
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104 | 3de388f6 | bellard | /* XXX: improve that */
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105 | 5fafdf24 | ths | pic_update_irq(isa_pic); |
106 | 3de388f6 | bellard | return intno;
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107 | 3de388f6 | bellard | } |
108 | 3de388f6 | bellard | /* read the irq from the PIC */
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109 | 0e21e12b | ths | if (!apic_accept_pic_intr(env))
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110 | 0e21e12b | ths | return -1; |
111 | 0e21e12b | ths | |
112 | 3de388f6 | bellard | intno = pic_read_irq(isa_pic); |
113 | 3de388f6 | bellard | return intno;
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114 | 3de388f6 | bellard | } |
115 | 3de388f6 | bellard | |
116 | d537cf6c | pbrook | static void pic_irq_request(void *opaque, int irq, int level) |
117 | 3de388f6 | bellard | { |
118 | a5b38b51 | aurel32 | CPUState *env = first_cpu; |
119 | a5b38b51 | aurel32 | |
120 | a5b38b51 | aurel32 | if (!level)
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121 | a5b38b51 | aurel32 | return;
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122 | a5b38b51 | aurel32 | |
123 | a5b38b51 | aurel32 | while (env) {
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124 | a5b38b51 | aurel32 | if (apic_accept_pic_intr(env))
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125 | a5b38b51 | aurel32 | apic_local_deliver(env, APIC_LINT0); |
126 | a5b38b51 | aurel32 | env = env->next_cpu; |
127 | a5b38b51 | aurel32 | } |
128 | 3de388f6 | bellard | } |
129 | 3de388f6 | bellard | |
130 | b0a21b53 | bellard | /* PC cmos mappings */
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131 | b0a21b53 | bellard | |
132 | 80cabfad | bellard | #define REG_EQUIPMENT_BYTE 0x14 |
133 | 80cabfad | bellard | |
134 | 777428f2 | bellard | static int cmos_get_fd_drive_type(int fd0) |
135 | 777428f2 | bellard | { |
136 | 777428f2 | bellard | int val;
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137 | 777428f2 | bellard | |
138 | 777428f2 | bellard | switch (fd0) {
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139 | 777428f2 | bellard | case 0: |
140 | 777428f2 | bellard | /* 1.44 Mb 3"5 drive */
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141 | 777428f2 | bellard | val = 4;
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142 | 777428f2 | bellard | break;
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143 | 777428f2 | bellard | case 1: |
144 | 777428f2 | bellard | /* 2.88 Mb 3"5 drive */
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145 | 777428f2 | bellard | val = 5;
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146 | 777428f2 | bellard | break;
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147 | 777428f2 | bellard | case 2: |
148 | 777428f2 | bellard | /* 1.2 Mb 5"5 drive */
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149 | 777428f2 | bellard | val = 2;
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150 | 777428f2 | bellard | break;
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151 | 777428f2 | bellard | default:
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152 | 777428f2 | bellard | val = 0;
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153 | 777428f2 | bellard | break;
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154 | 777428f2 | bellard | } |
155 | 777428f2 | bellard | return val;
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156 | 777428f2 | bellard | } |
157 | 777428f2 | bellard | |
158 | 5fafdf24 | ths | static void cmos_init_hd(int type_ofs, int info_ofs, BlockDriverState *hd) |
159 | ba6c2377 | bellard | { |
160 | ba6c2377 | bellard | RTCState *s = rtc_state; |
161 | ba6c2377 | bellard | int cylinders, heads, sectors;
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162 | ba6c2377 | bellard | bdrv_get_geometry_hint(hd, &cylinders, &heads, §ors); |
163 | ba6c2377 | bellard | rtc_set_memory(s, type_ofs, 47);
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164 | ba6c2377 | bellard | rtc_set_memory(s, info_ofs, cylinders); |
165 | ba6c2377 | bellard | rtc_set_memory(s, info_ofs + 1, cylinders >> 8); |
166 | ba6c2377 | bellard | rtc_set_memory(s, info_ofs + 2, heads);
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167 | ba6c2377 | bellard | rtc_set_memory(s, info_ofs + 3, 0xff); |
168 | ba6c2377 | bellard | rtc_set_memory(s, info_ofs + 4, 0xff); |
169 | ba6c2377 | bellard | rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3)); |
170 | ba6c2377 | bellard | rtc_set_memory(s, info_ofs + 6, cylinders);
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171 | ba6c2377 | bellard | rtc_set_memory(s, info_ofs + 7, cylinders >> 8); |
172 | ba6c2377 | bellard | rtc_set_memory(s, info_ofs + 8, sectors);
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173 | ba6c2377 | bellard | } |
174 | ba6c2377 | bellard | |
175 | 6ac0e82d | balrog | /* convert boot_device letter to something recognizable by the bios */
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176 | 6ac0e82d | balrog | static int boot_device2nibble(char boot_device) |
177 | 6ac0e82d | balrog | { |
178 | 6ac0e82d | balrog | switch(boot_device) {
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179 | 6ac0e82d | balrog | case 'a': |
180 | 6ac0e82d | balrog | case 'b': |
181 | 6ac0e82d | balrog | return 0x01; /* floppy boot */ |
182 | 6ac0e82d | balrog | case 'c': |
183 | 6ac0e82d | balrog | return 0x02; /* hard drive boot */ |
184 | 6ac0e82d | balrog | case 'd': |
185 | 6ac0e82d | balrog | return 0x03; /* CD-ROM boot */ |
186 | 6ac0e82d | balrog | case 'n': |
187 | 6ac0e82d | balrog | return 0x04; /* Network boot */ |
188 | 6ac0e82d | balrog | } |
189 | 6ac0e82d | balrog | return 0; |
190 | 6ac0e82d | balrog | } |
191 | 6ac0e82d | balrog | |
192 | ba6c2377 | bellard | /* hd_table must contain 4 block drivers */
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193 | 00f82b8a | aurel32 | static void cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size, |
194 | 00f82b8a | aurel32 | const char *boot_device, BlockDriverState **hd_table) |
195 | 80cabfad | bellard | { |
196 | b0a21b53 | bellard | RTCState *s = rtc_state; |
197 | 28c5af54 | j_mayer | int nbds, bds[3] = { 0, }; |
198 | 80cabfad | bellard | int val;
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199 | b41a2cd1 | bellard | int fd0, fd1, nb;
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200 | ba6c2377 | bellard | int i;
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201 | b0a21b53 | bellard | |
202 | b0a21b53 | bellard | /* various important CMOS locations needed by PC/Bochs bios */
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203 | 80cabfad | bellard | |
204 | 80cabfad | bellard | /* memory size */
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205 | 333190eb | bellard | val = 640; /* base memory in K */ |
206 | 333190eb | bellard | rtc_set_memory(s, 0x15, val);
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207 | 333190eb | bellard | rtc_set_memory(s, 0x16, val >> 8); |
208 | 333190eb | bellard | |
209 | 80cabfad | bellard | val = (ram_size / 1024) - 1024; |
210 | 80cabfad | bellard | if (val > 65535) |
211 | 80cabfad | bellard | val = 65535;
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212 | b0a21b53 | bellard | rtc_set_memory(s, 0x17, val);
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213 | b0a21b53 | bellard | rtc_set_memory(s, 0x18, val >> 8); |
214 | b0a21b53 | bellard | rtc_set_memory(s, 0x30, val);
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215 | b0a21b53 | bellard | rtc_set_memory(s, 0x31, val >> 8); |
216 | 80cabfad | bellard | |
217 | 00f82b8a | aurel32 | if (above_4g_mem_size) {
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218 | 00f82b8a | aurel32 | rtc_set_memory(s, 0x5b, (unsigned int)above_4g_mem_size >> 16); |
219 | 00f82b8a | aurel32 | rtc_set_memory(s, 0x5c, (unsigned int)above_4g_mem_size >> 24); |
220 | 00f82b8a | aurel32 | rtc_set_memory(s, 0x5d, (uint64_t)above_4g_mem_size >> 32); |
221 | 00f82b8a | aurel32 | } |
222 | 00f82b8a | aurel32 | |
223 | 9da98861 | bellard | if (ram_size > (16 * 1024 * 1024)) |
224 | 9da98861 | bellard | val = (ram_size / 65536) - ((16 * 1024 * 1024) / 65536); |
225 | 9da98861 | bellard | else
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226 | 9da98861 | bellard | val = 0;
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227 | 80cabfad | bellard | if (val > 65535) |
228 | 80cabfad | bellard | val = 65535;
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229 | b0a21b53 | bellard | rtc_set_memory(s, 0x34, val);
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230 | b0a21b53 | bellard | rtc_set_memory(s, 0x35, val >> 8); |
231 | 3b46e624 | ths | |
232 | 298e01b6 | aurel32 | /* set the number of CPU */
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233 | 298e01b6 | aurel32 | rtc_set_memory(s, 0x5f, smp_cpus - 1); |
234 | 298e01b6 | aurel32 | |
235 | 6ac0e82d | balrog | /* set boot devices, and disable floppy signature check if requested */
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236 | 28c5af54 | j_mayer | #define PC_MAX_BOOT_DEVICES 3 |
237 | 28c5af54 | j_mayer | nbds = strlen(boot_device); |
238 | 28c5af54 | j_mayer | if (nbds > PC_MAX_BOOT_DEVICES) {
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239 | 28c5af54 | j_mayer | fprintf(stderr, "Too many boot devices for PC\n");
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240 | 28c5af54 | j_mayer | exit(1);
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241 | 28c5af54 | j_mayer | } |
242 | 28c5af54 | j_mayer | for (i = 0; i < nbds; i++) { |
243 | 28c5af54 | j_mayer | bds[i] = boot_device2nibble(boot_device[i]); |
244 | 28c5af54 | j_mayer | if (bds[i] == 0) { |
245 | 28c5af54 | j_mayer | fprintf(stderr, "Invalid boot device for PC: '%c'\n",
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246 | 28c5af54 | j_mayer | boot_device[i]); |
247 | 28c5af54 | j_mayer | exit(1);
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248 | 28c5af54 | j_mayer | } |
249 | 28c5af54 | j_mayer | } |
250 | 28c5af54 | j_mayer | rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]); |
251 | 28c5af54 | j_mayer | rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1)); |
252 | 80cabfad | bellard | |
253 | b41a2cd1 | bellard | /* floppy type */
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254 | b41a2cd1 | bellard | |
255 | baca51fa | bellard | fd0 = fdctrl_get_drive_type(floppy_controller, 0);
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256 | baca51fa | bellard | fd1 = fdctrl_get_drive_type(floppy_controller, 1);
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257 | 80cabfad | bellard | |
258 | 777428f2 | bellard | val = (cmos_get_fd_drive_type(fd0) << 4) | cmos_get_fd_drive_type(fd1);
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259 | b0a21b53 | bellard | rtc_set_memory(s, 0x10, val);
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260 | 3b46e624 | ths | |
261 | b0a21b53 | bellard | val = 0;
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262 | b41a2cd1 | bellard | nb = 0;
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263 | 80cabfad | bellard | if (fd0 < 3) |
264 | 80cabfad | bellard | nb++; |
265 | 80cabfad | bellard | if (fd1 < 3) |
266 | 80cabfad | bellard | nb++; |
267 | 80cabfad | bellard | switch (nb) {
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268 | 80cabfad | bellard | case 0: |
269 | 80cabfad | bellard | break;
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270 | 80cabfad | bellard | case 1: |
271 | b0a21b53 | bellard | val |= 0x01; /* 1 drive, ready for boot */ |
272 | 80cabfad | bellard | break;
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273 | 80cabfad | bellard | case 2: |
274 | b0a21b53 | bellard | val |= 0x41; /* 2 drives, ready for boot */ |
275 | 80cabfad | bellard | break;
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276 | 80cabfad | bellard | } |
277 | b0a21b53 | bellard | val |= 0x02; /* FPU is there */ |
278 | b0a21b53 | bellard | val |= 0x04; /* PS/2 mouse installed */ |
279 | b0a21b53 | bellard | rtc_set_memory(s, REG_EQUIPMENT_BYTE, val); |
280 | b0a21b53 | bellard | |
281 | ba6c2377 | bellard | /* hard drives */
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282 | ba6c2377 | bellard | |
283 | ba6c2377 | bellard | rtc_set_memory(s, 0x12, (hd_table[0] ? 0xf0 : 0) | (hd_table[1] ? 0x0f : 0)); |
284 | ba6c2377 | bellard | if (hd_table[0]) |
285 | ba6c2377 | bellard | cmos_init_hd(0x19, 0x1b, hd_table[0]); |
286 | 5fafdf24 | ths | if (hd_table[1]) |
287 | ba6c2377 | bellard | cmos_init_hd(0x1a, 0x24, hd_table[1]); |
288 | ba6c2377 | bellard | |
289 | ba6c2377 | bellard | val = 0;
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290 | 40b6ecc6 | bellard | for (i = 0; i < 4; i++) { |
291 | ba6c2377 | bellard | if (hd_table[i]) {
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292 | 46d4767d | bellard | int cylinders, heads, sectors, translation;
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293 | 46d4767d | bellard | /* NOTE: bdrv_get_geometry_hint() returns the physical
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294 | 46d4767d | bellard | geometry. It is always such that: 1 <= sects <= 63, 1
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295 | 46d4767d | bellard | <= heads <= 16, 1 <= cylinders <= 16383. The BIOS
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296 | 46d4767d | bellard | geometry can be different if a translation is done. */
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297 | 46d4767d | bellard | translation = bdrv_get_translation_hint(hd_table[i]); |
298 | 46d4767d | bellard | if (translation == BIOS_ATA_TRANSLATION_AUTO) {
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299 | 46d4767d | bellard | bdrv_get_geometry_hint(hd_table[i], &cylinders, &heads, §ors); |
300 | 46d4767d | bellard | if (cylinders <= 1024 && heads <= 16 && sectors <= 63) { |
301 | 46d4767d | bellard | /* No translation. */
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302 | 46d4767d | bellard | translation = 0;
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303 | 46d4767d | bellard | } else {
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304 | 46d4767d | bellard | /* LBA translation. */
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305 | 46d4767d | bellard | translation = 1;
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306 | 46d4767d | bellard | } |
307 | 40b6ecc6 | bellard | } else {
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308 | 46d4767d | bellard | translation--; |
309 | ba6c2377 | bellard | } |
310 | ba6c2377 | bellard | val |= translation << (i * 2);
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311 | ba6c2377 | bellard | } |
312 | 40b6ecc6 | bellard | } |
313 | ba6c2377 | bellard | rtc_set_memory(s, 0x39, val);
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314 | 80cabfad | bellard | } |
315 | 80cabfad | bellard | |
316 | 59b8ad81 | bellard | void ioport_set_a20(int enable) |
317 | 59b8ad81 | bellard | { |
318 | 59b8ad81 | bellard | /* XXX: send to all CPUs ? */
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319 | 59b8ad81 | bellard | cpu_x86_set_a20(first_cpu, enable); |
320 | 59b8ad81 | bellard | } |
321 | 59b8ad81 | bellard | |
322 | 59b8ad81 | bellard | int ioport_get_a20(void) |
323 | 59b8ad81 | bellard | { |
324 | 59b8ad81 | bellard | return ((first_cpu->a20_mask >> 20) & 1); |
325 | 59b8ad81 | bellard | } |
326 | 59b8ad81 | bellard | |
327 | e1a23744 | bellard | static void ioport92_write(void *opaque, uint32_t addr, uint32_t val) |
328 | e1a23744 | bellard | { |
329 | 59b8ad81 | bellard | ioport_set_a20((val >> 1) & 1); |
330 | e1a23744 | bellard | /* XXX: bit 0 is fast reset */
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331 | e1a23744 | bellard | } |
332 | e1a23744 | bellard | |
333 | e1a23744 | bellard | static uint32_t ioport92_read(void *opaque, uint32_t addr) |
334 | e1a23744 | bellard | { |
335 | 59b8ad81 | bellard | return ioport_get_a20() << 1; |
336 | e1a23744 | bellard | } |
337 | e1a23744 | bellard | |
338 | 80cabfad | bellard | /***********************************************************/
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339 | 80cabfad | bellard | /* Bochs BIOS debug ports */
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340 | 80cabfad | bellard | |
341 | 9596ebb7 | pbrook | static void bochs_bios_write(void *opaque, uint32_t addr, uint32_t val) |
342 | 80cabfad | bellard | { |
343 | a2f659ee | bellard | static const char shutdown_str[8] = "Shutdown"; |
344 | a2f659ee | bellard | static int shutdown_index = 0; |
345 | 3b46e624 | ths | |
346 | 80cabfad | bellard | switch(addr) {
|
347 | 80cabfad | bellard | /* Bochs BIOS messages */
|
348 | 80cabfad | bellard | case 0x400: |
349 | 80cabfad | bellard | case 0x401: |
350 | 80cabfad | bellard | fprintf(stderr, "BIOS panic at rombios.c, line %d\n", val);
|
351 | 80cabfad | bellard | exit(1);
|
352 | 80cabfad | bellard | case 0x402: |
353 | 80cabfad | bellard | case 0x403: |
354 | 80cabfad | bellard | #ifdef DEBUG_BIOS
|
355 | 80cabfad | bellard | fprintf(stderr, "%c", val);
|
356 | 80cabfad | bellard | #endif
|
357 | 80cabfad | bellard | break;
|
358 | a2f659ee | bellard | case 0x8900: |
359 | a2f659ee | bellard | /* same as Bochs power off */
|
360 | a2f659ee | bellard | if (val == shutdown_str[shutdown_index]) {
|
361 | a2f659ee | bellard | shutdown_index++; |
362 | a2f659ee | bellard | if (shutdown_index == 8) { |
363 | a2f659ee | bellard | shutdown_index = 0;
|
364 | a2f659ee | bellard | qemu_system_shutdown_request(); |
365 | a2f659ee | bellard | } |
366 | a2f659ee | bellard | } else {
|
367 | a2f659ee | bellard | shutdown_index = 0;
|
368 | a2f659ee | bellard | } |
369 | a2f659ee | bellard | break;
|
370 | 80cabfad | bellard | |
371 | 80cabfad | bellard | /* LGPL'ed VGA BIOS messages */
|
372 | 80cabfad | bellard | case 0x501: |
373 | 80cabfad | bellard | case 0x502: |
374 | 80cabfad | bellard | fprintf(stderr, "VGA BIOS panic, line %d\n", val);
|
375 | 80cabfad | bellard | exit(1);
|
376 | 80cabfad | bellard | case 0x500: |
377 | 80cabfad | bellard | case 0x503: |
378 | 80cabfad | bellard | #ifdef DEBUG_BIOS
|
379 | 80cabfad | bellard | fprintf(stderr, "%c", val);
|
380 | 80cabfad | bellard | #endif
|
381 | 80cabfad | bellard | break;
|
382 | 80cabfad | bellard | } |
383 | 80cabfad | bellard | } |
384 | 80cabfad | bellard | |
385 | 9596ebb7 | pbrook | static void bochs_bios_init(void) |
386 | 80cabfad | bellard | { |
387 | b41a2cd1 | bellard | register_ioport_write(0x400, 1, 2, bochs_bios_write, NULL); |
388 | b41a2cd1 | bellard | register_ioport_write(0x401, 1, 2, bochs_bios_write, NULL); |
389 | b41a2cd1 | bellard | register_ioport_write(0x402, 1, 1, bochs_bios_write, NULL); |
390 | b41a2cd1 | bellard | register_ioport_write(0x403, 1, 1, bochs_bios_write, NULL); |
391 | a2f659ee | bellard | register_ioport_write(0x8900, 1, 1, bochs_bios_write, NULL); |
392 | b41a2cd1 | bellard | |
393 | b41a2cd1 | bellard | register_ioport_write(0x501, 1, 2, bochs_bios_write, NULL); |
394 | b41a2cd1 | bellard | register_ioport_write(0x502, 1, 2, bochs_bios_write, NULL); |
395 | b41a2cd1 | bellard | register_ioport_write(0x500, 1, 1, bochs_bios_write, NULL); |
396 | b41a2cd1 | bellard | register_ioport_write(0x503, 1, 1, bochs_bios_write, NULL); |
397 | 80cabfad | bellard | } |
398 | 80cabfad | bellard | |
399 | 642a4f96 | ths | /* Generate an initial boot sector which sets state and jump to
|
400 | 642a4f96 | ths | a specified vector */
|
401 | 3f6c925f | balrog | static void generate_bootsect(uint32_t gpr[8], uint16_t segs[6], uint16_t ip) |
402 | 642a4f96 | ths | { |
403 | 642a4f96 | ths | uint8_t bootsect[512], *p;
|
404 | 642a4f96 | ths | int i;
|
405 | e4bcb14c | ths | int hda;
|
406 | 642a4f96 | ths | |
407 | e4bcb14c | ths | hda = drive_get_index(IF_IDE, 0, 0); |
408 | e4bcb14c | ths | if (hda == -1) { |
409 | 642a4f96 | ths | fprintf(stderr, "A disk image must be given for 'hda' when booting "
|
410 | 642a4f96 | ths | "a Linux kernel\n");
|
411 | 642a4f96 | ths | exit(1);
|
412 | 642a4f96 | ths | } |
413 | 642a4f96 | ths | |
414 | 642a4f96 | ths | memset(bootsect, 0, sizeof(bootsect)); |
415 | 642a4f96 | ths | |
416 | 642a4f96 | ths | /* Copy the MSDOS partition table if possible */
|
417 | e4bcb14c | ths | bdrv_read(drives_table[hda].bdrv, 0, bootsect, 1); |
418 | 642a4f96 | ths | |
419 | 642a4f96 | ths | /* Make sure we have a partition signature */
|
420 | 642a4f96 | ths | bootsect[510] = 0x55; |
421 | 642a4f96 | ths | bootsect[511] = 0xaa; |
422 | 642a4f96 | ths | |
423 | 642a4f96 | ths | /* Actual code */
|
424 | 642a4f96 | ths | p = bootsect; |
425 | 642a4f96 | ths | *p++ = 0xfa; /* CLI */ |
426 | 642a4f96 | ths | *p++ = 0xfc; /* CLD */ |
427 | 642a4f96 | ths | |
428 | 642a4f96 | ths | for (i = 0; i < 6; i++) { |
429 | 642a4f96 | ths | if (i == 1) /* Skip CS */ |
430 | 642a4f96 | ths | continue;
|
431 | 642a4f96 | ths | |
432 | 642a4f96 | ths | *p++ = 0xb8; /* MOV AX,imm16 */ |
433 | 642a4f96 | ths | *p++ = segs[i]; |
434 | 642a4f96 | ths | *p++ = segs[i] >> 8;
|
435 | 642a4f96 | ths | *p++ = 0x8e; /* MOV <seg>,AX */ |
436 | 642a4f96 | ths | *p++ = 0xc0 + (i << 3); |
437 | 642a4f96 | ths | } |
438 | 642a4f96 | ths | |
439 | 642a4f96 | ths | for (i = 0; i < 8; i++) { |
440 | 642a4f96 | ths | *p++ = 0x66; /* 32-bit operand size */ |
441 | 642a4f96 | ths | *p++ = 0xb8 + i; /* MOV <reg>,imm32 */ |
442 | 642a4f96 | ths | *p++ = gpr[i]; |
443 | 642a4f96 | ths | *p++ = gpr[i] >> 8;
|
444 | 642a4f96 | ths | *p++ = gpr[i] >> 16;
|
445 | 642a4f96 | ths | *p++ = gpr[i] >> 24;
|
446 | 642a4f96 | ths | } |
447 | 642a4f96 | ths | |
448 | 642a4f96 | ths | *p++ = 0xea; /* JMP FAR */ |
449 | 642a4f96 | ths | *p++ = ip; /* IP */
|
450 | 642a4f96 | ths | *p++ = ip >> 8;
|
451 | 642a4f96 | ths | *p++ = segs[1]; /* CS */ |
452 | 642a4f96 | ths | *p++ = segs[1] >> 8; |
453 | 642a4f96 | ths | |
454 | e4bcb14c | ths | bdrv_set_boot_sector(drives_table[hda].bdrv, bootsect, sizeof(bootsect));
|
455 | 642a4f96 | ths | } |
456 | 80cabfad | bellard | |
457 | 642a4f96 | ths | static long get_file_size(FILE *f) |
458 | 642a4f96 | ths | { |
459 | 642a4f96 | ths | long where, size;
|
460 | 642a4f96 | ths | |
461 | 642a4f96 | ths | /* XXX: on Unix systems, using fstat() probably makes more sense */
|
462 | 642a4f96 | ths | |
463 | 642a4f96 | ths | where = ftell(f); |
464 | 642a4f96 | ths | fseek(f, 0, SEEK_END);
|
465 | 642a4f96 | ths | size = ftell(f); |
466 | 642a4f96 | ths | fseek(f, where, SEEK_SET); |
467 | 642a4f96 | ths | |
468 | 642a4f96 | ths | return size;
|
469 | 642a4f96 | ths | } |
470 | 642a4f96 | ths | |
471 | 642a4f96 | ths | static void load_linux(const char *kernel_filename, |
472 | 642a4f96 | ths | const char *initrd_filename, |
473 | 642a4f96 | ths | const char *kernel_cmdline) |
474 | 642a4f96 | ths | { |
475 | 642a4f96 | ths | uint16_t protocol; |
476 | 642a4f96 | ths | uint32_t gpr[8];
|
477 | 642a4f96 | ths | uint16_t seg[6];
|
478 | 642a4f96 | ths | uint16_t real_seg; |
479 | 642a4f96 | ths | int setup_size, kernel_size, initrd_size, cmdline_size;
|
480 | 642a4f96 | ths | uint32_t initrd_max; |
481 | 642a4f96 | ths | uint8_t header[1024];
|
482 | 642a4f96 | ths | uint8_t *real_addr, *prot_addr, *cmdline_addr, *initrd_addr; |
483 | 642a4f96 | ths | FILE *f, *fi; |
484 | 642a4f96 | ths | |
485 | 642a4f96 | ths | /* Align to 16 bytes as a paranoia measure */
|
486 | 642a4f96 | ths | cmdline_size = (strlen(kernel_cmdline)+16) & ~15; |
487 | 642a4f96 | ths | |
488 | 642a4f96 | ths | /* load the kernel header */
|
489 | 642a4f96 | ths | f = fopen(kernel_filename, "rb");
|
490 | 642a4f96 | ths | if (!f || !(kernel_size = get_file_size(f)) ||
|
491 | 642a4f96 | ths | fread(header, 1, 1024, f) != 1024) { |
492 | 642a4f96 | ths | fprintf(stderr, "qemu: could not load kernel '%s'\n",
|
493 | 642a4f96 | ths | kernel_filename); |
494 | 642a4f96 | ths | exit(1);
|
495 | 642a4f96 | ths | } |
496 | 642a4f96 | ths | |
497 | 642a4f96 | ths | /* kernel protocol version */
|
498 | bc4edd79 | bellard | #if 0
|
499 | 642a4f96 | ths | fprintf(stderr, "header magic: %#x\n", ldl_p(header+0x202));
|
500 | bc4edd79 | bellard | #endif
|
501 | 642a4f96 | ths | if (ldl_p(header+0x202) == 0x53726448) |
502 | 642a4f96 | ths | protocol = lduw_p(header+0x206);
|
503 | 642a4f96 | ths | else
|
504 | 642a4f96 | ths | protocol = 0;
|
505 | 642a4f96 | ths | |
506 | 642a4f96 | ths | if (protocol < 0x200 || !(header[0x211] & 0x01)) { |
507 | 642a4f96 | ths | /* Low kernel */
|
508 | 642a4f96 | ths | real_addr = phys_ram_base + 0x90000;
|
509 | 642a4f96 | ths | cmdline_addr = phys_ram_base + 0x9a000 - cmdline_size;
|
510 | 642a4f96 | ths | prot_addr = phys_ram_base + 0x10000;
|
511 | 642a4f96 | ths | } else if (protocol < 0x202) { |
512 | 642a4f96 | ths | /* High but ancient kernel */
|
513 | 642a4f96 | ths | real_addr = phys_ram_base + 0x90000;
|
514 | 642a4f96 | ths | cmdline_addr = phys_ram_base + 0x9a000 - cmdline_size;
|
515 | 642a4f96 | ths | prot_addr = phys_ram_base + 0x100000;
|
516 | 642a4f96 | ths | } else {
|
517 | 642a4f96 | ths | /* High and recent kernel */
|
518 | 642a4f96 | ths | real_addr = phys_ram_base + 0x10000;
|
519 | 642a4f96 | ths | cmdline_addr = phys_ram_base + 0x20000;
|
520 | 642a4f96 | ths | prot_addr = phys_ram_base + 0x100000;
|
521 | 642a4f96 | ths | } |
522 | 642a4f96 | ths | |
523 | bc4edd79 | bellard | #if 0
|
524 | 642a4f96 | ths | fprintf(stderr,
|
525 | 642a4f96 | ths | "qemu: real_addr = %#zx\n"
|
526 | 642a4f96 | ths | "qemu: cmdline_addr = %#zx\n"
|
527 | 642a4f96 | ths | "qemu: prot_addr = %#zx\n",
|
528 | 642a4f96 | ths | real_addr-phys_ram_base,
|
529 | 642a4f96 | ths | cmdline_addr-phys_ram_base,
|
530 | 642a4f96 | ths | prot_addr-phys_ram_base);
|
531 | bc4edd79 | bellard | #endif
|
532 | 642a4f96 | ths | |
533 | 642a4f96 | ths | /* highest address for loading the initrd */
|
534 | 642a4f96 | ths | if (protocol >= 0x203) |
535 | 642a4f96 | ths | initrd_max = ldl_p(header+0x22c);
|
536 | 642a4f96 | ths | else
|
537 | 642a4f96 | ths | initrd_max = 0x37ffffff;
|
538 | 642a4f96 | ths | |
539 | 642a4f96 | ths | if (initrd_max >= ram_size-ACPI_DATA_SIZE)
|
540 | 642a4f96 | ths | initrd_max = ram_size-ACPI_DATA_SIZE-1;
|
541 | 642a4f96 | ths | |
542 | 642a4f96 | ths | /* kernel command line */
|
543 | ffe8ab83 | ths | pstrcpy((char*)cmdline_addr, 4096, kernel_cmdline); |
544 | 642a4f96 | ths | |
545 | 642a4f96 | ths | if (protocol >= 0x202) { |
546 | 642a4f96 | ths | stl_p(header+0x228, cmdline_addr-phys_ram_base);
|
547 | 642a4f96 | ths | } else {
|
548 | 642a4f96 | ths | stw_p(header+0x20, 0xA33F); |
549 | 642a4f96 | ths | stw_p(header+0x22, cmdline_addr-real_addr);
|
550 | 642a4f96 | ths | } |
551 | 642a4f96 | ths | |
552 | 642a4f96 | ths | /* loader type */
|
553 | 642a4f96 | ths | /* High nybble = B reserved for Qemu; low nybble is revision number.
|
554 | 642a4f96 | ths | If this code is substantially changed, you may want to consider
|
555 | 642a4f96 | ths | incrementing the revision. */
|
556 | 642a4f96 | ths | if (protocol >= 0x200) |
557 | 642a4f96 | ths | header[0x210] = 0xB0; |
558 | 642a4f96 | ths | |
559 | 642a4f96 | ths | /* heap */
|
560 | 642a4f96 | ths | if (protocol >= 0x201) { |
561 | 642a4f96 | ths | header[0x211] |= 0x80; /* CAN_USE_HEAP */ |
562 | 642a4f96 | ths | stw_p(header+0x224, cmdline_addr-real_addr-0x200); |
563 | 642a4f96 | ths | } |
564 | 642a4f96 | ths | |
565 | 642a4f96 | ths | /* load initrd */
|
566 | 642a4f96 | ths | if (initrd_filename) {
|
567 | 642a4f96 | ths | if (protocol < 0x200) { |
568 | 642a4f96 | ths | fprintf(stderr, "qemu: linux kernel too old to load a ram disk\n");
|
569 | 642a4f96 | ths | exit(1);
|
570 | 642a4f96 | ths | } |
571 | 642a4f96 | ths | |
572 | 642a4f96 | ths | fi = fopen(initrd_filename, "rb");
|
573 | 642a4f96 | ths | if (!fi) {
|
574 | 642a4f96 | ths | fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
|
575 | 642a4f96 | ths | initrd_filename); |
576 | 642a4f96 | ths | exit(1);
|
577 | 642a4f96 | ths | } |
578 | 642a4f96 | ths | |
579 | 642a4f96 | ths | initrd_size = get_file_size(fi); |
580 | 642a4f96 | ths | initrd_addr = phys_ram_base + ((initrd_max-initrd_size) & ~4095);
|
581 | 642a4f96 | ths | |
582 | 642a4f96 | ths | fprintf(stderr, "qemu: loading initrd (%#x bytes) at %#zx\n",
|
583 | 642a4f96 | ths | initrd_size, initrd_addr-phys_ram_base); |
584 | 642a4f96 | ths | |
585 | 642a4f96 | ths | if (fread(initrd_addr, 1, initrd_size, fi) != initrd_size) { |
586 | 642a4f96 | ths | fprintf(stderr, "qemu: read error on initial ram disk '%s'\n",
|
587 | 642a4f96 | ths | initrd_filename); |
588 | 642a4f96 | ths | exit(1);
|
589 | 642a4f96 | ths | } |
590 | 642a4f96 | ths | fclose(fi); |
591 | 642a4f96 | ths | |
592 | 642a4f96 | ths | stl_p(header+0x218, initrd_addr-phys_ram_base);
|
593 | 642a4f96 | ths | stl_p(header+0x21c, initrd_size);
|
594 | 642a4f96 | ths | } |
595 | 642a4f96 | ths | |
596 | 642a4f96 | ths | /* store the finalized header and load the rest of the kernel */
|
597 | 642a4f96 | ths | memcpy(real_addr, header, 1024);
|
598 | 642a4f96 | ths | |
599 | 642a4f96 | ths | setup_size = header[0x1f1];
|
600 | 642a4f96 | ths | if (setup_size == 0) |
601 | 642a4f96 | ths | setup_size = 4;
|
602 | 642a4f96 | ths | |
603 | 642a4f96 | ths | setup_size = (setup_size+1)*512; |
604 | 642a4f96 | ths | kernel_size -= setup_size; /* Size of protected-mode code */
|
605 | 642a4f96 | ths | |
606 | 642a4f96 | ths | if (fread(real_addr+1024, 1, setup_size-1024, f) != setup_size-1024 || |
607 | 642a4f96 | ths | fread(prot_addr, 1, kernel_size, f) != kernel_size) {
|
608 | 642a4f96 | ths | fprintf(stderr, "qemu: read error on kernel '%s'\n",
|
609 | 642a4f96 | ths | kernel_filename); |
610 | 642a4f96 | ths | exit(1);
|
611 | 642a4f96 | ths | } |
612 | 642a4f96 | ths | fclose(f); |
613 | 642a4f96 | ths | |
614 | 642a4f96 | ths | /* generate bootsector to set up the initial register state */
|
615 | 642a4f96 | ths | real_seg = (real_addr-phys_ram_base) >> 4;
|
616 | 642a4f96 | ths | seg[0] = seg[2] = seg[3] = seg[4] = seg[4] = real_seg; |
617 | 642a4f96 | ths | seg[1] = real_seg+0x20; /* CS */ |
618 | 642a4f96 | ths | memset(gpr, 0, sizeof gpr); |
619 | 642a4f96 | ths | gpr[4] = cmdline_addr-real_addr-16; /* SP (-16 is paranoia) */ |
620 | 642a4f96 | ths | |
621 | 642a4f96 | ths | generate_bootsect(gpr, seg, 0);
|
622 | 642a4f96 | ths | } |
623 | 642a4f96 | ths | |
624 | 59b8ad81 | bellard | static void main_cpu_reset(void *opaque) |
625 | 59b8ad81 | bellard | { |
626 | 59b8ad81 | bellard | CPUState *env = opaque; |
627 | 59b8ad81 | bellard | cpu_reset(env); |
628 | 59b8ad81 | bellard | } |
629 | 59b8ad81 | bellard | |
630 | b41a2cd1 | bellard | static const int ide_iobase[2] = { 0x1f0, 0x170 }; |
631 | b41a2cd1 | bellard | static const int ide_iobase2[2] = { 0x3f6, 0x376 }; |
632 | b41a2cd1 | bellard | static const int ide_irq[2] = { 14, 15 }; |
633 | b41a2cd1 | bellard | |
634 | b41a2cd1 | bellard | #define NE2000_NB_MAX 6 |
635 | b41a2cd1 | bellard | |
636 | 8d11df9e | bellard | static int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 0x280, 0x380 }; |
637 | b41a2cd1 | bellard | static int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 }; |
638 | b41a2cd1 | bellard | |
639 | 8d11df9e | bellard | static int serial_io[MAX_SERIAL_PORTS] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8 }; |
640 | 8d11df9e | bellard | static int serial_irq[MAX_SERIAL_PORTS] = { 4, 3, 4, 3 }; |
641 | 8d11df9e | bellard | |
642 | 6508fe59 | bellard | static int parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc }; |
643 | 6508fe59 | bellard | static int parallel_irq[MAX_PARALLEL_PORTS] = { 7, 7, 7 }; |
644 | 6508fe59 | bellard | |
645 | 6a36d84e | bellard | #ifdef HAS_AUDIO
|
646 | d537cf6c | pbrook | static void audio_init (PCIBus *pci_bus, qemu_irq *pic) |
647 | 6a36d84e | bellard | { |
648 | 6a36d84e | bellard | struct soundhw *c;
|
649 | 6a36d84e | bellard | int audio_enabled = 0; |
650 | 6a36d84e | bellard | |
651 | 6a36d84e | bellard | for (c = soundhw; !audio_enabled && c->name; ++c) {
|
652 | 6a36d84e | bellard | audio_enabled = c->enabled; |
653 | 6a36d84e | bellard | } |
654 | 6a36d84e | bellard | |
655 | 6a36d84e | bellard | if (audio_enabled) {
|
656 | 6a36d84e | bellard | AudioState *s; |
657 | 6a36d84e | bellard | |
658 | 6a36d84e | bellard | s = AUD_init (); |
659 | 6a36d84e | bellard | if (s) {
|
660 | 6a36d84e | bellard | for (c = soundhw; c->name; ++c) {
|
661 | 6a36d84e | bellard | if (c->enabled) {
|
662 | 6a36d84e | bellard | if (c->isa) {
|
663 | d537cf6c | pbrook | c->init.init_isa (s, pic); |
664 | 6a36d84e | bellard | } |
665 | 6a36d84e | bellard | else {
|
666 | 6a36d84e | bellard | if (pci_bus) {
|
667 | 6a36d84e | bellard | c->init.init_pci (pci_bus, s); |
668 | 6a36d84e | bellard | } |
669 | 6a36d84e | bellard | } |
670 | 6a36d84e | bellard | } |
671 | 6a36d84e | bellard | } |
672 | 6a36d84e | bellard | } |
673 | 6a36d84e | bellard | } |
674 | 6a36d84e | bellard | } |
675 | 6a36d84e | bellard | #endif
|
676 | 6a36d84e | bellard | |
677 | d537cf6c | pbrook | static void pc_init_ne2k_isa(NICInfo *nd, qemu_irq *pic) |
678 | a41b2ff2 | pbrook | { |
679 | a41b2ff2 | pbrook | static int nb_ne2k = 0; |
680 | a41b2ff2 | pbrook | |
681 | a41b2ff2 | pbrook | if (nb_ne2k == NE2000_NB_MAX)
|
682 | a41b2ff2 | pbrook | return;
|
683 | d537cf6c | pbrook | isa_ne2000_init(ne2000_io[nb_ne2k], pic[ne2000_irq[nb_ne2k]], nd); |
684 | a41b2ff2 | pbrook | nb_ne2k++; |
685 | a41b2ff2 | pbrook | } |
686 | a41b2ff2 | pbrook | |
687 | 80cabfad | bellard | /* PC hardware initialisation */
|
688 | 00f82b8a | aurel32 | static void pc_init1(ram_addr_t ram_size, int vga_ram_size, |
689 | b881c2c6 | blueswir1 | const char *boot_device, DisplayState *ds, |
690 | b5ff2d6e | bellard | const char *kernel_filename, const char *kernel_cmdline, |
691 | 3dbbdc25 | bellard | const char *initrd_filename, |
692 | a049de61 | bellard | int pci_enabled, const char *cpu_model) |
693 | 80cabfad | bellard | { |
694 | 80cabfad | bellard | char buf[1024]; |
695 | 642a4f96 | ths | int ret, linux_boot, i;
|
696 | 970ac5a3 | bellard | ram_addr_t ram_addr, vga_ram_addr, bios_offset, vga_bios_offset; |
697 | 00f82b8a | aurel32 | ram_addr_t below_4g_mem_size, above_4g_mem_size = 0;
|
698 | 970ac5a3 | bellard | int bios_size, isa_bios_size, vga_bios_size;
|
699 | 46e50e9d | bellard | PCIBus *pci_bus; |
700 | 5c3ff3a7 | pbrook | int piix3_devfn = -1; |
701 | 59b8ad81 | bellard | CPUState *env; |
702 | a41b2ff2 | pbrook | NICInfo *nd; |
703 | d537cf6c | pbrook | qemu_irq *cpu_irq; |
704 | d537cf6c | pbrook | qemu_irq *i8259; |
705 | e4bcb14c | ths | int index;
|
706 | e4bcb14c | ths | BlockDriverState *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; |
707 | e4bcb14c | ths | BlockDriverState *fd[MAX_FD]; |
708 | d592d303 | bellard | |
709 | 00f82b8a | aurel32 | if (ram_size >= 0xe0000000 ) { |
710 | 00f82b8a | aurel32 | above_4g_mem_size = ram_size - 0xe0000000;
|
711 | 00f82b8a | aurel32 | below_4g_mem_size = 0xe0000000;
|
712 | 00f82b8a | aurel32 | } else {
|
713 | 00f82b8a | aurel32 | below_4g_mem_size = ram_size; |
714 | 00f82b8a | aurel32 | } |
715 | 00f82b8a | aurel32 | |
716 | 80cabfad | bellard | linux_boot = (kernel_filename != NULL);
|
717 | 80cabfad | bellard | |
718 | 59b8ad81 | bellard | /* init CPUs */
|
719 | a049de61 | bellard | if (cpu_model == NULL) { |
720 | a049de61 | bellard | #ifdef TARGET_X86_64
|
721 | a049de61 | bellard | cpu_model = "qemu64";
|
722 | a049de61 | bellard | #else
|
723 | a049de61 | bellard | cpu_model = "qemu32";
|
724 | a049de61 | bellard | #endif
|
725 | a049de61 | bellard | } |
726 | a049de61 | bellard | |
727 | 59b8ad81 | bellard | for(i = 0; i < smp_cpus; i++) { |
728 | aaed909a | bellard | env = cpu_init(cpu_model); |
729 | aaed909a | bellard | if (!env) {
|
730 | aaed909a | bellard | fprintf(stderr, "Unable to find x86 CPU definition\n");
|
731 | aaed909a | bellard | exit(1);
|
732 | aaed909a | bellard | } |
733 | 59b8ad81 | bellard | if (i != 0) |
734 | ad49ff9d | bellard | env->hflags |= HF_HALTED_MASK; |
735 | 59b8ad81 | bellard | if (smp_cpus > 1) { |
736 | 59b8ad81 | bellard | /* XXX: enable it in all cases */
|
737 | 59b8ad81 | bellard | env->cpuid_features |= CPUID_APIC; |
738 | 59b8ad81 | bellard | } |
739 | a5954d5c | bellard | register_savevm("cpu", i, 4, cpu_save, cpu_load, env); |
740 | 59b8ad81 | bellard | qemu_register_reset(main_cpu_reset, env); |
741 | 59b8ad81 | bellard | if (pci_enabled) {
|
742 | 59b8ad81 | bellard | apic_init(env); |
743 | 59b8ad81 | bellard | } |
744 | 59b8ad81 | bellard | } |
745 | 59b8ad81 | bellard | |
746 | 26fb5e48 | aurel32 | vmport_init(); |
747 | 26fb5e48 | aurel32 | |
748 | 80cabfad | bellard | /* allocate RAM */
|
749 | 970ac5a3 | bellard | ram_addr = qemu_ram_alloc(ram_size); |
750 | 00f82b8a | aurel32 | cpu_register_physical_memory(0, below_4g_mem_size, ram_addr);
|
751 | 00f82b8a | aurel32 | |
752 | 00f82b8a | aurel32 | /* above 4giga memory allocation */
|
753 | 00f82b8a | aurel32 | if (above_4g_mem_size > 0) { |
754 | 00f82b8a | aurel32 | cpu_register_physical_memory(0x100000000ULL, above_4g_mem_size,
|
755 | 00f82b8a | aurel32 | ram_addr + below_4g_mem_size); |
756 | 00f82b8a | aurel32 | } |
757 | 80cabfad | bellard | |
758 | 970ac5a3 | bellard | /* allocate VGA RAM */
|
759 | 970ac5a3 | bellard | vga_ram_addr = qemu_ram_alloc(vga_ram_size); |
760 | 7587cf44 | bellard | |
761 | 970ac5a3 | bellard | /* BIOS load */
|
762 | 1192dad8 | j_mayer | if (bios_name == NULL) |
763 | 1192dad8 | j_mayer | bios_name = BIOS_FILENAME; |
764 | 1192dad8 | j_mayer | snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name); |
765 | 7587cf44 | bellard | bios_size = get_image_size(buf); |
766 | 5fafdf24 | ths | if (bios_size <= 0 || |
767 | 970ac5a3 | bellard | (bios_size % 65536) != 0) { |
768 | 7587cf44 | bellard | goto bios_error;
|
769 | 7587cf44 | bellard | } |
770 | 970ac5a3 | bellard | bios_offset = qemu_ram_alloc(bios_size); |
771 | 7587cf44 | bellard | ret = load_image(buf, phys_ram_base + bios_offset); |
772 | 7587cf44 | bellard | if (ret != bios_size) {
|
773 | 7587cf44 | bellard | bios_error:
|
774 | 970ac5a3 | bellard | fprintf(stderr, "qemu: could not load PC BIOS '%s'\n", buf);
|
775 | 80cabfad | bellard | exit(1);
|
776 | 80cabfad | bellard | } |
777 | 7587cf44 | bellard | |
778 | 80cabfad | bellard | /* VGA BIOS load */
|
779 | de9258a8 | bellard | if (cirrus_vga_enabled) {
|
780 | de9258a8 | bellard | snprintf(buf, sizeof(buf), "%s/%s", bios_dir, VGABIOS_CIRRUS_FILENAME); |
781 | de9258a8 | bellard | } else {
|
782 | de9258a8 | bellard | snprintf(buf, sizeof(buf), "%s/%s", bios_dir, VGABIOS_FILENAME); |
783 | de9258a8 | bellard | } |
784 | 970ac5a3 | bellard | vga_bios_size = get_image_size(buf); |
785 | 5fafdf24 | ths | if (vga_bios_size <= 0 || vga_bios_size > 65536) |
786 | 970ac5a3 | bellard | goto vga_bios_error;
|
787 | 970ac5a3 | bellard | vga_bios_offset = qemu_ram_alloc(65536);
|
788 | 970ac5a3 | bellard | |
789 | 7587cf44 | bellard | ret = load_image(buf, phys_ram_base + vga_bios_offset); |
790 | 970ac5a3 | bellard | if (ret != vga_bios_size) {
|
791 | 970ac5a3 | bellard | vga_bios_error:
|
792 | 970ac5a3 | bellard | fprintf(stderr, "qemu: could not load VGA BIOS '%s'\n", buf);
|
793 | 970ac5a3 | bellard | exit(1);
|
794 | 970ac5a3 | bellard | } |
795 | 970ac5a3 | bellard | |
796 | 80cabfad | bellard | /* setup basic memory access */
|
797 | 5fafdf24 | ths | cpu_register_physical_memory(0xc0000, 0x10000, |
798 | 7587cf44 | bellard | vga_bios_offset | IO_MEM_ROM); |
799 | 7587cf44 | bellard | |
800 | 7587cf44 | bellard | /* map the last 128KB of the BIOS in ISA space */
|
801 | 7587cf44 | bellard | isa_bios_size = bios_size; |
802 | 7587cf44 | bellard | if (isa_bios_size > (128 * 1024)) |
803 | 7587cf44 | bellard | isa_bios_size = 128 * 1024; |
804 | 5fafdf24 | ths | cpu_register_physical_memory(0xd0000, (192 * 1024) - isa_bios_size, |
805 | 7587cf44 | bellard | IO_MEM_UNASSIGNED); |
806 | 5fafdf24 | ths | cpu_register_physical_memory(0x100000 - isa_bios_size,
|
807 | 5fafdf24 | ths | isa_bios_size, |
808 | 7587cf44 | bellard | (bios_offset + bios_size - isa_bios_size) | IO_MEM_ROM); |
809 | 9ae02555 | ths | |
810 | 970ac5a3 | bellard | { |
811 | 970ac5a3 | bellard | ram_addr_t option_rom_offset; |
812 | 970ac5a3 | bellard | int size, offset;
|
813 | 970ac5a3 | bellard | |
814 | 970ac5a3 | bellard | offset = 0;
|
815 | 970ac5a3 | bellard | for (i = 0; i < nb_option_roms; i++) { |
816 | 970ac5a3 | bellard | size = get_image_size(option_rom[i]); |
817 | 970ac5a3 | bellard | if (size < 0) { |
818 | 5fafdf24 | ths | fprintf(stderr, "Could not load option rom '%s'\n",
|
819 | 970ac5a3 | bellard | option_rom[i]); |
820 | 970ac5a3 | bellard | exit(1);
|
821 | 970ac5a3 | bellard | } |
822 | 970ac5a3 | bellard | if (size > (0x10000 - offset)) |
823 | 970ac5a3 | bellard | goto option_rom_error;
|
824 | 970ac5a3 | bellard | option_rom_offset = qemu_ram_alloc(size); |
825 | 970ac5a3 | bellard | ret = load_image(option_rom[i], phys_ram_base + option_rom_offset); |
826 | 970ac5a3 | bellard | if (ret != size) {
|
827 | 970ac5a3 | bellard | option_rom_error:
|
828 | 970ac5a3 | bellard | fprintf(stderr, "Too many option ROMS\n");
|
829 | 970ac5a3 | bellard | exit(1);
|
830 | 970ac5a3 | bellard | } |
831 | 970ac5a3 | bellard | size = (size + 4095) & ~4095; |
832 | 970ac5a3 | bellard | cpu_register_physical_memory(0xd0000 + offset,
|
833 | 970ac5a3 | bellard | size, option_rom_offset | IO_MEM_ROM); |
834 | 970ac5a3 | bellard | offset += size; |
835 | 970ac5a3 | bellard | } |
836 | 9ae02555 | ths | } |
837 | 9ae02555 | ths | |
838 | 7587cf44 | bellard | /* map all the bios at the top of memory */
|
839 | 5fafdf24 | ths | cpu_register_physical_memory((uint32_t)(-bios_size), |
840 | 7587cf44 | bellard | bios_size, bios_offset | IO_MEM_ROM); |
841 | 3b46e624 | ths | |
842 | 80cabfad | bellard | bochs_bios_init(); |
843 | 80cabfad | bellard | |
844 | 642a4f96 | ths | if (linux_boot)
|
845 | 642a4f96 | ths | load_linux(kernel_filename, initrd_filename, kernel_cmdline); |
846 | 80cabfad | bellard | |
847 | a5b38b51 | aurel32 | cpu_irq = qemu_allocate_irqs(pic_irq_request, NULL, 1); |
848 | d537cf6c | pbrook | i8259 = i8259_init(cpu_irq[0]);
|
849 | d537cf6c | pbrook | ferr_irq = i8259[13];
|
850 | d537cf6c | pbrook | |
851 | 69b91039 | bellard | if (pci_enabled) {
|
852 | d537cf6c | pbrook | pci_bus = i440fx_init(&i440fx_state, i8259); |
853 | 8f1c91d8 | ths | piix3_devfn = piix3_init(pci_bus, -1);
|
854 | 46e50e9d | bellard | } else {
|
855 | 46e50e9d | bellard | pci_bus = NULL;
|
856 | 69b91039 | bellard | } |
857 | 69b91039 | bellard | |
858 | 80cabfad | bellard | /* init basic PC hardware */
|
859 | b41a2cd1 | bellard | register_ioport_write(0x80, 1, 1, ioport80_write, NULL); |
860 | 80cabfad | bellard | |
861 | f929aad6 | bellard | register_ioport_write(0xf0, 1, 1, ioportF0_write, NULL); |
862 | f929aad6 | bellard | |
863 | 1f04275e | bellard | if (cirrus_vga_enabled) {
|
864 | 1f04275e | bellard | if (pci_enabled) {
|
865 | 5fafdf24 | ths | pci_cirrus_vga_init(pci_bus, |
866 | 5fafdf24 | ths | ds, phys_ram_base + vga_ram_addr, |
867 | 970ac5a3 | bellard | vga_ram_addr, vga_ram_size); |
868 | 1f04275e | bellard | } else {
|
869 | 5fafdf24 | ths | isa_cirrus_vga_init(ds, phys_ram_base + vga_ram_addr, |
870 | 970ac5a3 | bellard | vga_ram_addr, vga_ram_size); |
871 | 1f04275e | bellard | } |
872 | d34cab9f | ths | } else if (vmsvga_enabled) { |
873 | d34cab9f | ths | if (pci_enabled)
|
874 | 45e4522e | balrog | pci_vmsvga_init(pci_bus, ds, phys_ram_base + vga_ram_addr, |
875 | 45e4522e | balrog | vga_ram_addr, vga_ram_size); |
876 | d34cab9f | ths | else
|
877 | d34cab9f | ths | fprintf(stderr, "%s: vmware_vga: no PCI bus\n", __FUNCTION__);
|
878 | 1f04275e | bellard | } else {
|
879 | 89b6b508 | bellard | if (pci_enabled) {
|
880 | 5fafdf24 | ths | pci_vga_init(pci_bus, ds, phys_ram_base + vga_ram_addr, |
881 | 970ac5a3 | bellard | vga_ram_addr, vga_ram_size, 0, 0); |
882 | 89b6b508 | bellard | } else {
|
883 | 5fafdf24 | ths | isa_vga_init(ds, phys_ram_base + vga_ram_addr, |
884 | 970ac5a3 | bellard | vga_ram_addr, vga_ram_size); |
885 | 89b6b508 | bellard | } |
886 | 1f04275e | bellard | } |
887 | 80cabfad | bellard | |
888 | d537cf6c | pbrook | rtc_state = rtc_init(0x70, i8259[8]); |
889 | 80cabfad | bellard | |
890 | e1a23744 | bellard | register_ioport_read(0x92, 1, 1, ioport92_read, NULL); |
891 | e1a23744 | bellard | register_ioport_write(0x92, 1, 1, ioport92_write, NULL); |
892 | e1a23744 | bellard | |
893 | d592d303 | bellard | if (pci_enabled) {
|
894 | d592d303 | bellard | ioapic = ioapic_init(); |
895 | d592d303 | bellard | } |
896 | d537cf6c | pbrook | pit = pit_init(0x40, i8259[0]); |
897 | fd06c375 | bellard | pcspk_init(pit); |
898 | d592d303 | bellard | if (pci_enabled) {
|
899 | d592d303 | bellard | pic_set_alt_irq_func(isa_pic, ioapic_set_irq, ioapic); |
900 | d592d303 | bellard | } |
901 | b41a2cd1 | bellard | |
902 | 8d11df9e | bellard | for(i = 0; i < MAX_SERIAL_PORTS; i++) { |
903 | 8d11df9e | bellard | if (serial_hds[i]) {
|
904 | d537cf6c | pbrook | serial_init(serial_io[i], i8259[serial_irq[i]], serial_hds[i]); |
905 | 8d11df9e | bellard | } |
906 | 8d11df9e | bellard | } |
907 | b41a2cd1 | bellard | |
908 | 6508fe59 | bellard | for(i = 0; i < MAX_PARALLEL_PORTS; i++) { |
909 | 6508fe59 | bellard | if (parallel_hds[i]) {
|
910 | d537cf6c | pbrook | parallel_init(parallel_io[i], i8259[parallel_irq[i]], |
911 | d537cf6c | pbrook | parallel_hds[i]); |
912 | 6508fe59 | bellard | } |
913 | 6508fe59 | bellard | } |
914 | 6508fe59 | bellard | |
915 | a41b2ff2 | pbrook | for(i = 0; i < nb_nics; i++) { |
916 | a41b2ff2 | pbrook | nd = &nd_table[i]; |
917 | a41b2ff2 | pbrook | if (!nd->model) {
|
918 | a41b2ff2 | pbrook | if (pci_enabled) {
|
919 | a41b2ff2 | pbrook | nd->model = "ne2k_pci";
|
920 | a41b2ff2 | pbrook | } else {
|
921 | a41b2ff2 | pbrook | nd->model = "ne2k_isa";
|
922 | a41b2ff2 | pbrook | } |
923 | 69b91039 | bellard | } |
924 | a41b2ff2 | pbrook | if (strcmp(nd->model, "ne2k_isa") == 0) { |
925 | d537cf6c | pbrook | pc_init_ne2k_isa(nd, i8259); |
926 | a41b2ff2 | pbrook | } else if (pci_enabled) { |
927 | c4a7060c | blueswir1 | if (strcmp(nd->model, "?") == 0) |
928 | c4a7060c | blueswir1 | fprintf(stderr, "qemu: Supported ISA NICs: ne2k_isa\n");
|
929 | abcebc7e | ths | pci_nic_init(pci_bus, nd, -1);
|
930 | c4a7060c | blueswir1 | } else if (strcmp(nd->model, "?") == 0) { |
931 | c4a7060c | blueswir1 | fprintf(stderr, "qemu: Supported ISA NICs: ne2k_isa\n");
|
932 | c4a7060c | blueswir1 | exit(1);
|
933 | a41b2ff2 | pbrook | } else {
|
934 | a41b2ff2 | pbrook | fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd->model);
|
935 | a41b2ff2 | pbrook | exit(1);
|
936 | 69b91039 | bellard | } |
937 | a41b2ff2 | pbrook | } |
938 | b41a2cd1 | bellard | |
939 | e4bcb14c | ths | if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) {
|
940 | e4bcb14c | ths | fprintf(stderr, "qemu: too many IDE bus\n");
|
941 | e4bcb14c | ths | exit(1);
|
942 | e4bcb14c | ths | } |
943 | e4bcb14c | ths | |
944 | e4bcb14c | ths | for(i = 0; i < MAX_IDE_BUS * MAX_IDE_DEVS; i++) { |
945 | e4bcb14c | ths | index = drive_get_index(IF_IDE, i / MAX_IDE_DEVS, i % MAX_IDE_DEVS); |
946 | e4bcb14c | ths | if (index != -1) |
947 | e4bcb14c | ths | hd[i] = drives_table[index].bdrv; |
948 | e4bcb14c | ths | else
|
949 | e4bcb14c | ths | hd[i] = NULL;
|
950 | e4bcb14c | ths | } |
951 | e4bcb14c | ths | |
952 | a41b2ff2 | pbrook | if (pci_enabled) {
|
953 | e4bcb14c | ths | pci_piix3_ide_init(pci_bus, hd, piix3_devfn + 1, i8259);
|
954 | a41b2ff2 | pbrook | } else {
|
955 | e4bcb14c | ths | for(i = 0; i < MAX_IDE_BUS; i++) { |
956 | d537cf6c | pbrook | isa_ide_init(ide_iobase[i], ide_iobase2[i], i8259[ide_irq[i]], |
957 | e4bcb14c | ths | hd[MAX_IDE_DEVS * i], hd[MAX_IDE_DEVS * i + 1]);
|
958 | 69b91039 | bellard | } |
959 | b41a2cd1 | bellard | } |
960 | 69b91039 | bellard | |
961 | d537cf6c | pbrook | i8042_init(i8259[1], i8259[12], 0x60); |
962 | 7c29d0c0 | bellard | DMA_init(0);
|
963 | 6a36d84e | bellard | #ifdef HAS_AUDIO
|
964 | d537cf6c | pbrook | audio_init(pci_enabled ? pci_bus : NULL, i8259);
|
965 | fb065187 | bellard | #endif
|
966 | 80cabfad | bellard | |
967 | e4bcb14c | ths | for(i = 0; i < MAX_FD; i++) { |
968 | e4bcb14c | ths | index = drive_get_index(IF_FLOPPY, 0, i);
|
969 | e4bcb14c | ths | if (index != -1) |
970 | e4bcb14c | ths | fd[i] = drives_table[index].bdrv; |
971 | e4bcb14c | ths | else
|
972 | e4bcb14c | ths | fd[i] = NULL;
|
973 | e4bcb14c | ths | } |
974 | e4bcb14c | ths | floppy_controller = fdctrl_init(i8259[6], 2, 0, 0x3f0, fd); |
975 | b41a2cd1 | bellard | |
976 | 00f82b8a | aurel32 | cmos_init(below_4g_mem_size, above_4g_mem_size, boot_device, hd); |
977 | 69b91039 | bellard | |
978 | bb36d470 | bellard | if (pci_enabled && usb_enabled) {
|
979 | afcc3cdf | ths | usb_uhci_piix3_init(pci_bus, piix3_devfn + 2);
|
980 | bb36d470 | bellard | } |
981 | bb36d470 | bellard | |
982 | 6515b203 | bellard | if (pci_enabled && acpi_enabled) {
|
983 | 3fffc223 | ths | uint8_t *eeprom_buf = qemu_mallocz(8 * 256); /* XXX: make this persistent */ |
984 | 0ff596d0 | pbrook | i2c_bus *smbus; |
985 | 0ff596d0 | pbrook | |
986 | 0ff596d0 | pbrook | /* TODO: Populate SPD eeprom data. */
|
987 | cf7a2fe2 | aurel32 | smbus = piix4_pm_init(pci_bus, piix3_devfn + 3, 0xb100, i8259[9]); |
988 | 3fffc223 | ths | for (i = 0; i < 8; i++) { |
989 | 0ff596d0 | pbrook | smbus_eeprom_device_init(smbus, 0x50 + i, eeprom_buf + (i * 256)); |
990 | 3fffc223 | ths | } |
991 | 6515b203 | bellard | } |
992 | 3b46e624 | ths | |
993 | a5954d5c | bellard | if (i440fx_state) {
|
994 | a5954d5c | bellard | i440fx_init_memory_mappings(i440fx_state); |
995 | a5954d5c | bellard | } |
996 | e4bcb14c | ths | |
997 | 7d8406be | pbrook | if (pci_enabled) {
|
998 | e4bcb14c | ths | int max_bus;
|
999 | e4bcb14c | ths | int bus, unit;
|
1000 | 7d8406be | pbrook | void *scsi;
|
1001 | 96d30e48 | ths | |
1002 | e4bcb14c | ths | max_bus = drive_get_max_bus(IF_SCSI); |
1003 | e4bcb14c | ths | |
1004 | e4bcb14c | ths | for (bus = 0; bus <= max_bus; bus++) { |
1005 | e4bcb14c | ths | scsi = lsi_scsi_init(pci_bus, -1);
|
1006 | e4bcb14c | ths | for (unit = 0; unit < LSI_MAX_DEVS; unit++) { |
1007 | e4bcb14c | ths | index = drive_get_index(IF_SCSI, bus, unit); |
1008 | e4bcb14c | ths | if (index == -1) |
1009 | e4bcb14c | ths | continue;
|
1010 | e4bcb14c | ths | lsi_scsi_attach(scsi, drives_table[index].bdrv, unit); |
1011 | e4bcb14c | ths | } |
1012 | e4bcb14c | ths | } |
1013 | 7d8406be | pbrook | } |
1014 | 80cabfad | bellard | } |
1015 | b5ff2d6e | bellard | |
1016 | 00f82b8a | aurel32 | static void pc_init_pci(ram_addr_t ram_size, int vga_ram_size, |
1017 | b881c2c6 | blueswir1 | const char *boot_device, DisplayState *ds, |
1018 | 5fafdf24 | ths | const char *kernel_filename, |
1019 | 3dbbdc25 | bellard | const char *kernel_cmdline, |
1020 | 94fc95cd | j_mayer | const char *initrd_filename, |
1021 | 94fc95cd | j_mayer | const char *cpu_model) |
1022 | 3dbbdc25 | bellard | { |
1023 | b881c2c6 | blueswir1 | pc_init1(ram_size, vga_ram_size, boot_device, ds, |
1024 | 3dbbdc25 | bellard | kernel_filename, kernel_cmdline, |
1025 | a049de61 | bellard | initrd_filename, 1, cpu_model);
|
1026 | 3dbbdc25 | bellard | } |
1027 | 3dbbdc25 | bellard | |
1028 | 00f82b8a | aurel32 | static void pc_init_isa(ram_addr_t ram_size, int vga_ram_size, |
1029 | b881c2c6 | blueswir1 | const char *boot_device, DisplayState *ds, |
1030 | 5fafdf24 | ths | const char *kernel_filename, |
1031 | 3dbbdc25 | bellard | const char *kernel_cmdline, |
1032 | 94fc95cd | j_mayer | const char *initrd_filename, |
1033 | 94fc95cd | j_mayer | const char *cpu_model) |
1034 | 3dbbdc25 | bellard | { |
1035 | b881c2c6 | blueswir1 | pc_init1(ram_size, vga_ram_size, boot_device, ds, |
1036 | 3dbbdc25 | bellard | kernel_filename, kernel_cmdline, |
1037 | a049de61 | bellard | initrd_filename, 0, cpu_model);
|
1038 | 3dbbdc25 | bellard | } |
1039 | 3dbbdc25 | bellard | |
1040 | b5ff2d6e | bellard | QEMUMachine pc_machine = { |
1041 | b5ff2d6e | bellard | "pc",
|
1042 | b5ff2d6e | bellard | "Standard PC",
|
1043 | 3dbbdc25 | bellard | pc_init_pci, |
1044 | 7fb4fdcf | balrog | VGA_RAM_SIZE + PC_MAX_BIOS_SIZE, |
1045 | 3dbbdc25 | bellard | }; |
1046 | 3dbbdc25 | bellard | |
1047 | 3dbbdc25 | bellard | QEMUMachine isapc_machine = { |
1048 | 3dbbdc25 | bellard | "isapc",
|
1049 | 3dbbdc25 | bellard | "ISA-only PC",
|
1050 | 3dbbdc25 | bellard | pc_init_isa, |
1051 | 7fb4fdcf | balrog | VGA_RAM_SIZE + PC_MAX_BIOS_SIZE, |
1052 | b5ff2d6e | bellard | }; |