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1 | 02eb84d0 | Michael S. Tsirkin | /*
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2 | 02eb84d0 | Michael S. Tsirkin | * MSI-X device support
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3 | 02eb84d0 | Michael S. Tsirkin | *
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4 | 02eb84d0 | Michael S. Tsirkin | * This module includes support for MSI-X in pci devices.
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5 | 02eb84d0 | Michael S. Tsirkin | *
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6 | 02eb84d0 | Michael S. Tsirkin | * Author: Michael S. Tsirkin <mst@redhat.com>
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7 | 02eb84d0 | Michael S. Tsirkin | *
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8 | 02eb84d0 | Michael S. Tsirkin | * Copyright (c) 2009, Red Hat Inc, Michael S. Tsirkin (mst@redhat.com)
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9 | 02eb84d0 | Michael S. Tsirkin | *
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10 | 02eb84d0 | Michael S. Tsirkin | * This work is licensed under the terms of the GNU GPL, version 2. See
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11 | 02eb84d0 | Michael S. Tsirkin | * the COPYING file in the top-level directory.
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12 | 02eb84d0 | Michael S. Tsirkin | */
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13 | 02eb84d0 | Michael S. Tsirkin | |
14 | 02eb84d0 | Michael S. Tsirkin | #include "hw.h" |
15 | 02eb84d0 | Michael S. Tsirkin | #include "msix.h" |
16 | 02eb84d0 | Michael S. Tsirkin | #include "pci.h" |
17 | bf1b0071 | Blue Swirl | #include "range.h" |
18 | 02eb84d0 | Michael S. Tsirkin | |
19 | 02eb84d0 | Michael S. Tsirkin | #define MSIX_CAP_LENGTH 12 |
20 | 02eb84d0 | Michael S. Tsirkin | |
21 | 2760952b | Michael S. Tsirkin | /* MSI enable bit and maskall bit are in byte 1 in FLAGS register */
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22 | 2760952b | Michael S. Tsirkin | #define MSIX_CONTROL_OFFSET (PCI_MSIX_FLAGS + 1) |
23 | 02eb84d0 | Michael S. Tsirkin | #define MSIX_ENABLE_MASK (PCI_MSIX_FLAGS_ENABLE >> 8) |
24 | 5b5cb086 | Michael S. Tsirkin | #define MSIX_MASKALL_MASK (PCI_MSIX_FLAGS_MASKALL >> 8) |
25 | 02eb84d0 | Michael S. Tsirkin | |
26 | 5a1fc5e8 | Michael S. Tsirkin | /* How much space does an MSIX table need. */
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27 | 5a1fc5e8 | Michael S. Tsirkin | /* The spec requires giving the table structure
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28 | 5a1fc5e8 | Michael S. Tsirkin | * a 4K aligned region all by itself. */
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29 | 5a1fc5e8 | Michael S. Tsirkin | #define MSIX_PAGE_SIZE 0x1000 |
30 | 5a1fc5e8 | Michael S. Tsirkin | /* Reserve second half of the page for pending bits */
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31 | 5a1fc5e8 | Michael S. Tsirkin | #define MSIX_PAGE_PENDING (MSIX_PAGE_SIZE / 2) |
32 | 02eb84d0 | Michael S. Tsirkin | #define MSIX_MAX_ENTRIES 32 |
33 | 02eb84d0 | Michael S. Tsirkin | |
34 | 02eb84d0 | Michael S. Tsirkin | |
35 | 02eb84d0 | Michael S. Tsirkin | /* Flag for interrupt controller to declare MSI-X support */
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36 | 02eb84d0 | Michael S. Tsirkin | int msix_supported;
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37 | 02eb84d0 | Michael S. Tsirkin | |
38 | 02eb84d0 | Michael S. Tsirkin | /* Add MSI-X capability to the config space for the device. */
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39 | 02eb84d0 | Michael S. Tsirkin | /* Given a bar and its size, add MSI-X table on top of it
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40 | 02eb84d0 | Michael S. Tsirkin | * and fill MSI-X capability in the config space.
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41 | 02eb84d0 | Michael S. Tsirkin | * Original bar size must be a power of 2 or 0.
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42 | 02eb84d0 | Michael S. Tsirkin | * New bar size is returned. */
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43 | 02eb84d0 | Michael S. Tsirkin | static int msix_add_config(struct PCIDevice *pdev, unsigned short nentries, |
44 | 02eb84d0 | Michael S. Tsirkin | unsigned bar_nr, unsigned bar_size) |
45 | 02eb84d0 | Michael S. Tsirkin | { |
46 | 02eb84d0 | Michael S. Tsirkin | int config_offset;
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47 | 02eb84d0 | Michael S. Tsirkin | uint8_t *config; |
48 | 02eb84d0 | Michael S. Tsirkin | uint32_t new_size; |
49 | 02eb84d0 | Michael S. Tsirkin | |
50 | 02eb84d0 | Michael S. Tsirkin | if (nentries < 1 || nentries > PCI_MSIX_FLAGS_QSIZE + 1) |
51 | 02eb84d0 | Michael S. Tsirkin | return -EINVAL;
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52 | 02eb84d0 | Michael S. Tsirkin | if (bar_size > 0x80000000) |
53 | 02eb84d0 | Michael S. Tsirkin | return -ENOSPC;
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54 | 02eb84d0 | Michael S. Tsirkin | |
55 | 02eb84d0 | Michael S. Tsirkin | /* Add space for MSI-X structures */
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56 | 5e520a7d | Blue Swirl | if (!bar_size) {
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57 | 5a1fc5e8 | Michael S. Tsirkin | new_size = MSIX_PAGE_SIZE; |
58 | 5a1fc5e8 | Michael S. Tsirkin | } else if (bar_size < MSIX_PAGE_SIZE) { |
59 | 5a1fc5e8 | Michael S. Tsirkin | bar_size = MSIX_PAGE_SIZE; |
60 | 5a1fc5e8 | Michael S. Tsirkin | new_size = MSIX_PAGE_SIZE * 2;
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61 | 5a1fc5e8 | Michael S. Tsirkin | } else {
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62 | 02eb84d0 | Michael S. Tsirkin | new_size = bar_size * 2;
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63 | 5a1fc5e8 | Michael S. Tsirkin | } |
64 | 02eb84d0 | Michael S. Tsirkin | |
65 | 02eb84d0 | Michael S. Tsirkin | pdev->msix_bar_size = new_size; |
66 | ca77089d | Isaku Yamahata | config_offset = pci_add_capability(pdev, PCI_CAP_ID_MSIX, |
67 | ca77089d | Isaku Yamahata | 0, MSIX_CAP_LENGTH);
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68 | 02eb84d0 | Michael S. Tsirkin | if (config_offset < 0) |
69 | 02eb84d0 | Michael S. Tsirkin | return config_offset;
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70 | 02eb84d0 | Michael S. Tsirkin | config = pdev->config + config_offset; |
71 | 02eb84d0 | Michael S. Tsirkin | |
72 | 02eb84d0 | Michael S. Tsirkin | pci_set_word(config + PCI_MSIX_FLAGS, nentries - 1);
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73 | 02eb84d0 | Michael S. Tsirkin | /* Table on top of BAR */
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74 | 01731cfb | Jan Kiszka | pci_set_long(config + PCI_MSIX_TABLE, bar_size | bar_nr); |
75 | 02eb84d0 | Michael S. Tsirkin | /* Pending bits on top of that */
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76 | 01731cfb | Jan Kiszka | pci_set_long(config + PCI_MSIX_PBA, (bar_size + MSIX_PAGE_PENDING) | |
77 | 5a1fc5e8 | Michael S. Tsirkin | bar_nr); |
78 | 02eb84d0 | Michael S. Tsirkin | pdev->msix_cap = config_offset; |
79 | ebabb67a | Stefan Weil | /* Make flags bit writable. */
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80 | 5b5cb086 | Michael S. Tsirkin | pdev->wmask[config_offset + MSIX_CONTROL_OFFSET] |= MSIX_ENABLE_MASK | |
81 | 5b5cb086 | Michael S. Tsirkin | MSIX_MASKALL_MASK; |
82 | 02eb84d0 | Michael S. Tsirkin | return 0; |
83 | 02eb84d0 | Michael S. Tsirkin | } |
84 | 02eb84d0 | Michael S. Tsirkin | |
85 | c227f099 | Anthony Liguori | static uint32_t msix_mmio_readl(void *opaque, target_phys_addr_t addr) |
86 | 02eb84d0 | Michael S. Tsirkin | { |
87 | 02eb84d0 | Michael S. Tsirkin | PCIDevice *dev = opaque; |
88 | 76f5159d | Michael S. Tsirkin | unsigned int offset = addr & (MSIX_PAGE_SIZE - 1) & ~0x3; |
89 | 02eb84d0 | Michael S. Tsirkin | void *page = dev->msix_table_page;
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90 | 02eb84d0 | Michael S. Tsirkin | |
91 | 76f5159d | Michael S. Tsirkin | return pci_get_long(page + offset);
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92 | 02eb84d0 | Michael S. Tsirkin | } |
93 | 02eb84d0 | Michael S. Tsirkin | |
94 | c227f099 | Anthony Liguori | static uint32_t msix_mmio_read_unallowed(void *opaque, target_phys_addr_t addr) |
95 | 02eb84d0 | Michael S. Tsirkin | { |
96 | 02eb84d0 | Michael S. Tsirkin | fprintf(stderr, "MSI-X: only dword read is allowed!\n");
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97 | 02eb84d0 | Michael S. Tsirkin | return 0; |
98 | 02eb84d0 | Michael S. Tsirkin | } |
99 | 02eb84d0 | Michael S. Tsirkin | |
100 | 02eb84d0 | Michael S. Tsirkin | static uint8_t msix_pending_mask(int vector) |
101 | 02eb84d0 | Michael S. Tsirkin | { |
102 | 02eb84d0 | Michael S. Tsirkin | return 1 << (vector % 8); |
103 | 02eb84d0 | Michael S. Tsirkin | } |
104 | 02eb84d0 | Michael S. Tsirkin | |
105 | 02eb84d0 | Michael S. Tsirkin | static uint8_t *msix_pending_byte(PCIDevice *dev, int vector) |
106 | 02eb84d0 | Michael S. Tsirkin | { |
107 | 5a1fc5e8 | Michael S. Tsirkin | return dev->msix_table_page + MSIX_PAGE_PENDING + vector / 8; |
108 | 02eb84d0 | Michael S. Tsirkin | } |
109 | 02eb84d0 | Michael S. Tsirkin | |
110 | 02eb84d0 | Michael S. Tsirkin | static int msix_is_pending(PCIDevice *dev, int vector) |
111 | 02eb84d0 | Michael S. Tsirkin | { |
112 | 02eb84d0 | Michael S. Tsirkin | return *msix_pending_byte(dev, vector) & msix_pending_mask(vector);
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113 | 02eb84d0 | Michael S. Tsirkin | } |
114 | 02eb84d0 | Michael S. Tsirkin | |
115 | 02eb84d0 | Michael S. Tsirkin | static void msix_set_pending(PCIDevice *dev, int vector) |
116 | 02eb84d0 | Michael S. Tsirkin | { |
117 | 02eb84d0 | Michael S. Tsirkin | *msix_pending_byte(dev, vector) |= msix_pending_mask(vector); |
118 | 02eb84d0 | Michael S. Tsirkin | } |
119 | 02eb84d0 | Michael S. Tsirkin | |
120 | 02eb84d0 | Michael S. Tsirkin | static void msix_clr_pending(PCIDevice *dev, int vector) |
121 | 02eb84d0 | Michael S. Tsirkin | { |
122 | 02eb84d0 | Michael S. Tsirkin | *msix_pending_byte(dev, vector) &= ~msix_pending_mask(vector); |
123 | 02eb84d0 | Michael S. Tsirkin | } |
124 | 02eb84d0 | Michael S. Tsirkin | |
125 | 5b5cb086 | Michael S. Tsirkin | static int msix_function_masked(PCIDevice *dev) |
126 | 5b5cb086 | Michael S. Tsirkin | { |
127 | 5b5cb086 | Michael S. Tsirkin | return dev->config[dev->msix_cap + MSIX_CONTROL_OFFSET] & MSIX_MASKALL_MASK;
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128 | 5b5cb086 | Michael S. Tsirkin | } |
129 | 5b5cb086 | Michael S. Tsirkin | |
130 | 02eb84d0 | Michael S. Tsirkin | static int msix_is_masked(PCIDevice *dev, int vector) |
131 | 02eb84d0 | Michael S. Tsirkin | { |
132 | 01731cfb | Jan Kiszka | unsigned offset =
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133 | 01731cfb | Jan Kiszka | vector * PCI_MSIX_ENTRY_SIZE + PCI_MSIX_ENTRY_VECTOR_CTRL; |
134 | 5b5cb086 | Michael S. Tsirkin | return msix_function_masked(dev) ||
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135 | 01731cfb | Jan Kiszka | dev->msix_table_page[offset] & PCI_MSIX_ENTRY_CTRL_MASKBIT; |
136 | 5b5cb086 | Michael S. Tsirkin | } |
137 | 5b5cb086 | Michael S. Tsirkin | |
138 | 5b5cb086 | Michael S. Tsirkin | static void msix_handle_mask_update(PCIDevice *dev, int vector) |
139 | 5b5cb086 | Michael S. Tsirkin | { |
140 | 5b5cb086 | Michael S. Tsirkin | if (!msix_is_masked(dev, vector) && msix_is_pending(dev, vector)) {
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141 | 5b5cb086 | Michael S. Tsirkin | msix_clr_pending(dev, vector); |
142 | 5b5cb086 | Michael S. Tsirkin | msix_notify(dev, vector); |
143 | 5b5cb086 | Michael S. Tsirkin | } |
144 | 5b5cb086 | Michael S. Tsirkin | } |
145 | 5b5cb086 | Michael S. Tsirkin | |
146 | 5b5cb086 | Michael S. Tsirkin | /* Handle MSI-X capability config write. */
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147 | 5b5cb086 | Michael S. Tsirkin | void msix_write_config(PCIDevice *dev, uint32_t addr,
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148 | 5b5cb086 | Michael S. Tsirkin | uint32_t val, int len)
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149 | 5b5cb086 | Michael S. Tsirkin | { |
150 | 5b5cb086 | Michael S. Tsirkin | unsigned enable_pos = dev->msix_cap + MSIX_CONTROL_OFFSET;
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151 | 5b5cb086 | Michael S. Tsirkin | int vector;
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152 | 5b5cb086 | Michael S. Tsirkin | |
153 | 98a3cb02 | Isaku Yamahata | if (!range_covers_byte(addr, len, enable_pos)) {
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154 | 5b5cb086 | Michael S. Tsirkin | return;
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155 | 5b5cb086 | Michael S. Tsirkin | } |
156 | 5b5cb086 | Michael S. Tsirkin | |
157 | 5b5cb086 | Michael S. Tsirkin | if (!msix_enabled(dev)) {
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158 | 5b5cb086 | Michael S. Tsirkin | return;
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159 | 5b5cb086 | Michael S. Tsirkin | } |
160 | 5b5cb086 | Michael S. Tsirkin | |
161 | e407bf13 | Isaku Yamahata | pci_device_deassert_intx(dev); |
162 | 5b5cb086 | Michael S. Tsirkin | |
163 | 5b5cb086 | Michael S. Tsirkin | if (msix_function_masked(dev)) {
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164 | 5b5cb086 | Michael S. Tsirkin | return;
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165 | 5b5cb086 | Michael S. Tsirkin | } |
166 | 5b5cb086 | Michael S. Tsirkin | |
167 | 5b5cb086 | Michael S. Tsirkin | for (vector = 0; vector < dev->msix_entries_nr; ++vector) { |
168 | 5b5cb086 | Michael S. Tsirkin | msix_handle_mask_update(dev, vector); |
169 | 5b5cb086 | Michael S. Tsirkin | } |
170 | 02eb84d0 | Michael S. Tsirkin | } |
171 | 02eb84d0 | Michael S. Tsirkin | |
172 | c227f099 | Anthony Liguori | static void msix_mmio_writel(void *opaque, target_phys_addr_t addr, |
173 | 02eb84d0 | Michael S. Tsirkin | uint32_t val) |
174 | 02eb84d0 | Michael S. Tsirkin | { |
175 | 02eb84d0 | Michael S. Tsirkin | PCIDevice *dev = opaque; |
176 | 76f5159d | Michael S. Tsirkin | unsigned int offset = addr & (MSIX_PAGE_SIZE - 1) & ~0x3; |
177 | 01731cfb | Jan Kiszka | int vector = offset / PCI_MSIX_ENTRY_SIZE;
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178 | 76f5159d | Michael S. Tsirkin | pci_set_long(dev->msix_table_page + offset, val); |
179 | 5b5cb086 | Michael S. Tsirkin | msix_handle_mask_update(dev, vector); |
180 | 02eb84d0 | Michael S. Tsirkin | } |
181 | 02eb84d0 | Michael S. Tsirkin | |
182 | c227f099 | Anthony Liguori | static void msix_mmio_write_unallowed(void *opaque, target_phys_addr_t addr, |
183 | 02eb84d0 | Michael S. Tsirkin | uint32_t val) |
184 | 02eb84d0 | Michael S. Tsirkin | { |
185 | 02eb84d0 | Michael S. Tsirkin | fprintf(stderr, "MSI-X: only dword write is allowed!\n");
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186 | 02eb84d0 | Michael S. Tsirkin | } |
187 | 02eb84d0 | Michael S. Tsirkin | |
188 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const msix_mmio_write[] = { |
189 | 02eb84d0 | Michael S. Tsirkin | msix_mmio_write_unallowed, msix_mmio_write_unallowed, msix_mmio_writel |
190 | 02eb84d0 | Michael S. Tsirkin | }; |
191 | 02eb84d0 | Michael S. Tsirkin | |
192 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const msix_mmio_read[] = { |
193 | 02eb84d0 | Michael S. Tsirkin | msix_mmio_read_unallowed, msix_mmio_read_unallowed, msix_mmio_readl |
194 | 02eb84d0 | Michael S. Tsirkin | }; |
195 | 02eb84d0 | Michael S. Tsirkin | |
196 | 02eb84d0 | Michael S. Tsirkin | /* Should be called from device's map method. */
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197 | 02eb84d0 | Michael S. Tsirkin | void msix_mmio_map(PCIDevice *d, int region_num, |
198 | 6e355d90 | Isaku Yamahata | pcibus_t addr, pcibus_t size, int type)
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199 | 02eb84d0 | Michael S. Tsirkin | { |
200 | 02eb84d0 | Michael S. Tsirkin | uint8_t *config = d->config + d->msix_cap; |
201 | 01731cfb | Jan Kiszka | uint32_t table = pci_get_long(config + PCI_MSIX_TABLE); |
202 | 5a1fc5e8 | Michael S. Tsirkin | uint32_t offset = table & ~(MSIX_PAGE_SIZE - 1);
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203 | 02eb84d0 | Michael S. Tsirkin | /* TODO: for assigned devices, we'll want to make it possible to map
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204 | 02eb84d0 | Michael S. Tsirkin | * pending bits separately in case they are in a separate bar. */
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205 | 02eb84d0 | Michael S. Tsirkin | int table_bir = table & PCI_MSIX_FLAGS_BIRMASK;
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206 | 02eb84d0 | Michael S. Tsirkin | |
207 | 02eb84d0 | Michael S. Tsirkin | if (table_bir != region_num)
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208 | 02eb84d0 | Michael S. Tsirkin | return;
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209 | 02eb84d0 | Michael S. Tsirkin | if (size <= offset)
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210 | 02eb84d0 | Michael S. Tsirkin | return;
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211 | 02eb84d0 | Michael S. Tsirkin | cpu_register_physical_memory(addr + offset, size - offset, |
212 | 02eb84d0 | Michael S. Tsirkin | d->msix_mmio_index); |
213 | 02eb84d0 | Michael S. Tsirkin | } |
214 | 02eb84d0 | Michael S. Tsirkin | |
215 | ae1be0bb | Michael S. Tsirkin | static void msix_mask_all(struct PCIDevice *dev, unsigned nentries) |
216 | ae1be0bb | Michael S. Tsirkin | { |
217 | ae1be0bb | Michael S. Tsirkin | int vector;
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218 | ae1be0bb | Michael S. Tsirkin | for (vector = 0; vector < nentries; ++vector) { |
219 | 01731cfb | Jan Kiszka | unsigned offset =
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220 | 01731cfb | Jan Kiszka | vector * PCI_MSIX_ENTRY_SIZE + PCI_MSIX_ENTRY_VECTOR_CTRL; |
221 | 01731cfb | Jan Kiszka | dev->msix_table_page[offset] |= PCI_MSIX_ENTRY_CTRL_MASKBIT; |
222 | ae1be0bb | Michael S. Tsirkin | } |
223 | ae1be0bb | Michael S. Tsirkin | } |
224 | ae1be0bb | Michael S. Tsirkin | |
225 | 02eb84d0 | Michael S. Tsirkin | /* Initialize the MSI-X structures. Note: if MSI-X is supported, BAR size is
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226 | 02eb84d0 | Michael S. Tsirkin | * modified, it should be retrieved with msix_bar_size. */
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227 | 02eb84d0 | Michael S. Tsirkin | int msix_init(struct PCIDevice *dev, unsigned short nentries, |
228 | 5a1fc5e8 | Michael S. Tsirkin | unsigned bar_nr, unsigned bar_size) |
229 | 02eb84d0 | Michael S. Tsirkin | { |
230 | 02eb84d0 | Michael S. Tsirkin | int ret;
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231 | 02eb84d0 | Michael S. Tsirkin | /* Nothing to do if MSI is not supported by interrupt controller */
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232 | 02eb84d0 | Michael S. Tsirkin | if (!msix_supported)
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233 | 02eb84d0 | Michael S. Tsirkin | return -ENOTSUP;
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234 | 02eb84d0 | Michael S. Tsirkin | |
235 | 02eb84d0 | Michael S. Tsirkin | if (nentries > MSIX_MAX_ENTRIES)
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236 | 02eb84d0 | Michael S. Tsirkin | return -EINVAL;
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237 | 02eb84d0 | Michael S. Tsirkin | |
238 | 02eb84d0 | Michael S. Tsirkin | dev->msix_entry_used = qemu_mallocz(MSIX_MAX_ENTRIES * |
239 | 02eb84d0 | Michael S. Tsirkin | sizeof *dev->msix_entry_used);
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240 | 02eb84d0 | Michael S. Tsirkin | |
241 | 5a1fc5e8 | Michael S. Tsirkin | dev->msix_table_page = qemu_mallocz(MSIX_PAGE_SIZE); |
242 | ae1be0bb | Michael S. Tsirkin | msix_mask_all(dev, nentries); |
243 | 02eb84d0 | Michael S. Tsirkin | |
244 | 02eb84d0 | Michael S. Tsirkin | dev->msix_mmio_index = cpu_register_io_memory(msix_mmio_read, |
245 | 2507c12a | Alexander Graf | msix_mmio_write, dev, |
246 | 2507c12a | Alexander Graf | DEVICE_NATIVE_ENDIAN); |
247 | 02eb84d0 | Michael S. Tsirkin | if (dev->msix_mmio_index == -1) { |
248 | 02eb84d0 | Michael S. Tsirkin | ret = -EBUSY; |
249 | 02eb84d0 | Michael S. Tsirkin | goto err_index;
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250 | 02eb84d0 | Michael S. Tsirkin | } |
251 | 02eb84d0 | Michael S. Tsirkin | |
252 | 02eb84d0 | Michael S. Tsirkin | dev->msix_entries_nr = nentries; |
253 | 02eb84d0 | Michael S. Tsirkin | ret = msix_add_config(dev, nentries, bar_nr, bar_size); |
254 | 02eb84d0 | Michael S. Tsirkin | if (ret)
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255 | 02eb84d0 | Michael S. Tsirkin | goto err_config;
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256 | 02eb84d0 | Michael S. Tsirkin | |
257 | 02eb84d0 | Michael S. Tsirkin | dev->cap_present |= QEMU_PCI_CAP_MSIX; |
258 | 02eb84d0 | Michael S. Tsirkin | return 0; |
259 | 02eb84d0 | Michael S. Tsirkin | |
260 | 02eb84d0 | Michael S. Tsirkin | err_config:
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261 | 3174ecd1 | Michael S. Tsirkin | dev->msix_entries_nr = 0;
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262 | 02eb84d0 | Michael S. Tsirkin | cpu_unregister_io_memory(dev->msix_mmio_index); |
263 | 02eb84d0 | Michael S. Tsirkin | err_index:
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264 | 02eb84d0 | Michael S. Tsirkin | qemu_free(dev->msix_table_page); |
265 | 02eb84d0 | Michael S. Tsirkin | dev->msix_table_page = NULL;
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266 | 02eb84d0 | Michael S. Tsirkin | qemu_free(dev->msix_entry_used); |
267 | 02eb84d0 | Michael S. Tsirkin | dev->msix_entry_used = NULL;
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268 | 02eb84d0 | Michael S. Tsirkin | return ret;
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269 | 02eb84d0 | Michael S. Tsirkin | } |
270 | 02eb84d0 | Michael S. Tsirkin | |
271 | 98304c84 | Michael S. Tsirkin | static void msix_free_irq_entries(PCIDevice *dev) |
272 | 98304c84 | Michael S. Tsirkin | { |
273 | 98304c84 | Michael S. Tsirkin | int vector;
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274 | 98304c84 | Michael S. Tsirkin | |
275 | 98304c84 | Michael S. Tsirkin | for (vector = 0; vector < dev->msix_entries_nr; ++vector) { |
276 | 98304c84 | Michael S. Tsirkin | dev->msix_entry_used[vector] = 0;
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277 | 98304c84 | Michael S. Tsirkin | msix_clr_pending(dev, vector); |
278 | 98304c84 | Michael S. Tsirkin | } |
279 | 98304c84 | Michael S. Tsirkin | } |
280 | 98304c84 | Michael S. Tsirkin | |
281 | 02eb84d0 | Michael S. Tsirkin | /* Clean up resources for the device. */
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282 | 02eb84d0 | Michael S. Tsirkin | int msix_uninit(PCIDevice *dev)
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283 | 02eb84d0 | Michael S. Tsirkin | { |
284 | 02eb84d0 | Michael S. Tsirkin | if (!(dev->cap_present & QEMU_PCI_CAP_MSIX))
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285 | 02eb84d0 | Michael S. Tsirkin | return 0; |
286 | 02eb84d0 | Michael S. Tsirkin | pci_del_capability(dev, PCI_CAP_ID_MSIX, MSIX_CAP_LENGTH); |
287 | 02eb84d0 | Michael S. Tsirkin | dev->msix_cap = 0;
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288 | 02eb84d0 | Michael S. Tsirkin | msix_free_irq_entries(dev); |
289 | 02eb84d0 | Michael S. Tsirkin | dev->msix_entries_nr = 0;
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290 | 02eb84d0 | Michael S. Tsirkin | cpu_unregister_io_memory(dev->msix_mmio_index); |
291 | 02eb84d0 | Michael S. Tsirkin | qemu_free(dev->msix_table_page); |
292 | 02eb84d0 | Michael S. Tsirkin | dev->msix_table_page = NULL;
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293 | 02eb84d0 | Michael S. Tsirkin | qemu_free(dev->msix_entry_used); |
294 | 02eb84d0 | Michael S. Tsirkin | dev->msix_entry_used = NULL;
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295 | 02eb84d0 | Michael S. Tsirkin | dev->cap_present &= ~QEMU_PCI_CAP_MSIX; |
296 | 02eb84d0 | Michael S. Tsirkin | return 0; |
297 | 02eb84d0 | Michael S. Tsirkin | } |
298 | 02eb84d0 | Michael S. Tsirkin | |
299 | 02eb84d0 | Michael S. Tsirkin | void msix_save(PCIDevice *dev, QEMUFile *f)
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300 | 02eb84d0 | Michael S. Tsirkin | { |
301 | 9a3e12c8 | Michael S. Tsirkin | unsigned n = dev->msix_entries_nr;
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302 | 9a3e12c8 | Michael S. Tsirkin | |
303 | 72755a70 | Michael S. Tsirkin | if (!(dev->cap_present & QEMU_PCI_CAP_MSIX)) {
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304 | 9a3e12c8 | Michael S. Tsirkin | return;
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305 | 72755a70 | Michael S. Tsirkin | } |
306 | 9a3e12c8 | Michael S. Tsirkin | |
307 | 01731cfb | Jan Kiszka | qemu_put_buffer(f, dev->msix_table_page, n * PCI_MSIX_ENTRY_SIZE); |
308 | 5a1fc5e8 | Michael S. Tsirkin | qemu_put_buffer(f, dev->msix_table_page + MSIX_PAGE_PENDING, (n + 7) / 8); |
309 | 02eb84d0 | Michael S. Tsirkin | } |
310 | 02eb84d0 | Michael S. Tsirkin | |
311 | 02eb84d0 | Michael S. Tsirkin | /* Should be called after restoring the config space. */
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312 | 02eb84d0 | Michael S. Tsirkin | void msix_load(PCIDevice *dev, QEMUFile *f)
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313 | 02eb84d0 | Michael S. Tsirkin | { |
314 | 02eb84d0 | Michael S. Tsirkin | unsigned n = dev->msix_entries_nr;
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315 | 02eb84d0 | Michael S. Tsirkin | |
316 | 98846d73 | Blue Swirl | if (!(dev->cap_present & QEMU_PCI_CAP_MSIX)) {
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317 | 02eb84d0 | Michael S. Tsirkin | return;
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318 | 98846d73 | Blue Swirl | } |
319 | 02eb84d0 | Michael S. Tsirkin | |
320 | 4bfd1712 | Michael S. Tsirkin | msix_free_irq_entries(dev); |
321 | 01731cfb | Jan Kiszka | qemu_get_buffer(f, dev->msix_table_page, n * PCI_MSIX_ENTRY_SIZE); |
322 | 5a1fc5e8 | Michael S. Tsirkin | qemu_get_buffer(f, dev->msix_table_page + MSIX_PAGE_PENDING, (n + 7) / 8); |
323 | 02eb84d0 | Michael S. Tsirkin | } |
324 | 02eb84d0 | Michael S. Tsirkin | |
325 | 02eb84d0 | Michael S. Tsirkin | /* Does device support MSI-X? */
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326 | 02eb84d0 | Michael S. Tsirkin | int msix_present(PCIDevice *dev)
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327 | 02eb84d0 | Michael S. Tsirkin | { |
328 | 02eb84d0 | Michael S. Tsirkin | return dev->cap_present & QEMU_PCI_CAP_MSIX;
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329 | 02eb84d0 | Michael S. Tsirkin | } |
330 | 02eb84d0 | Michael S. Tsirkin | |
331 | 02eb84d0 | Michael S. Tsirkin | /* Is MSI-X enabled? */
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332 | 02eb84d0 | Michael S. Tsirkin | int msix_enabled(PCIDevice *dev)
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333 | 02eb84d0 | Michael S. Tsirkin | { |
334 | 02eb84d0 | Michael S. Tsirkin | return (dev->cap_present & QEMU_PCI_CAP_MSIX) &&
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335 | 2760952b | Michael S. Tsirkin | (dev->config[dev->msix_cap + MSIX_CONTROL_OFFSET] & |
336 | 02eb84d0 | Michael S. Tsirkin | MSIX_ENABLE_MASK); |
337 | 02eb84d0 | Michael S. Tsirkin | } |
338 | 02eb84d0 | Michael S. Tsirkin | |
339 | 02eb84d0 | Michael S. Tsirkin | /* Size of bar where MSI-X table resides, or 0 if MSI-X not supported. */
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340 | 02eb84d0 | Michael S. Tsirkin | uint32_t msix_bar_size(PCIDevice *dev) |
341 | 02eb84d0 | Michael S. Tsirkin | { |
342 | 02eb84d0 | Michael S. Tsirkin | return (dev->cap_present & QEMU_PCI_CAP_MSIX) ?
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343 | 02eb84d0 | Michael S. Tsirkin | dev->msix_bar_size : 0;
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344 | 02eb84d0 | Michael S. Tsirkin | } |
345 | 02eb84d0 | Michael S. Tsirkin | |
346 | 02eb84d0 | Michael S. Tsirkin | /* Send an MSI-X message */
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347 | 02eb84d0 | Michael S. Tsirkin | void msix_notify(PCIDevice *dev, unsigned vector) |
348 | 02eb84d0 | Michael S. Tsirkin | { |
349 | 01731cfb | Jan Kiszka | uint8_t *table_entry = dev->msix_table_page + vector * PCI_MSIX_ENTRY_SIZE; |
350 | 02eb84d0 | Michael S. Tsirkin | uint64_t address; |
351 | 02eb84d0 | Michael S. Tsirkin | uint32_t data; |
352 | 02eb84d0 | Michael S. Tsirkin | |
353 | 02eb84d0 | Michael S. Tsirkin | if (vector >= dev->msix_entries_nr || !dev->msix_entry_used[vector])
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354 | 02eb84d0 | Michael S. Tsirkin | return;
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355 | 02eb84d0 | Michael S. Tsirkin | if (msix_is_masked(dev, vector)) {
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356 | 02eb84d0 | Michael S. Tsirkin | msix_set_pending(dev, vector); |
357 | 02eb84d0 | Michael S. Tsirkin | return;
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358 | 02eb84d0 | Michael S. Tsirkin | } |
359 | 02eb84d0 | Michael S. Tsirkin | |
360 | 01731cfb | Jan Kiszka | address = pci_get_quad(table_entry + PCI_MSIX_ENTRY_LOWER_ADDR); |
361 | 01731cfb | Jan Kiszka | data = pci_get_long(table_entry + PCI_MSIX_ENTRY_DATA); |
362 | ae5d3eb4 | Alexander Graf | stl_le_phys(address, data); |
363 | 02eb84d0 | Michael S. Tsirkin | } |
364 | 02eb84d0 | Michael S. Tsirkin | |
365 | 02eb84d0 | Michael S. Tsirkin | void msix_reset(PCIDevice *dev)
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366 | 02eb84d0 | Michael S. Tsirkin | { |
367 | 02eb84d0 | Michael S. Tsirkin | if (!(dev->cap_present & QEMU_PCI_CAP_MSIX))
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368 | 02eb84d0 | Michael S. Tsirkin | return;
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369 | 02eb84d0 | Michael S. Tsirkin | msix_free_irq_entries(dev); |
370 | 2760952b | Michael S. Tsirkin | dev->config[dev->msix_cap + MSIX_CONTROL_OFFSET] &= |
371 | 2760952b | Michael S. Tsirkin | ~dev->wmask[dev->msix_cap + MSIX_CONTROL_OFFSET]; |
372 | 5a1fc5e8 | Michael S. Tsirkin | memset(dev->msix_table_page, 0, MSIX_PAGE_SIZE);
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373 | ae1be0bb | Michael S. Tsirkin | msix_mask_all(dev, dev->msix_entries_nr); |
374 | 02eb84d0 | Michael S. Tsirkin | } |
375 | 02eb84d0 | Michael S. Tsirkin | |
376 | 02eb84d0 | Michael S. Tsirkin | /* PCI spec suggests that devices make it possible for software to configure
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377 | 02eb84d0 | Michael S. Tsirkin | * less vectors than supported by the device, but does not specify a standard
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378 | 02eb84d0 | Michael S. Tsirkin | * mechanism for devices to do so.
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379 | 02eb84d0 | Michael S. Tsirkin | *
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380 | 02eb84d0 | Michael S. Tsirkin | * We support this by asking devices to declare vectors software is going to
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381 | 02eb84d0 | Michael S. Tsirkin | * actually use, and checking this on the notification path. Devices that
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382 | 02eb84d0 | Michael S. Tsirkin | * don't want to follow the spec suggestion can declare all vectors as used. */
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383 | 02eb84d0 | Michael S. Tsirkin | |
384 | 02eb84d0 | Michael S. Tsirkin | /* Mark vector as used. */
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385 | 02eb84d0 | Michael S. Tsirkin | int msix_vector_use(PCIDevice *dev, unsigned vector) |
386 | 02eb84d0 | Michael S. Tsirkin | { |
387 | 02eb84d0 | Michael S. Tsirkin | if (vector >= dev->msix_entries_nr)
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388 | 02eb84d0 | Michael S. Tsirkin | return -EINVAL;
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389 | 02eb84d0 | Michael S. Tsirkin | dev->msix_entry_used[vector]++; |
390 | 02eb84d0 | Michael S. Tsirkin | return 0; |
391 | 02eb84d0 | Michael S. Tsirkin | } |
392 | 02eb84d0 | Michael S. Tsirkin | |
393 | 02eb84d0 | Michael S. Tsirkin | /* Mark vector as unused. */
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394 | 02eb84d0 | Michael S. Tsirkin | void msix_vector_unuse(PCIDevice *dev, unsigned vector) |
395 | 02eb84d0 | Michael S. Tsirkin | { |
396 | 98304c84 | Michael S. Tsirkin | if (vector >= dev->msix_entries_nr || !dev->msix_entry_used[vector]) {
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397 | 98304c84 | Michael S. Tsirkin | return;
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398 | 98304c84 | Michael S. Tsirkin | } |
399 | 98304c84 | Michael S. Tsirkin | if (--dev->msix_entry_used[vector]) {
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400 | 98304c84 | Michael S. Tsirkin | return;
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401 | 98304c84 | Michael S. Tsirkin | } |
402 | 98304c84 | Michael S. Tsirkin | msix_clr_pending(dev, vector); |
403 | 02eb84d0 | Michael S. Tsirkin | } |
404 | b5f28bca | Michael S. Tsirkin | |
405 | b5f28bca | Michael S. Tsirkin | void msix_unuse_all_vectors(PCIDevice *dev)
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406 | b5f28bca | Michael S. Tsirkin | { |
407 | b5f28bca | Michael S. Tsirkin | if (!(dev->cap_present & QEMU_PCI_CAP_MSIX))
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408 | b5f28bca | Michael S. Tsirkin | return;
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409 | b5f28bca | Michael S. Tsirkin | msix_free_irq_entries(dev); |
410 | b5f28bca | Michael S. Tsirkin | } |