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1 | 87ecb68b | pbrook | #ifndef SUN4M_H
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2 | 87ecb68b | pbrook | #define SUN4M_H
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3 | 87ecb68b | pbrook | |
4 | 87ecb68b | pbrook | /* Devices used by sparc32 system. */
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5 | 87ecb68b | pbrook | |
6 | 87ecb68b | pbrook | /* iommu.c */
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7 | ff403da6 | blueswir1 | void *iommu_init(target_phys_addr_t addr, uint32_t version, qemu_irq irq);
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8 | 87ecb68b | pbrook | void sparc_iommu_memory_rw(void *opaque, target_phys_addr_t addr, |
9 | 87ecb68b | pbrook | uint8_t *buf, int len, int is_write); |
10 | 87ecb68b | pbrook | static inline void sparc_iommu_memory_read(void *opaque, |
11 | 87ecb68b | pbrook | target_phys_addr_t addr, |
12 | 87ecb68b | pbrook | uint8_t *buf, int len)
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13 | 87ecb68b | pbrook | { |
14 | 87ecb68b | pbrook | sparc_iommu_memory_rw(opaque, addr, buf, len, 0);
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15 | 87ecb68b | pbrook | } |
16 | 87ecb68b | pbrook | |
17 | 87ecb68b | pbrook | static inline void sparc_iommu_memory_write(void *opaque, |
18 | 87ecb68b | pbrook | target_phys_addr_t addr, |
19 | 87ecb68b | pbrook | uint8_t *buf, int len)
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20 | 87ecb68b | pbrook | { |
21 | 87ecb68b | pbrook | sparc_iommu_memory_rw(opaque, addr, buf, len, 1);
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22 | 87ecb68b | pbrook | } |
23 | 87ecb68b | pbrook | |
24 | 87ecb68b | pbrook | /* tcx.c */
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25 | 87ecb68b | pbrook | void tcx_init(DisplayState *ds, target_phys_addr_t addr, uint8_t *vram_base,
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26 | 87ecb68b | pbrook | unsigned long vram_offset, int vram_size, int width, int height, |
27 | 87ecb68b | pbrook | int depth);
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28 | 87ecb68b | pbrook | |
29 | 87ecb68b | pbrook | /* slavio_intctl.c */
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30 | 87ecb68b | pbrook | void *slavio_intctl_init(target_phys_addr_t addr, target_phys_addr_t addrg,
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31 | 87ecb68b | pbrook | const uint32_t *intbit_to_level,
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32 | 87ecb68b | pbrook | qemu_irq **irq, qemu_irq **cpu_irq, |
33 | 87ecb68b | pbrook | qemu_irq **parent_irq, unsigned int cputimer); |
34 | 87ecb68b | pbrook | void slavio_pic_info(void *opaque); |
35 | 87ecb68b | pbrook | void slavio_irq_info(void *opaque); |
36 | 87ecb68b | pbrook | |
37 | 7d85892b | blueswir1 | /* sbi.c */
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38 | 7d85892b | blueswir1 | void *sbi_init(target_phys_addr_t addr, qemu_irq **irq, qemu_irq **cpu_irq,
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39 | 7d85892b | blueswir1 | qemu_irq **parent_irq); |
40 | 7d85892b | blueswir1 | |
41 | ee76f82e | blueswir1 | /* sun4c_intctl.c */
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42 | ee76f82e | blueswir1 | void *sun4c_intctl_init(target_phys_addr_t addr, qemu_irq **irq,
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43 | ee76f82e | blueswir1 | qemu_irq *parent_irq); |
44 | 22548760 | blueswir1 | void sun4c_pic_info(void *opaque); |
45 | 22548760 | blueswir1 | void sun4c_irq_info(void *opaque); |
46 | ee76f82e | blueswir1 | |
47 | 87ecb68b | pbrook | /* slavio_timer.c */
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48 | 87ecb68b | pbrook | void slavio_timer_init_all(target_phys_addr_t base, qemu_irq master_irq,
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49 | 19f8e5dd | blueswir1 | qemu_irq *cpu_irqs, unsigned int num_cpus); |
50 | 87ecb68b | pbrook | |
51 | 87ecb68b | pbrook | /* slavio_misc.c */
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52 | 87ecb68b | pbrook | void *slavio_misc_init(target_phys_addr_t base, target_phys_addr_t power_base,
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53 | 0019ad53 | blueswir1 | target_phys_addr_t aux1_base, |
54 | 0019ad53 | blueswir1 | target_phys_addr_t aux2_base, qemu_irq irq, |
55 | 6d0c293d | blueswir1 | qemu_irq cpu_halt, qemu_irq **fdc_tc); |
56 | 87ecb68b | pbrook | void slavio_set_power_fail(void *opaque, int power_failing); |
57 | 87ecb68b | pbrook | |
58 | 87ecb68b | pbrook | /* cs4231.c */
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59 | 87ecb68b | pbrook | void cs_init(target_phys_addr_t base, int irq, void *intctl); |
60 | 87ecb68b | pbrook | |
61 | 87ecb68b | pbrook | /* sparc32_dma.c */
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62 | 216fdffa | blueswir1 | #include "sparc32_dma.h" |
63 | 87ecb68b | pbrook | |
64 | 87ecb68b | pbrook | /* pcnet.c */
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65 | 87ecb68b | pbrook | void lance_init(NICInfo *nd, target_phys_addr_t leaddr, void *dma_opaque, |
66 | 87ecb68b | pbrook | qemu_irq irq, qemu_irq *reset); |
67 | 87ecb68b | pbrook | |
68 | 7eb0c8e8 | blueswir1 | /* eccmemctl.c */
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69 | e42c20b4 | blueswir1 | void *ecc_init(target_phys_addr_t base, qemu_irq irq, uint32_t version);
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70 | 7eb0c8e8 | blueswir1 | |
71 | 87ecb68b | pbrook | #endif |