root / hw / eccmemctl.c @ 75f76531
History | View | Annotate | Download (11.1 kB)
1 |
/*
|
---|---|
2 |
* QEMU Sparc Sun4m ECC memory controller emulation
|
3 |
*
|
4 |
* Copyright (c) 2007 Robert Reif
|
5 |
*
|
6 |
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
7 |
* of this software and associated documentation files (the "Software"), to deal
|
8 |
* in the Software without restriction, including without limitation the rights
|
9 |
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
10 |
* copies of the Software, and to permit persons to whom the Software is
|
11 |
* furnished to do so, subject to the following conditions:
|
12 |
*
|
13 |
* The above copyright notice and this permission notice shall be included in
|
14 |
* all copies or substantial portions of the Software.
|
15 |
*
|
16 |
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
17 |
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
18 |
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
19 |
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
20 |
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
21 |
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
22 |
* THE SOFTWARE.
|
23 |
*/
|
24 |
#include "hw.h" |
25 |
#include "sun4m.h" |
26 |
#include "sysemu.h" |
27 |
|
28 |
//#define DEBUG_ECC
|
29 |
|
30 |
#ifdef DEBUG_ECC
|
31 |
#define DPRINTF(fmt, args...) \
|
32 |
do { printf("ECC: " fmt , ##args); } while (0) |
33 |
#else
|
34 |
#define DPRINTF(fmt, args...)
|
35 |
#endif
|
36 |
|
37 |
/* There are 3 versions of this chip used in SMP sun4m systems:
|
38 |
* MCC (version 0, implementation 0) SS-600MP
|
39 |
* EMC (version 0, implementation 1) SS-10
|
40 |
* SMC (version 0, implementation 2) SS-10SX and SS-20
|
41 |
*/
|
42 |
|
43 |
#define ECC_MCC 0x00000000 |
44 |
#define ECC_EMC 0x10000000 |
45 |
#define ECC_SMC 0x20000000 |
46 |
|
47 |
/* Register indexes */
|
48 |
#define ECC_MER 0 /* Memory Enable Register */ |
49 |
#define ECC_MDR 1 /* Memory Delay Register */ |
50 |
#define ECC_MFSR 2 /* Memory Fault Status Register */ |
51 |
#define ECC_VCR 3 /* Video Configuration Register */ |
52 |
#define ECC_MFAR0 4 /* Memory Fault Address Register 0 */ |
53 |
#define ECC_MFAR1 5 /* Memory Fault Address Register 1 */ |
54 |
#define ECC_DR 6 /* Diagnostic Register */ |
55 |
#define ECC_ECR0 7 /* Event Count Register 0 */ |
56 |
#define ECC_ECR1 8 /* Event Count Register 1 */ |
57 |
|
58 |
/* ECC fault control register */
|
59 |
#define ECC_MER_EE 0x00000001 /* Enable ECC checking */ |
60 |
#define ECC_MER_EI 0x00000002 /* Enable Interrupts on |
61 |
correctable errors */
|
62 |
#define ECC_MER_MRR0 0x00000004 /* SIMM 0 */ |
63 |
#define ECC_MER_MRR1 0x00000008 /* SIMM 1 */ |
64 |
#define ECC_MER_MRR2 0x00000010 /* SIMM 2 */ |
65 |
#define ECC_MER_MRR3 0x00000020 /* SIMM 3 */ |
66 |
#define ECC_MER_MRR4 0x00000040 /* SIMM 4 */ |
67 |
#define ECC_MER_MRR5 0x00000080 /* SIMM 5 */ |
68 |
#define ECC_MER_MRR6 0x00000100 /* SIMM 6 */ |
69 |
#define ECC_MER_MRR7 0x00000200 /* SIMM 7 */ |
70 |
#define ECC_MER_REU 0x00000100 /* Memory Refresh Enable (600MP) */ |
71 |
#define ECC_MER_MRR 0x000003fc /* MRR mask */ |
72 |
#define ECC_MER_A 0x00000400 /* Memory controller addr map select */ |
73 |
#define ECC_MER_DCI 0x00000800 /* Disables Coherent Invalidate ACK */ |
74 |
#define ECC_MER_VER 0x0f000000 /* Version */ |
75 |
#define ECC_MER_IMPL 0xf0000000 /* Implementation */ |
76 |
#define ECC_MER_MASK_0 0x00000103 /* Version 0 (MCC) mask */ |
77 |
#define ECC_MER_MASK_1 0x00000bff /* Version 1 (EMC) mask */ |
78 |
#define ECC_MER_MASK_2 0x00000bff /* Version 2 (SMC) mask */ |
79 |
|
80 |
/* ECC memory delay register */
|
81 |
#define ECC_MDR_RRI 0x000003ff /* Refresh Request Interval */ |
82 |
#define ECC_MDR_MI 0x00001c00 /* MIH Delay */ |
83 |
#define ECC_MDR_CI 0x0000e000 /* Coherent Invalidate Delay */ |
84 |
#define ECC_MDR_MDL 0x001f0000 /* MBus Master arbitration delay */ |
85 |
#define ECC_MDR_MDH 0x03e00000 /* MBus Master arbitration delay */ |
86 |
#define ECC_MDR_GAD 0x7c000000 /* Graphics Arbitration Delay */ |
87 |
#define ECC_MDR_RSC 0x80000000 /* Refresh load control */ |
88 |
#define ECC_MDR_MASK 0x7fffffff |
89 |
|
90 |
/* ECC fault status register */
|
91 |
#define ECC_MFSR_CE 0x00000001 /* Correctable error */ |
92 |
#define ECC_MFSR_BS 0x00000002 /* C2 graphics bad slot access */ |
93 |
#define ECC_MFSR_TO 0x00000004 /* Timeout on write */ |
94 |
#define ECC_MFSR_UE 0x00000008 /* Uncorrectable error */ |
95 |
#define ECC_MFSR_DW 0x000000f0 /* Index of double word in block */ |
96 |
#define ECC_MFSR_SYND 0x0000ff00 /* Syndrome for correctable error */ |
97 |
#define ECC_MFSR_ME 0x00010000 /* Multiple errors */ |
98 |
#define ECC_MFSR_C2ERR 0x00020000 /* C2 graphics error */ |
99 |
|
100 |
/* ECC fault address register 0 */
|
101 |
#define ECC_MFAR0_PADDR 0x0000000f /* PA[32-35] */ |
102 |
#define ECC_MFAR0_TYPE 0x000000f0 /* Transaction type */ |
103 |
#define ECC_MFAR0_SIZE 0x00000700 /* Transaction size */ |
104 |
#define ECC_MFAR0_CACHE 0x00000800 /* Mapped cacheable */ |
105 |
#define ECC_MFAR0_LOCK 0x00001000 /* Error occurred in atomic cycle */ |
106 |
#define ECC_MFAR0_BMODE 0x00002000 /* Boot mode */ |
107 |
#define ECC_MFAR0_VADDR 0x003fc000 /* VA[12-19] (superset bits) */ |
108 |
#define ECC_MFAR0_S 0x08000000 /* Supervisor mode */ |
109 |
#define ECC_MFARO_MID 0xf0000000 /* Module ID */ |
110 |
|
111 |
/* ECC diagnostic register */
|
112 |
#define ECC_DR_CBX 0x00000001 |
113 |
#define ECC_DR_CB0 0x00000002 |
114 |
#define ECC_DR_CB1 0x00000004 |
115 |
#define ECC_DR_CB2 0x00000008 |
116 |
#define ECC_DR_CB4 0x00000010 |
117 |
#define ECC_DR_CB8 0x00000020 |
118 |
#define ECC_DR_CB16 0x00000040 |
119 |
#define ECC_DR_CB32 0x00000080 |
120 |
#define ECC_DR_DMODE 0x00000c00 |
121 |
|
122 |
#define ECC_NREGS 9 |
123 |
#define ECC_SIZE (ECC_NREGS * sizeof(uint32_t)) |
124 |
|
125 |
#define ECC_DIAG_SIZE 4 |
126 |
#define ECC_DIAG_MASK (ECC_DIAG_SIZE - 1) |
127 |
|
128 |
typedef struct ECCState { |
129 |
qemu_irq irq; |
130 |
uint32_t regs[ECC_NREGS]; |
131 |
uint8_t diag[ECC_DIAG_SIZE]; |
132 |
uint32_t version; |
133 |
} ECCState; |
134 |
|
135 |
static void ecc_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val) |
136 |
{ |
137 |
ECCState *s = opaque; |
138 |
|
139 |
switch (addr >> 2) { |
140 |
case ECC_MER:
|
141 |
if (s->version == ECC_MCC)
|
142 |
s->regs[ECC_MER] = (val & ECC_MER_MASK_0); |
143 |
else if (s->version == ECC_EMC) |
144 |
s->regs[ECC_MER] = s->version | (val & ECC_MER_MASK_1); |
145 |
else if (s->version == ECC_SMC) |
146 |
s->regs[ECC_MER] = s->version | (val & ECC_MER_MASK_2); |
147 |
DPRINTF("Write memory enable %08x\n", val);
|
148 |
break;
|
149 |
case ECC_MDR:
|
150 |
s->regs[ECC_MDR] = val & ECC_MDR_MASK; |
151 |
DPRINTF("Write memory delay %08x\n", val);
|
152 |
break;
|
153 |
case ECC_MFSR:
|
154 |
s->regs[ECC_MFSR] = val; |
155 |
qemu_irq_lower(s->irq); |
156 |
DPRINTF("Write memory fault status %08x\n", val);
|
157 |
break;
|
158 |
case ECC_VCR:
|
159 |
s->regs[ECC_VCR] = val; |
160 |
DPRINTF("Write slot configuration %08x\n", val);
|
161 |
break;
|
162 |
case ECC_DR:
|
163 |
s->regs[ECC_DR] = val; |
164 |
DPRINTF("Write diagnostic %08x\n", val);
|
165 |
break;
|
166 |
case ECC_ECR0:
|
167 |
s->regs[ECC_ECR0] = val; |
168 |
DPRINTF("Write event count 1 %08x\n", val);
|
169 |
break;
|
170 |
case ECC_ECR1:
|
171 |
s->regs[ECC_ECR0] = val; |
172 |
DPRINTF("Write event count 2 %08x\n", val);
|
173 |
break;
|
174 |
} |
175 |
} |
176 |
|
177 |
static uint32_t ecc_mem_readl(void *opaque, target_phys_addr_t addr) |
178 |
{ |
179 |
ECCState *s = opaque; |
180 |
uint32_t ret = 0;
|
181 |
|
182 |
switch (addr >> 2) { |
183 |
case ECC_MER:
|
184 |
ret = s->regs[ECC_MER]; |
185 |
DPRINTF("Read memory enable %08x\n", ret);
|
186 |
break;
|
187 |
case ECC_MDR:
|
188 |
ret = s->regs[ECC_MDR]; |
189 |
DPRINTF("Read memory delay %08x\n", ret);
|
190 |
break;
|
191 |
case ECC_MFSR:
|
192 |
ret = s->regs[ECC_MFSR]; |
193 |
DPRINTF("Read memory fault status %08x\n", ret);
|
194 |
break;
|
195 |
case ECC_VCR:
|
196 |
ret = s->regs[ECC_VCR]; |
197 |
DPRINTF("Read slot configuration %08x\n", ret);
|
198 |
break;
|
199 |
case ECC_MFAR0:
|
200 |
ret = s->regs[ECC_MFAR0]; |
201 |
DPRINTF("Read memory fault address 0 %08x\n", ret);
|
202 |
break;
|
203 |
case ECC_MFAR1:
|
204 |
ret = s->regs[ECC_MFAR1]; |
205 |
DPRINTF("Read memory fault address 1 %08x\n", ret);
|
206 |
break;
|
207 |
case ECC_DR:
|
208 |
ret = s->regs[ECC_DR]; |
209 |
DPRINTF("Read diagnostic %08x\n", ret);
|
210 |
break;
|
211 |
case ECC_ECR0:
|
212 |
ret = s->regs[ECC_ECR0]; |
213 |
DPRINTF("Read event count 1 %08x\n", ret);
|
214 |
break;
|
215 |
case ECC_ECR1:
|
216 |
ret = s->regs[ECC_ECR0]; |
217 |
DPRINTF("Read event count 2 %08x\n", ret);
|
218 |
break;
|
219 |
} |
220 |
return ret;
|
221 |
} |
222 |
|
223 |
static CPUReadMemoryFunc *ecc_mem_read[3] = { |
224 |
NULL,
|
225 |
NULL,
|
226 |
ecc_mem_readl, |
227 |
}; |
228 |
|
229 |
static CPUWriteMemoryFunc *ecc_mem_write[3] = { |
230 |
NULL,
|
231 |
NULL,
|
232 |
ecc_mem_writel, |
233 |
}; |
234 |
|
235 |
static void ecc_diag_mem_writeb(void *opaque, target_phys_addr_t addr, |
236 |
uint32_t val) |
237 |
{ |
238 |
ECCState *s = opaque; |
239 |
|
240 |
DPRINTF("Write diagnostic[%d] = %02x\n", (int)addr, val); |
241 |
s->diag[addr & ECC_DIAG_MASK] = val; |
242 |
} |
243 |
|
244 |
static uint32_t ecc_diag_mem_readb(void *opaque, target_phys_addr_t addr) |
245 |
{ |
246 |
ECCState *s = opaque; |
247 |
uint32_t ret = s->diag[(int)addr];
|
248 |
|
249 |
DPRINTF("Read diagnostic[%d] = %02x\n", (int)addr, ret); |
250 |
return ret;
|
251 |
} |
252 |
|
253 |
static CPUReadMemoryFunc *ecc_diag_mem_read[3] = { |
254 |
ecc_diag_mem_readb, |
255 |
NULL,
|
256 |
NULL,
|
257 |
}; |
258 |
|
259 |
static CPUWriteMemoryFunc *ecc_diag_mem_write[3] = { |
260 |
ecc_diag_mem_writeb, |
261 |
NULL,
|
262 |
NULL,
|
263 |
}; |
264 |
|
265 |
static int ecc_load(QEMUFile *f, void *opaque, int version_id) |
266 |
{ |
267 |
ECCState *s = opaque; |
268 |
int i;
|
269 |
|
270 |
if (version_id != 3) |
271 |
return -EINVAL;
|
272 |
|
273 |
for (i = 0; i < ECC_NREGS; i++) |
274 |
qemu_get_be32s(f, &s->regs[i]); |
275 |
|
276 |
for (i = 0; i < ECC_DIAG_SIZE; i++) |
277 |
qemu_get_8s(f, &s->diag[i]); |
278 |
|
279 |
qemu_get_be32s(f, &s->version); |
280 |
|
281 |
return 0; |
282 |
} |
283 |
|
284 |
static void ecc_save(QEMUFile *f, void *opaque) |
285 |
{ |
286 |
ECCState *s = opaque; |
287 |
int i;
|
288 |
|
289 |
for (i = 0; i < ECC_NREGS; i++) |
290 |
qemu_put_be32s(f, &s->regs[i]); |
291 |
|
292 |
for (i = 0; i < ECC_DIAG_SIZE; i++) |
293 |
qemu_put_8s(f, &s->diag[i]); |
294 |
|
295 |
qemu_put_be32s(f, &s->version); |
296 |
} |
297 |
|
298 |
static void ecc_reset(void *opaque) |
299 |
{ |
300 |
ECCState *s = opaque; |
301 |
|
302 |
if (s->version == ECC_MCC)
|
303 |
s->regs[ECC_MER] &= ECC_MER_REU; |
304 |
else
|
305 |
s->regs[ECC_MER] &= (ECC_MER_VER | ECC_MER_IMPL | ECC_MER_MRR | |
306 |
ECC_MER_DCI); |
307 |
s->regs[ECC_MDR] = 0x20;
|
308 |
s->regs[ECC_MFSR] = 0;
|
309 |
s->regs[ECC_VCR] = 0;
|
310 |
s->regs[ECC_MFAR0] = 0x07c00000;
|
311 |
s->regs[ECC_MFAR1] = 0;
|
312 |
s->regs[ECC_DR] = 0;
|
313 |
s->regs[ECC_ECR0] = 0;
|
314 |
s->regs[ECC_ECR1] = 0;
|
315 |
} |
316 |
|
317 |
void * ecc_init(target_phys_addr_t base, qemu_irq irq, uint32_t version)
|
318 |
{ |
319 |
int ecc_io_memory;
|
320 |
ECCState *s; |
321 |
|
322 |
s = qemu_mallocz(sizeof(ECCState));
|
323 |
if (!s)
|
324 |
return NULL; |
325 |
|
326 |
s->version = version; |
327 |
s->regs[0] = version;
|
328 |
s->irq = irq; |
329 |
|
330 |
ecc_io_memory = cpu_register_io_memory(0, ecc_mem_read, ecc_mem_write, s);
|
331 |
cpu_register_physical_memory(base, ECC_SIZE, ecc_io_memory); |
332 |
if (version == ECC_MCC) { // SS-600MP only |
333 |
ecc_io_memory = cpu_register_io_memory(0, ecc_diag_mem_read,
|
334 |
ecc_diag_mem_write, s); |
335 |
cpu_register_physical_memory(base + 0x1000, ECC_DIAG_SIZE,
|
336 |
ecc_io_memory); |
337 |
} |
338 |
register_savevm("ECC", base, 3, ecc_save, ecc_load, s); |
339 |
qemu_register_reset(ecc_reset, s); |
340 |
ecc_reset(s); |
341 |
return s;
|
342 |
} |