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/*
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* QEMU Sun4u/Sun4v System Emulator
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*
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* Copyright (c) 2005 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "hw.h" |
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#include "pci.h" |
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#include "pc.h" |
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#include "nvram.h" |
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#include "fdc.h" |
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#include "net.h" |
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#include "qemu-timer.h" |
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#include "sysemu.h" |
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#include "boards.h" |
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#include "firmware_abi.h" |
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#include "fw_cfg.h" |
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|
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//#define DEBUG_IRQ
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|
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#ifdef DEBUG_IRQ
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#define DPRINTF(fmt, args...) \
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do { printf("CPUIRQ: " fmt , ##args); } while (0) |
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#else
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#define DPRINTF(fmt, args...)
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#endif
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|
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#define KERNEL_LOAD_ADDR 0x00404000 |
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#define CMDLINE_ADDR 0x003ff000 |
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#define INITRD_LOAD_ADDR 0x00300000 |
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#define PROM_SIZE_MAX (4 * 1024 * 1024) |
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#define PROM_VADDR 0x000ffd00000ULL |
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#define APB_SPECIAL_BASE 0x1fe00000000ULL |
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#define APB_MEM_BASE 0x1ff00000000ULL |
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#define VGA_BASE (APB_MEM_BASE + 0x400000ULL) |
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#define PROM_FILENAME "openbios-sparc64" |
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#define NVRAM_SIZE 0x2000 |
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#define MAX_IDE_BUS 2 |
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#define BIOS_CFG_IOPORT 0x510 |
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|
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#define MAX_PILS 16 |
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|
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#define TICK_INT_DIS 0x8000000000000000ULL |
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#define TICK_MAX 0x7fffffffffffffffULL |
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|
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struct hwdef {
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const char * const default_cpu_model; |
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uint16_t machine_id; |
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uint64_t prom_addr; |
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uint64_t console_serial_base; |
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}; |
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|
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int DMA_get_channel_mode (int nchan) |
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{ |
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return 0; |
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} |
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int DMA_read_memory (int nchan, void *buf, int pos, int size) |
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{ |
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return 0; |
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} |
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int DMA_write_memory (int nchan, void *buf, int pos, int size) |
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{ |
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return 0; |
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} |
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void DMA_hold_DREQ (int nchan) {} |
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void DMA_release_DREQ (int nchan) {} |
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void DMA_schedule(int nchan) {} |
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void DMA_init (int high_page_enable) {} |
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void DMA_register_channel (int nchan, |
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DMA_transfer_handler transfer_handler, |
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void *opaque)
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{ |
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} |
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|
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static int nvram_boot_set(void *opaque, const char *boot_device) |
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{ |
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unsigned int i; |
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uint8_t image[sizeof(ohwcfg_v3_t)];
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ohwcfg_v3_t *header = (ohwcfg_v3_t *)ℑ |
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m48t59_t *nvram = (m48t59_t *)opaque; |
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for (i = 0; i < sizeof(image); i++) |
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image[i] = m48t59_read(nvram, i) & 0xff;
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|
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pstrcpy((char *)header->boot_devices, sizeof(header->boot_devices), |
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boot_device); |
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header->nboot_devices = strlen(boot_device) & 0xff;
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header->crc = cpu_to_be16(OHW_compute_crc(header, 0x00, 0xF8)); |
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for (i = 0; i < sizeof(image); i++) |
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m48t59_write(nvram, i, image[i]); |
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return 0; |
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} |
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|
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static int sun4u_NVRAM_set_params (m48t59_t *nvram, uint16_t NVRAM_size, |
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const char *arch, |
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ram_addr_t RAM_size, |
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const char *boot_devices, |
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uint32_t kernel_image, uint32_t kernel_size, |
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const char *cmdline, |
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uint32_t initrd_image, uint32_t initrd_size, |
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uint32_t NVRAM_image, |
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int width, int height, int depth, |
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const uint8_t *macaddr)
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{ |
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unsigned int i; |
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uint32_t start, end; |
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uint8_t image[0x1ff0];
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ohwcfg_v3_t *header = (ohwcfg_v3_t *)ℑ |
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struct sparc_arch_cfg *sparc_header;
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struct OpenBIOS_nvpart_v1 *part_header;
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memset(image, '\0', sizeof(image)); |
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// Try to match PPC NVRAM
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pstrcpy((char *)header->struct_ident, sizeof(header->struct_ident), |
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"QEMU_BIOS");
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header->struct_version = cpu_to_be32(3); /* structure v3 */ |
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header->nvram_size = cpu_to_be16(NVRAM_size); |
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header->nvram_arch_ptr = cpu_to_be16(sizeof(ohwcfg_v3_t));
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header->nvram_arch_size = cpu_to_be16(sizeof(struct sparc_arch_cfg)); |
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pstrcpy((char *)header->arch, sizeof(header->arch), arch); |
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header->nb_cpus = smp_cpus & 0xff;
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header->RAM0_base = 0;
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header->RAM0_size = cpu_to_be64((uint64_t)RAM_size); |
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pstrcpy((char *)header->boot_devices, sizeof(header->boot_devices), |
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boot_devices); |
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header->nboot_devices = strlen(boot_devices) & 0xff;
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header->kernel_image = cpu_to_be64((uint64_t)kernel_image); |
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header->kernel_size = cpu_to_be64((uint64_t)kernel_size); |
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if (cmdline) {
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pstrcpy_targphys(CMDLINE_ADDR, TARGET_PAGE_SIZE, cmdline); |
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header->cmdline = cpu_to_be64((uint64_t)CMDLINE_ADDR); |
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header->cmdline_size = cpu_to_be64((uint64_t)strlen(cmdline)); |
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} |
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header->initrd_image = cpu_to_be64((uint64_t)initrd_image); |
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header->initrd_size = cpu_to_be64((uint64_t)initrd_size); |
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header->NVRAM_image = cpu_to_be64((uint64_t)NVRAM_image); |
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header->width = cpu_to_be16(width); |
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header->height = cpu_to_be16(height); |
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header->depth = cpu_to_be16(depth); |
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if (nographic)
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header->graphic_flags = cpu_to_be16(OHW_GF_NOGRAPHICS); |
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header->crc = cpu_to_be16(OHW_compute_crc(header, 0x00, 0xF8)); |
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// Architecture specific header
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start = sizeof(ohwcfg_v3_t);
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sparc_header = (struct sparc_arch_cfg *)&image[start];
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sparc_header->valid = 0;
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start += sizeof(struct sparc_arch_cfg); |
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// OpenBIOS nvram variables
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// Variable partition
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part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
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part_header->signature = OPENBIOS_PART_SYSTEM; |
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pstrcpy(part_header->name, sizeof(part_header->name), "system"); |
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end = start + sizeof(struct OpenBIOS_nvpart_v1); |
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for (i = 0; i < nb_prom_envs; i++) |
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end = OpenBIOS_set_var(image, end, prom_envs[i]); |
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// End marker
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image[end++] = '\0';
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end = start + ((end - start + 15) & ~15); |
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OpenBIOS_finish_partition(part_header, end - start); |
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// free partition
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start = end; |
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part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
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part_header->signature = OPENBIOS_PART_FREE; |
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pstrcpy(part_header->name, sizeof(part_header->name), "free"); |
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end = 0x1fd0;
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OpenBIOS_finish_partition(part_header, end - start); |
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Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, 0x80); |
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for (i = 0; i < sizeof(image); i++) |
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m48t59_write(nvram, i, image[i]); |
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qemu_register_boot_set(nvram_boot_set, nvram); |
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return 0; |
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} |
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void pic_info(void) |
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{ |
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} |
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void irq_info(void) |
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{ |
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} |
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void cpu_check_irqs(CPUState *env)
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{ |
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uint32_t pil = env->pil_in | (env->softint & ~SOFTINT_TIMER) | |
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((env->softint & SOFTINT_TIMER) << 14);
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if (pil && (env->interrupt_index == 0 || |
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(env->interrupt_index & ~15) == TT_EXTINT)) {
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unsigned int i; |
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for (i = 15; i > 0; i--) { |
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if (pil & (1 << i)) { |
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int old_interrupt = env->interrupt_index;
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env->interrupt_index = TT_EXTINT | i; |
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if (old_interrupt != env->interrupt_index) {
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DPRINTF("Set CPU IRQ %d\n", i);
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cpu_interrupt(env, CPU_INTERRUPT_HARD); |
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} |
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break;
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} |
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} |
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} else if (!pil && (env->interrupt_index & ~15) == TT_EXTINT) { |
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DPRINTF("Reset CPU IRQ %d\n", env->interrupt_index & 15); |
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env->interrupt_index = 0;
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cpu_reset_interrupt(env, CPU_INTERRUPT_HARD); |
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} |
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} |
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static void cpu_set_irq(void *opaque, int irq, int level) |
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{ |
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CPUState *env = opaque; |
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if (level) {
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DPRINTF("Raise CPU IRQ %d\n", irq);
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env->halted = 0;
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env->pil_in |= 1 << irq;
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cpu_check_irqs(env); |
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} else {
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DPRINTF("Lower CPU IRQ %d\n", irq);
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env->pil_in &= ~(1 << irq);
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cpu_check_irqs(env); |
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} |
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} |
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|
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void qemu_system_powerdown(void) |
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{ |
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} |
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|
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typedef struct ResetData { |
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CPUState *env; |
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uint64_t reset_addr; |
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} ResetData; |
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|
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static void main_cpu_reset(void *opaque) |
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{ |
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ResetData *s = (ResetData *)opaque; |
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CPUState *env = s->env; |
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cpu_reset(env); |
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env->tick_cmpr = TICK_INT_DIS | 0;
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ptimer_set_limit(env->tick, TICK_MAX, 1);
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ptimer_run(env->tick, 0);
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env->stick_cmpr = TICK_INT_DIS | 0;
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ptimer_set_limit(env->stick, TICK_MAX, 1);
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ptimer_run(env->stick, 0);
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env->hstick_cmpr = TICK_INT_DIS | 0;
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ptimer_set_limit(env->hstick, TICK_MAX, 1);
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ptimer_run(env->hstick, 0);
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env->gregs[1] = 0; // Memory start |
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env->gregs[2] = ram_size; // Memory size |
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env->gregs[3] = 0; // Machine description XXX |
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env->pc = s->reset_addr; |
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env->npc = env->pc + 4;
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} |
290 |
|
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static void tick_irq(void *opaque) |
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{ |
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CPUState *env = opaque; |
294 |
|
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if (!(env->tick_cmpr & TICK_INT_DIS)) {
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env->softint |= SOFTINT_TIMER; |
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cpu_interrupt(env, CPU_INTERRUPT_TIMER); |
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} |
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} |
300 |
|
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static void stick_irq(void *opaque) |
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{ |
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CPUState *env = opaque; |
304 |
|
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if (!(env->stick_cmpr & TICK_INT_DIS)) {
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env->softint |= SOFTINT_STIMER; |
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cpu_interrupt(env, CPU_INTERRUPT_TIMER); |
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} |
309 |
} |
310 |
|
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static void hstick_irq(void *opaque) |
312 |
{ |
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CPUState *env = opaque; |
314 |
|
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if (!(env->hstick_cmpr & TICK_INT_DIS)) {
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cpu_interrupt(env, CPU_INTERRUPT_TIMER); |
317 |
} |
318 |
} |
319 |
|
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void cpu_tick_set_count(void *opaque, uint64_t count) |
321 |
{ |
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ptimer_set_count(opaque, -count); |
323 |
} |
324 |
|
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uint64_t cpu_tick_get_count(void *opaque)
|
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{ |
327 |
return -ptimer_get_count(opaque);
|
328 |
} |
329 |
|
330 |
void cpu_tick_set_limit(void *opaque, uint64_t limit) |
331 |
{ |
332 |
ptimer_set_limit(opaque, -limit, 0);
|
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} |
334 |
|
335 |
static const int ide_iobase[2] = { 0x1f0, 0x170 }; |
336 |
static const int ide_iobase2[2] = { 0x3f6, 0x376 }; |
337 |
static const int ide_irq[2] = { 14, 15 }; |
338 |
|
339 |
static const int serial_io[MAX_SERIAL_PORTS] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8 }; |
340 |
static const int serial_irq[MAX_SERIAL_PORTS] = { 4, 3, 4, 3 }; |
341 |
|
342 |
static const int parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc }; |
343 |
static const int parallel_irq[MAX_PARALLEL_PORTS] = { 7, 7, 7 }; |
344 |
|
345 |
static fdctrl_t *floppy_controller;
|
346 |
|
347 |
static void ebus_mmio_mapfunc(PCIDevice *pci_dev, int region_num, |
348 |
uint32_t addr, uint32_t size, int type)
|
349 |
{ |
350 |
DPRINTF("Mapping region %d registers at %08x\n", region_num, addr);
|
351 |
switch (region_num) {
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352 |
case 0: |
353 |
isa_mmio_init(addr, 0x1000000);
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354 |
break;
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355 |
case 1: |
356 |
isa_mmio_init(addr, 0x800000);
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357 |
break;
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358 |
} |
359 |
} |
360 |
|
361 |
/* EBUS (Eight bit bus) bridge */
|
362 |
static void |
363 |
pci_ebus_init(PCIBus *bus, int devfn)
|
364 |
{ |
365 |
PCIDevice *s; |
366 |
|
367 |
s = pci_register_device(bus, "EBUS", sizeof(*s), devfn, NULL, NULL); |
368 |
s->config[0x00] = 0x8e; // vendor_id : Sun |
369 |
s->config[0x01] = 0x10; |
370 |
s->config[0x02] = 0x00; // device_id |
371 |
s->config[0x03] = 0x10; |
372 |
s->config[0x04] = 0x06; // command = bus master, pci mem |
373 |
s->config[0x05] = 0x00; |
374 |
s->config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error |
375 |
s->config[0x07] = 0x03; // status = medium devsel |
376 |
s->config[0x08] = 0x01; // revision |
377 |
s->config[0x09] = 0x00; // programming i/f |
378 |
s->config[0x0A] = 0x80; // class_sub = misc bridge |
379 |
s->config[0x0B] = 0x06; // class_base = PCI_bridge |
380 |
s->config[0x0D] = 0x0a; // latency_timer |
381 |
s->config[0x0E] = 0x00; // header_type |
382 |
|
383 |
pci_register_io_region(s, 0, 0x1000000, PCI_ADDRESS_SPACE_MEM, |
384 |
ebus_mmio_mapfunc); |
385 |
pci_register_io_region(s, 1, 0x800000, PCI_ADDRESS_SPACE_MEM, |
386 |
ebus_mmio_mapfunc); |
387 |
} |
388 |
|
389 |
static void sun4uv_init(ram_addr_t RAM_size, int vga_ram_size, |
390 |
const char *boot_devices, DisplayState *ds, |
391 |
const char *kernel_filename, const char *kernel_cmdline, |
392 |
const char *initrd_filename, const char *cpu_model, |
393 |
const struct hwdef *hwdef) |
394 |
{ |
395 |
CPUState *env; |
396 |
char buf[1024]; |
397 |
m48t59_t *nvram; |
398 |
int ret, linux_boot;
|
399 |
unsigned int i; |
400 |
ram_addr_t ram_offset, prom_offset, vga_ram_offset; |
401 |
long initrd_size, kernel_size;
|
402 |
PCIBus *pci_bus, *pci_bus2, *pci_bus3; |
403 |
QEMUBH *bh; |
404 |
qemu_irq *irq; |
405 |
int drive_index;
|
406 |
BlockDriverState *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; |
407 |
BlockDriverState *fd[MAX_FD]; |
408 |
void *fw_cfg;
|
409 |
ResetData *reset_info; |
410 |
|
411 |
linux_boot = (kernel_filename != NULL);
|
412 |
|
413 |
/* init CPUs */
|
414 |
if (!cpu_model)
|
415 |
cpu_model = hwdef->default_cpu_model; |
416 |
|
417 |
env = cpu_init(cpu_model); |
418 |
if (!env) {
|
419 |
fprintf(stderr, "Unable to find Sparc CPU definition\n");
|
420 |
exit(1);
|
421 |
} |
422 |
bh = qemu_bh_new(tick_irq, env); |
423 |
env->tick = ptimer_init(bh); |
424 |
ptimer_set_period(env->tick, 1ULL);
|
425 |
|
426 |
bh = qemu_bh_new(stick_irq, env); |
427 |
env->stick = ptimer_init(bh); |
428 |
ptimer_set_period(env->stick, 1ULL);
|
429 |
|
430 |
bh = qemu_bh_new(hstick_irq, env); |
431 |
env->hstick = ptimer_init(bh); |
432 |
ptimer_set_period(env->hstick, 1ULL);
|
433 |
|
434 |
reset_info = qemu_mallocz(sizeof(ResetData));
|
435 |
reset_info->env = env; |
436 |
reset_info->reset_addr = hwdef->prom_addr + 0x40ULL;
|
437 |
qemu_register_reset(main_cpu_reset, reset_info); |
438 |
main_cpu_reset(reset_info); |
439 |
// Override warm reset address with cold start address
|
440 |
env->pc = hwdef->prom_addr + 0x20ULL;
|
441 |
env->npc = env->pc + 4;
|
442 |
|
443 |
/* allocate RAM */
|
444 |
ram_offset = qemu_ram_alloc(RAM_size); |
445 |
cpu_register_physical_memory(0, RAM_size, ram_offset);
|
446 |
|
447 |
prom_offset = qemu_ram_alloc(PROM_SIZE_MAX); |
448 |
cpu_register_physical_memory(hwdef->prom_addr, |
449 |
(PROM_SIZE_MAX + TARGET_PAGE_SIZE) & |
450 |
TARGET_PAGE_MASK, |
451 |
prom_offset | IO_MEM_ROM); |
452 |
|
453 |
if (bios_name == NULL) |
454 |
bios_name = PROM_FILENAME; |
455 |
snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name); |
456 |
ret = load_elf(buf, hwdef->prom_addr - PROM_VADDR, NULL, NULL, NULL); |
457 |
if (ret < 0) { |
458 |
ret = load_image_targphys(buf, hwdef->prom_addr, |
459 |
(PROM_SIZE_MAX + TARGET_PAGE_SIZE) & |
460 |
TARGET_PAGE_MASK); |
461 |
if (ret < 0) { |
462 |
fprintf(stderr, "qemu: could not load prom '%s'\n",
|
463 |
buf); |
464 |
exit(1);
|
465 |
} |
466 |
} |
467 |
|
468 |
kernel_size = 0;
|
469 |
initrd_size = 0;
|
470 |
if (linux_boot) {
|
471 |
/* XXX: put correct offset */
|
472 |
kernel_size = load_elf(kernel_filename, 0, NULL, NULL, NULL); |
473 |
if (kernel_size < 0) |
474 |
kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR, |
475 |
ram_size - KERNEL_LOAD_ADDR); |
476 |
if (kernel_size < 0) |
477 |
kernel_size = load_image_targphys(kernel_filename, |
478 |
KERNEL_LOAD_ADDR, |
479 |
ram_size - KERNEL_LOAD_ADDR); |
480 |
if (kernel_size < 0) { |
481 |
fprintf(stderr, "qemu: could not load kernel '%s'\n",
|
482 |
kernel_filename); |
483 |
exit(1);
|
484 |
} |
485 |
|
486 |
/* load initrd */
|
487 |
if (initrd_filename) {
|
488 |
initrd_size = load_image_targphys(initrd_filename, |
489 |
INITRD_LOAD_ADDR, |
490 |
ram_size - INITRD_LOAD_ADDR); |
491 |
if (initrd_size < 0) { |
492 |
fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
|
493 |
initrd_filename); |
494 |
exit(1);
|
495 |
} |
496 |
} |
497 |
if (initrd_size > 0) { |
498 |
for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) { |
499 |
if (ldl_phys(KERNEL_LOAD_ADDR + i) == 0x48647253) { // HdrS |
500 |
stl_phys(KERNEL_LOAD_ADDR + i + 16, INITRD_LOAD_ADDR);
|
501 |
stl_phys(KERNEL_LOAD_ADDR + i + 20, initrd_size);
|
502 |
break;
|
503 |
} |
504 |
} |
505 |
} |
506 |
} |
507 |
pci_bus = pci_apb_init(APB_SPECIAL_BASE, APB_MEM_BASE, NULL, &pci_bus2,
|
508 |
&pci_bus3); |
509 |
isa_mem_base = VGA_BASE; |
510 |
vga_ram_offset = qemu_ram_alloc(vga_ram_size); |
511 |
pci_vga_init(pci_bus, ds, phys_ram_base + vga_ram_offset, |
512 |
vga_ram_offset, vga_ram_size, |
513 |
0, 0); |
514 |
|
515 |
// XXX Should be pci_bus3
|
516 |
pci_ebus_init(pci_bus, -1);
|
517 |
|
518 |
i = 0;
|
519 |
if (hwdef->console_serial_base) {
|
520 |
serial_mm_init(hwdef->console_serial_base, 0, NULL, 115200, |
521 |
serial_hds[i], 1);
|
522 |
i++; |
523 |
} |
524 |
for(; i < MAX_SERIAL_PORTS; i++) {
|
525 |
if (serial_hds[i]) {
|
526 |
serial_init(serial_io[i], NULL/*serial_irq[i]*/, 115200, |
527 |
serial_hds[i]); |
528 |
} |
529 |
} |
530 |
|
531 |
for(i = 0; i < MAX_PARALLEL_PORTS; i++) { |
532 |
if (parallel_hds[i]) {
|
533 |
parallel_init(parallel_io[i], NULL/*parallel_irq[i]*/, |
534 |
parallel_hds[i]); |
535 |
} |
536 |
} |
537 |
|
538 |
for(i = 0; i < nb_nics; i++) |
539 |
pci_nic_init(pci_bus, &nd_table[i], -1, "ne2k_pci"); |
540 |
|
541 |
irq = qemu_allocate_irqs(cpu_set_irq, env, MAX_PILS); |
542 |
if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) {
|
543 |
fprintf(stderr, "qemu: too many IDE bus\n");
|
544 |
exit(1);
|
545 |
} |
546 |
for(i = 0; i < MAX_IDE_BUS * MAX_IDE_DEVS; i++) { |
547 |
drive_index = drive_get_index(IF_IDE, i / MAX_IDE_DEVS, |
548 |
i % MAX_IDE_DEVS); |
549 |
if (drive_index != -1) |
550 |
hd[i] = drives_table[drive_index].bdrv; |
551 |
else
|
552 |
hd[i] = NULL;
|
553 |
} |
554 |
|
555 |
// XXX pci_cmd646_ide_init(pci_bus, hd, 1);
|
556 |
pci_piix3_ide_init(pci_bus, hd, -1, irq);
|
557 |
/* FIXME: wire up interrupts. */
|
558 |
i8042_init(NULL/*1*/, NULL/*12*/, 0x60); |
559 |
for(i = 0; i < MAX_FD; i++) { |
560 |
drive_index = drive_get_index(IF_FLOPPY, 0, i);
|
561 |
if (drive_index != -1) |
562 |
fd[i] = drives_table[drive_index].bdrv; |
563 |
else
|
564 |
fd[i] = NULL;
|
565 |
} |
566 |
floppy_controller = fdctrl_init(NULL/*6*/, 2, 0, 0x3f0, fd); |
567 |
nvram = m48t59_init(NULL/*8*/, 0, 0x0074, NVRAM_SIZE, 59); |
568 |
sun4u_NVRAM_set_params(nvram, NVRAM_SIZE, "Sun4u", RAM_size, boot_devices,
|
569 |
KERNEL_LOAD_ADDR, kernel_size, |
570 |
kernel_cmdline, |
571 |
INITRD_LOAD_ADDR, initrd_size, |
572 |
/* XXX: need an option to load a NVRAM image */
|
573 |
0,
|
574 |
graphic_width, graphic_height, graphic_depth, |
575 |
(uint8_t *)&nd_table[0].macaddr);
|
576 |
|
577 |
fw_cfg = fw_cfg_init(BIOS_CFG_IOPORT, BIOS_CFG_IOPORT + 1, 0, 0); |
578 |
fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
|
579 |
fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); |
580 |
fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id); |
581 |
} |
582 |
|
583 |
enum {
|
584 |
sun4u_id = 0,
|
585 |
sun4v_id = 64,
|
586 |
niagara_id, |
587 |
}; |
588 |
|
589 |
static const struct hwdef hwdefs[] = { |
590 |
/* Sun4u generic PC-like machine */
|
591 |
{ |
592 |
.default_cpu_model = "TI UltraSparc II",
|
593 |
.machine_id = sun4u_id, |
594 |
.prom_addr = 0x1fff0000000ULL,
|
595 |
.console_serial_base = 0,
|
596 |
}, |
597 |
/* Sun4v generic PC-like machine */
|
598 |
{ |
599 |
.default_cpu_model = "Sun UltraSparc T1",
|
600 |
.machine_id = sun4v_id, |
601 |
.prom_addr = 0x1fff0000000ULL,
|
602 |
.console_serial_base = 0,
|
603 |
}, |
604 |
/* Sun4v generic Niagara machine */
|
605 |
{ |
606 |
.default_cpu_model = "Sun UltraSparc T1",
|
607 |
.machine_id = niagara_id, |
608 |
.prom_addr = 0xfff0000000ULL,
|
609 |
.console_serial_base = 0xfff0c2c000ULL,
|
610 |
}, |
611 |
}; |
612 |
|
613 |
/* Sun4u hardware initialisation */
|
614 |
static void sun4u_init(ram_addr_t RAM_size, int vga_ram_size, |
615 |
const char *boot_devices, DisplayState *ds, |
616 |
const char *kernel_filename, const char *kernel_cmdline, |
617 |
const char *initrd_filename, const char *cpu_model) |
618 |
{ |
619 |
sun4uv_init(RAM_size, vga_ram_size, boot_devices, ds, kernel_filename, |
620 |
kernel_cmdline, initrd_filename, cpu_model, &hwdefs[0]);
|
621 |
} |
622 |
|
623 |
/* Sun4v hardware initialisation */
|
624 |
static void sun4v_init(ram_addr_t RAM_size, int vga_ram_size, |
625 |
const char *boot_devices, DisplayState *ds, |
626 |
const char *kernel_filename, const char *kernel_cmdline, |
627 |
const char *initrd_filename, const char *cpu_model) |
628 |
{ |
629 |
sun4uv_init(RAM_size, vga_ram_size, boot_devices, ds, kernel_filename, |
630 |
kernel_cmdline, initrd_filename, cpu_model, &hwdefs[1]);
|
631 |
} |
632 |
|
633 |
/* Niagara hardware initialisation */
|
634 |
static void niagara_init(ram_addr_t RAM_size, int vga_ram_size, |
635 |
const char *boot_devices, DisplayState *ds, |
636 |
const char *kernel_filename, const char *kernel_cmdline, |
637 |
const char *initrd_filename, const char *cpu_model) |
638 |
{ |
639 |
sun4uv_init(RAM_size, vga_ram_size, boot_devices, ds, kernel_filename, |
640 |
kernel_cmdline, initrd_filename, cpu_model, &hwdefs[2]);
|
641 |
} |
642 |
|
643 |
QEMUMachine sun4u_machine = { |
644 |
.name = "sun4u",
|
645 |
.desc = "Sun4u platform",
|
646 |
.init = sun4u_init, |
647 |
.ram_require = PROM_SIZE_MAX + VGA_RAM_SIZE, |
648 |
.nodisk_ok = 1,
|
649 |
.max_cpus = 1, // XXX for now |
650 |
}; |
651 |
|
652 |
QEMUMachine sun4v_machine = { |
653 |
.name = "sun4v",
|
654 |
.desc = "Sun4v platform",
|
655 |
.init = sun4v_init, |
656 |
.ram_require = PROM_SIZE_MAX + VGA_RAM_SIZE, |
657 |
.nodisk_ok = 1,
|
658 |
.max_cpus = 1, // XXX for now |
659 |
}; |
660 |
|
661 |
QEMUMachine niagara_machine = { |
662 |
.name = "Niagara",
|
663 |
.desc = "Sun4v platform, Niagara",
|
664 |
.init = niagara_init, |
665 |
.ram_require = PROM_SIZE_MAX + VGA_RAM_SIZE, |
666 |
.nodisk_ok = 1,
|
667 |
.max_cpus = 1, // XXX for now |
668 |
}; |