root / hw / eepro100.c @ 769cf7a5
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/*
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* QEMU i8255x (PRO100) emulation
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*
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* Copyright (c) 2006-2007 Stefan Weil
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*
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* Portions of the code are copies from grub / etherboot eepro100.c
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* and linux e100.c.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see <http://www.gnu.org/licenses/>.
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*
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* Tested features (i82559):
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* PXE boot (i386) no valid link
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* Linux networking (i386) ok
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*
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* Untested:
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* non-i386 platforms
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* Windows networking
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*
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* References:
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*
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* Intel 8255x 10/100 Mbps Ethernet Controller Family
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* Open Source Software Developer Manual
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*/
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#if defined(TARGET_I386)
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# warning "PXE boot still not working!" |
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#endif
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#include <stddef.h> /* offsetof */ |
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#include "hw.h" |
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#include "pci.h" |
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#include "net.h" |
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#include "eeprom93xx.h" |
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/* Common declarations for all PCI devices. */
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#define PCI_CONFIG_8(offset, value) \
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(pci_conf[offset] = (value)) |
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#define PCI_CONFIG_16(offset, value) \
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(*(uint16_t *)&pci_conf[offset] = cpu_to_le16(value)) |
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#define PCI_CONFIG_32(offset, value) \
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(*(uint32_t *)&pci_conf[offset] = cpu_to_le32(value)) |
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#define KiB 1024 |
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/* debug EEPRO100 card */
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//~ #define DEBUG_EEPRO100
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#ifdef DEBUG_EEPRO100
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#define logout(fmt, ...) fprintf(stderr, "EE100\t%-24s" fmt, __func__, ## __VA_ARGS__) |
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#else
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#define logout(fmt, ...) ((void)0) |
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#endif
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/* Set flags to 0 to disable debug output. */
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#define MDI 0 |
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#define TRACE(flag, command) ((flag) ? (command) : (void)0) |
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#define missing(text) assert(!"feature is missing in this emulation: " text) |
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#define MAX_ETH_FRAME_SIZE 1514 |
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/* This driver supports several different devices which are declared here. */
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#define i82551 0x82551 |
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#define i82557B 0x82557b |
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#define i82557C 0x82557c |
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#define i82558B 0x82558b |
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#define i82559C 0x82559c |
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#define i82559ER 0x82559e |
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#define i82562 0x82562 |
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#define EEPROM_SIZE 64 |
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#define PCI_MEM_SIZE (4 * KiB) |
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#define PCI_IO_SIZE 64 |
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#define PCI_FLASH_SIZE (128 * KiB) |
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#define BIT(n) (1 << (n)) |
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#define BITS(n, m) (((0xffffffffU << (31 - n)) >> (31 - n + m)) << m) |
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/* The SCB accepts the following controls for the Tx and Rx units: */
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#define CU_NOP 0x0000 /* No operation. */ |
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#define CU_START 0x0010 /* CU start. */ |
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#define CU_RESUME 0x0020 /* CU resume. */ |
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#define CU_STATSADDR 0x0040 /* Load dump counters address. */ |
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#define CU_SHOWSTATS 0x0050 /* Dump statistical counters. */ |
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#define CU_CMD_BASE 0x0060 /* Load CU base address. */ |
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#define CU_DUMPSTATS 0x0070 /* Dump and reset statistical counters. */ |
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#define CU_SRESUME 0x00a0 /* CU static resume. */ |
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#define RU_NOP 0x0000 |
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#define RX_START 0x0001 |
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#define RX_RESUME 0x0002 |
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#define RX_ABORT 0x0004 |
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#define RX_ADDR_LOAD 0x0006 |
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#define RX_RESUMENR 0x0007 |
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#define INT_MASK 0x0100 |
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#define DRVR_INT 0x0200 /* Driver generated interrupt. */ |
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typedef unsigned char bool; |
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/* Offsets to the various registers.
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All accesses need not be longword aligned. */
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enum speedo_offsets {
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SCBStatus = 0,
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SCBAck = 1,
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SCBCmd = 2, /* Rx/Command Unit command and status. */ |
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SCBIntmask = 3,
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SCBPointer = 4, /* General purpose pointer. */ |
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SCBPort = 8, /* Misc. commands and operands. */ |
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SCBflash = 12, SCBeeprom = 14, /* EEPROM and flash memory control. */ |
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SCBCtrlMDI = 16, /* MDI interface control. */ |
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SCBEarlyRx = 20, /* Early receive byte count. */ |
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SCBFlow = 24,
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}; |
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/* A speedo3 transmit buffer descriptor with two buffers... */
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typedef struct { |
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uint16_t status; |
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uint16_t command; |
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uint32_t link; /* void * */
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uint32_t tx_desc_addr; /* transmit buffer decsriptor array address. */
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uint16_t tcb_bytes; /* transmit command block byte count (in lower 14 bits */
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uint8_t tx_threshold; /* transmit threshold */
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uint8_t tbd_count; /* TBD number */
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//~ /* This constitutes two "TBD" entries: hdr and data */
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//~ uint32_t tx_buf_addr0; /* void *, header of frame to be transmitted. */
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//~ int32_t tx_buf_size0; /* Length of Tx hdr. */
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//~ uint32_t tx_buf_addr1; /* void *, data to be transmitted. */
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//~ int32_t tx_buf_size1; /* Length of Tx data. */
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} eepro100_tx_t; |
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/* Receive frame descriptor. */
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typedef struct { |
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int16_t status; |
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uint16_t command; |
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uint32_t link; /* struct RxFD * */
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uint32_t rx_buf_addr; /* void * */
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uint16_t count; |
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uint16_t size; |
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char packet[MAX_ETH_FRAME_SIZE + 4]; |
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} eepro100_rx_t; |
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typedef struct { |
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uint32_t tx_good_frames, tx_max_collisions, tx_late_collisions, |
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tx_underruns, tx_lost_crs, tx_deferred, tx_single_collisions, |
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tx_multiple_collisions, tx_total_collisions; |
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uint32_t rx_good_frames, rx_crc_errors, rx_alignment_errors, |
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rx_resource_errors, rx_overrun_errors, rx_cdt_errors, |
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rx_short_frame_errors; |
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uint32_t fc_xmt_pause, fc_rcv_pause, fc_rcv_unsupported; |
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uint16_t xmt_tco_frames, rcv_tco_frames; |
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uint32_t complete; |
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} eepro100_stats_t; |
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typedef enum { |
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cu_idle = 0,
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cu_suspended = 1,
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cu_active = 2,
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cu_lpq_active = 2,
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cu_hqp_active = 3
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} cu_state_t; |
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typedef enum { |
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ru_idle = 0,
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ru_suspended = 1,
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ru_no_resources = 2,
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ru_ready = 4
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} ru_state_t; |
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typedef struct { |
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#if 1 |
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uint8_t cmd; |
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uint32_t start; |
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uint32_t stop; |
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uint8_t boundary; |
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uint8_t tsr; |
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uint8_t tpsr; |
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uint16_t tcnt; |
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uint16_t rcnt; |
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uint32_t rsar; |
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uint8_t rsr; |
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uint8_t rxcr; |
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uint8_t isr; |
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uint8_t dcfg; |
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uint8_t imr; |
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uint8_t phys[6]; /* mac address */ |
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uint8_t curpag; |
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uint8_t mult[8]; /* multicast mask array */ |
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int mmio_index;
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PCIDevice *pci_dev; |
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VLANClientState *vc; |
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#endif
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uint8_t scb_stat; /* SCB stat/ack byte */
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uint8_t int_stat; /* PCI interrupt status */
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uint32_t region[3]; /* PCI region addresses */ |
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uint8_t macaddr[6];
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uint32_t statcounter[19];
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uint16_t mdimem[32];
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eeprom_t *eeprom; |
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uint32_t device; /* device variant */
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uint32_t pointer; |
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/* (cu_base + cu_offset) address the next command block in the command block list. */
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uint32_t cu_base; /* CU base address */
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uint32_t cu_offset; /* CU address offset */
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/* (ru_base + ru_offset) address the RFD in the Receive Frame Area. */
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uint32_t ru_base; /* RU base address */
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uint32_t ru_offset; /* RU address offset */
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uint32_t statsaddr; /* pointer to eepro100_stats_t */
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eepro100_stats_t statistics; /* statistical counters */
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#if 0
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uint16_t status;
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#endif
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/* Configuration bytes. */
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uint8_t configuration[22];
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/* Data in mem is always in the byte order of the controller (le). */
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uint8_t mem[PCI_MEM_SIZE]; |
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} EEPRO100State; |
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/* Default values for MDI (PHY) registers */
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static const uint16_t eepro100_mdi_default[] = { |
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/* MDI Registers 0 - 6, 7 */
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0x3000, 0x780d, 0x02a8, 0x0154, 0x05e1, 0x0000, 0x0000, 0x0000, |
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/* MDI Registers 8 - 15 */
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0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, |
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/* MDI Registers 16 - 31 */
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0x0003, 0x0000, 0x0001, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, |
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0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, |
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}; |
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/* Readonly mask for MDI (PHY) registers */
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static const uint16_t eepro100_mdi_mask[] = { |
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0x0000, 0xffff, 0xffff, 0xffff, 0xc01f, 0xffff, 0xffff, 0x0000, |
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0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, |
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0x0fff, 0x0000, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, |
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0xffff, 0xffff, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, |
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}; |
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#define POLYNOMIAL 0x04c11db6 |
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/* From FreeBSD */
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/* XXX: optimize */
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static int compute_mcast_idx(const uint8_t * ep) |
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{ |
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uint32_t crc; |
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int carry, i, j;
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uint8_t b; |
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crc = 0xffffffff;
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for (i = 0; i < 6; i++) { |
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b = *ep++; |
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for (j = 0; j < 8; j++) { |
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carry = ((crc & 0x80000000L) ? 1 : 0) ^ (b & 0x01); |
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crc <<= 1;
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b >>= 1;
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if (carry)
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crc = ((crc ^ POLYNOMIAL) | carry); |
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} |
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} |
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return (crc >> 26); |
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} |
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#if defined(DEBUG_EEPRO100)
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static const char *nic_dump(const uint8_t * buf, unsigned size) |
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{ |
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static char dump[3 * 16 + 1]; |
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char *p = &dump[0]; |
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if (size > 16) |
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size = 16;
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while (size-- > 0) { |
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p += sprintf(p, " %02x", *buf++);
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} |
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return dump;
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} |
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#endif /* DEBUG_EEPRO100 */ |
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enum scb_stat_ack {
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stat_ack_not_ours = 0x00,
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stat_ack_sw_gen = 0x04,
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stat_ack_rnr = 0x10,
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stat_ack_cu_idle = 0x20,
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stat_ack_frame_rx = 0x40,
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stat_ack_cu_cmd_done = 0x80,
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stat_ack_not_present = 0xFF,
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stat_ack_rx = (stat_ack_sw_gen | stat_ack_rnr | stat_ack_frame_rx), |
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stat_ack_tx = (stat_ack_cu_idle | stat_ack_cu_cmd_done), |
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}; |
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static void disable_interrupt(EEPRO100State * s) |
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{ |
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if (s->int_stat) {
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logout("interrupt disabled\n");
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qemu_irq_lower(s->pci_dev->irq[0]);
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s->int_stat = 0;
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} |
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} |
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static void enable_interrupt(EEPRO100State * s) |
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{ |
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if (!s->int_stat) {
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logout("interrupt enabled\n");
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qemu_irq_raise(s->pci_dev->irq[0]);
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s->int_stat = 1;
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} |
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} |
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static void eepro100_acknowledge(EEPRO100State * s) |
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{ |
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s->scb_stat &= ~s->mem[SCBAck]; |
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s->mem[SCBAck] = s->scb_stat; |
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if (s->scb_stat == 0) { |
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disable_interrupt(s); |
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} |
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} |
329 |
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static void eepro100_interrupt(EEPRO100State * s, uint8_t stat) |
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{ |
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uint8_t mask = ~s->mem[SCBIntmask]; |
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s->mem[SCBAck] |= stat; |
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stat = s->scb_stat = s->mem[SCBAck]; |
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stat &= (mask | 0x0f);
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//~ stat &= (~s->mem[SCBIntmask] | 0x0xf);
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if (stat && (mask & 0x01)) { |
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/* SCB mask and SCB Bit M do not disable interrupt. */
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enable_interrupt(s); |
340 |
} else if (s->int_stat) { |
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disable_interrupt(s); |
342 |
} |
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} |
344 |
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static void eepro100_cx_interrupt(EEPRO100State * s) |
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{ |
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/* CU completed action command. */
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/* Transmit not ok (82557 only, not in emulation). */
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eepro100_interrupt(s, 0x80);
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} |
351 |
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static void eepro100_cna_interrupt(EEPRO100State * s) |
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{ |
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/* CU left the active state. */
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eepro100_interrupt(s, 0x20);
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} |
357 |
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static void eepro100_fr_interrupt(EEPRO100State * s) |
359 |
{ |
360 |
/* RU received a complete frame. */
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eepro100_interrupt(s, 0x40);
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} |
363 |
|
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#if 0
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static void eepro100_rnr_interrupt(EEPRO100State * s)
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{
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/* RU is not ready. */
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eepro100_interrupt(s, 0x10);
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}
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#endif
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371 |
|
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static void eepro100_mdi_interrupt(EEPRO100State * s) |
373 |
{ |
374 |
/* MDI completed read or write cycle. */
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eepro100_interrupt(s, 0x08);
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} |
377 |
|
378 |
static void eepro100_swi_interrupt(EEPRO100State * s) |
379 |
{ |
380 |
/* Software has requested an interrupt. */
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eepro100_interrupt(s, 0x04);
|
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} |
383 |
|
384 |
#if 0
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static void eepro100_fcp_interrupt(EEPRO100State * s)
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{
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387 |
/* Flow control pause interrupt (82558 and later). */
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eepro100_interrupt(s, 0x01);
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389 |
}
|
390 |
#endif
|
391 |
|
392 |
static void pci_reset(EEPRO100State * s) |
393 |
{ |
394 |
uint32_t device = s->device; |
395 |
uint8_t *pci_conf = s->pci_dev->config; |
396 |
|
397 |
logout("%p\n", s);
|
398 |
|
399 |
/* PCI Vendor ID */
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400 |
pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL); |
401 |
/* PCI Device ID */
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402 |
pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82551IT); |
403 |
/* PCI Command */
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404 |
PCI_CONFIG_16(PCI_COMMAND, 0x0000);
|
405 |
/* PCI Status */
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406 |
PCI_CONFIG_16(PCI_STATUS, 0x2800);
|
407 |
/* PCI Revision ID */
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408 |
PCI_CONFIG_8(PCI_REVISION_ID, 0x08);
|
409 |
/* PCI Class Code */
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410 |
PCI_CONFIG_8(0x09, 0x00); |
411 |
pci_config_set_class(pci_conf, PCI_CLASS_NETWORK_ETHERNET); |
412 |
/* PCI Cache Line Size */
|
413 |
/* check cache line size!!! */
|
414 |
//~ PCI_CONFIG_8(0x0c, 0x00);
|
415 |
/* PCI Latency Timer */
|
416 |
PCI_CONFIG_8(0x0d, 0x20); // latency timer = 32 clocks |
417 |
/* PCI Header Type */
|
418 |
/* BIST (built-in self test) */
|
419 |
#if defined(TARGET_I386)
|
420 |
// !!! workaround for buggy bios
|
421 |
//~ #define PCI_ADDRESS_SPACE_MEM_PREFETCH 0
|
422 |
#endif
|
423 |
#if 0
|
424 |
/* PCI Base Address Registers */
|
425 |
/* CSR Memory Mapped Base Address */
|
426 |
PCI_CONFIG_32(PCI_BASE_ADDRESS_0,
|
427 |
PCI_ADDRESS_SPACE_MEM | PCI_ADDRESS_SPACE_MEM_PREFETCH);
|
428 |
/* CSR I/O Mapped Base Address */
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429 |
PCI_CONFIG_32(PCI_BASE_ADDRESS_1, PCI_ADDRESS_SPACE_IO);
|
430 |
#if 0
|
431 |
/* Flash Memory Mapped Base Address */
|
432 |
PCI_CONFIG_32(PCI_BASE_ADDRESS_2, 0xfffe0000 | PCI_ADDRESS_SPACE_MEM);
|
433 |
#endif
|
434 |
#endif
|
435 |
/* Expansion ROM Base Address (depends on boot disable!!!) */
|
436 |
PCI_CONFIG_32(0x30, 0x00000000); |
437 |
/* Capability Pointer */
|
438 |
PCI_CONFIG_8(0x34, 0xdc); |
439 |
/* Interrupt Pin */
|
440 |
PCI_CONFIG_8(0x3d, 1); // interrupt pin 0 |
441 |
/* Minimum Grant */
|
442 |
PCI_CONFIG_8(0x3e, 0x08); |
443 |
/* Maximum Latency */
|
444 |
PCI_CONFIG_8(0x3f, 0x18); |
445 |
/* Power Management Capabilities / Next Item Pointer / Capability ID */
|
446 |
PCI_CONFIG_32(0xdc, 0x7e210001); |
447 |
|
448 |
switch (device) {
|
449 |
case i82551:
|
450 |
//~ PCI_CONFIG_16(PCI_DEVICE_ID, 0x1209);
|
451 |
PCI_CONFIG_8(PCI_REVISION_ID, 0x0f);
|
452 |
break;
|
453 |
case i82557B:
|
454 |
PCI_CONFIG_16(PCI_DEVICE_ID, 0x1229);
|
455 |
PCI_CONFIG_8(PCI_REVISION_ID, 0x02);
|
456 |
break;
|
457 |
case i82557C:
|
458 |
PCI_CONFIG_16(PCI_DEVICE_ID, 0x1229);
|
459 |
PCI_CONFIG_8(PCI_REVISION_ID, 0x03);
|
460 |
break;
|
461 |
case i82558B:
|
462 |
PCI_CONFIG_16(PCI_DEVICE_ID, 0x1229);
|
463 |
PCI_CONFIG_16(PCI_STATUS, 0x2810);
|
464 |
PCI_CONFIG_8(PCI_REVISION_ID, 0x05);
|
465 |
break;
|
466 |
case i82559C:
|
467 |
PCI_CONFIG_16(PCI_DEVICE_ID, 0x1229);
|
468 |
PCI_CONFIG_16(PCI_STATUS, 0x2810);
|
469 |
//~ PCI_CONFIG_8(PCI_REVISION_ID, 0x08);
|
470 |
break;
|
471 |
case i82559ER:
|
472 |
//~ PCI_CONFIG_16(PCI_DEVICE_ID, 0x1209);
|
473 |
PCI_CONFIG_16(PCI_STATUS, 0x2810);
|
474 |
PCI_CONFIG_8(PCI_REVISION_ID, 0x09);
|
475 |
break;
|
476 |
//~ PCI_CONFIG_16(PCI_DEVICE_ID, 0x1029);
|
477 |
//~ PCI_CONFIG_16(PCI_DEVICE_ID, 0x1030); /* 82559 InBusiness 10/100 */
|
478 |
default:
|
479 |
logout("Device %X is undefined!\n", device);
|
480 |
} |
481 |
|
482 |
if (device == i82557C || device == i82558B || device == i82559C) {
|
483 |
logout("Get device id and revision from EEPROM!!!\n");
|
484 |
} |
485 |
} |
486 |
|
487 |
static void nic_selective_reset(EEPRO100State * s) |
488 |
{ |
489 |
size_t i; |
490 |
uint16_t *eeprom_contents = eeprom93xx_data(s->eeprom); |
491 |
//~ eeprom93xx_reset(s->eeprom);
|
492 |
memcpy(eeprom_contents, s->macaddr, 6);
|
493 |
eeprom_contents[0xa] = 0x4000; |
494 |
uint16_t sum = 0;
|
495 |
for (i = 0; i < EEPROM_SIZE - 1; i++) { |
496 |
sum += eeprom_contents[i]; |
497 |
} |
498 |
eeprom_contents[EEPROM_SIZE - 1] = 0xbaba - sum; |
499 |
|
500 |
memset(s->mem, 0, sizeof(s->mem)); |
501 |
uint32_t val = BIT(21);
|
502 |
memcpy(&s->mem[SCBCtrlMDI], &val, sizeof(val));
|
503 |
|
504 |
assert(sizeof(s->mdimem) == sizeof(eepro100_mdi_default)); |
505 |
memcpy(&s->mdimem[0], &eepro100_mdi_default[0], sizeof(s->mdimem)); |
506 |
} |
507 |
|
508 |
static void nic_reset(void *opaque) |
509 |
{ |
510 |
EEPRO100State *s = opaque; |
511 |
logout("%p\n", s);
|
512 |
static int first; |
513 |
if (!first) {
|
514 |
first = 1;
|
515 |
} |
516 |
nic_selective_reset(s); |
517 |
} |
518 |
|
519 |
#if defined(DEBUG_EEPRO100)
|
520 |
static const char *reg[PCI_IO_SIZE / 4] = { |
521 |
"Command/Status",
|
522 |
"General Pointer",
|
523 |
"Port",
|
524 |
"EEPROM/Flash Control",
|
525 |
"MDI Control",
|
526 |
"Receive DMA Byte Count",
|
527 |
"Flow control register",
|
528 |
"General Status/Control"
|
529 |
}; |
530 |
|
531 |
static char *regname(uint32_t addr) |
532 |
{ |
533 |
static char buf[16]; |
534 |
if (addr < PCI_IO_SIZE) {
|
535 |
const char *r = reg[addr / 4]; |
536 |
if (r != 0) { |
537 |
sprintf(buf, "%s+%u", r, addr % 4); |
538 |
} else {
|
539 |
sprintf(buf, "0x%02x", addr);
|
540 |
} |
541 |
} else {
|
542 |
sprintf(buf, "??? 0x%08x", addr);
|
543 |
} |
544 |
return buf;
|
545 |
} |
546 |
#endif /* DEBUG_EEPRO100 */ |
547 |
|
548 |
#if 0
|
549 |
static uint16_t eepro100_read_status(EEPRO100State * s)
|
550 |
{
|
551 |
uint16_t val = s->status;
|
552 |
logout("val=0x%04x\n", val);
|
553 |
return val;
|
554 |
}
|
555 |
|
556 |
static void eepro100_write_status(EEPRO100State * s, uint16_t val)
|
557 |
{
|
558 |
logout("val=0x%04x\n", val);
|
559 |
s->status = val;
|
560 |
}
|
561 |
#endif
|
562 |
|
563 |
/*****************************************************************************
|
564 |
*
|
565 |
* Command emulation.
|
566 |
*
|
567 |
****************************************************************************/
|
568 |
|
569 |
#if 0
|
570 |
static uint16_t eepro100_read_command(EEPRO100State * s)
|
571 |
{
|
572 |
uint16_t val = 0xffff;
|
573 |
//~ logout("val=0x%04x\n", val);
|
574 |
return val;
|
575 |
}
|
576 |
#endif
|
577 |
|
578 |
/* Commands that can be put in a command list entry. */
|
579 |
enum commands {
|
580 |
CmdNOp = 0,
|
581 |
CmdIASetup = 1,
|
582 |
CmdConfigure = 2,
|
583 |
CmdMulticastList = 3,
|
584 |
CmdTx = 4,
|
585 |
CmdTDR = 5, /* load microcode */ |
586 |
CmdDump = 6,
|
587 |
CmdDiagnose = 7,
|
588 |
|
589 |
/* And some extra flags: */
|
590 |
CmdSuspend = 0x4000, /* Suspend after completion. */ |
591 |
CmdIntr = 0x2000, /* Interrupt after completion. */ |
592 |
CmdTxFlex = 0x0008, /* Use "Flexible mode" for CmdTx command. */ |
593 |
}; |
594 |
|
595 |
static cu_state_t get_cu_state(EEPRO100State * s)
|
596 |
{ |
597 |
return ((s->mem[SCBStatus] >> 6) & 0x03); |
598 |
} |
599 |
|
600 |
static void set_cu_state(EEPRO100State * s, cu_state_t state) |
601 |
{ |
602 |
s->mem[SCBStatus] = (s->mem[SCBStatus] & 0x3f) + (state << 6); |
603 |
} |
604 |
|
605 |
static ru_state_t get_ru_state(EEPRO100State * s)
|
606 |
{ |
607 |
return ((s->mem[SCBStatus] >> 2) & 0x0f); |
608 |
} |
609 |
|
610 |
static void set_ru_state(EEPRO100State * s, ru_state_t state) |
611 |
{ |
612 |
s->mem[SCBStatus] = (s->mem[SCBStatus] & 0xc3) + (state << 2); |
613 |
} |
614 |
|
615 |
static void dump_statistics(EEPRO100State * s) |
616 |
{ |
617 |
/* Dump statistical data. Most data is never changed by the emulation
|
618 |
* and always 0, so we first just copy the whole block and then those
|
619 |
* values which really matter.
|
620 |
* Number of data should check configuration!!!
|
621 |
*/
|
622 |
cpu_physical_memory_write(s->statsaddr, (uint8_t *) & s->statistics, 64);
|
623 |
stl_phys(s->statsaddr + 0, s->statistics.tx_good_frames);
|
624 |
stl_phys(s->statsaddr + 36, s->statistics.rx_good_frames);
|
625 |
stl_phys(s->statsaddr + 48, s->statistics.rx_resource_errors);
|
626 |
stl_phys(s->statsaddr + 60, s->statistics.rx_short_frame_errors);
|
627 |
//~ stw_phys(s->statsaddr + 76, s->statistics.xmt_tco_frames);
|
628 |
//~ stw_phys(s->statsaddr + 78, s->statistics.rcv_tco_frames);
|
629 |
//~ missing("CU dump statistical counters");
|
630 |
} |
631 |
|
632 |
static void eepro100_cu_command(EEPRO100State * s, uint8_t val) |
633 |
{ |
634 |
eepro100_tx_t tx; |
635 |
uint32_t cb_address; |
636 |
switch (val) {
|
637 |
case CU_NOP:
|
638 |
/* No operation. */
|
639 |
break;
|
640 |
case CU_START:
|
641 |
if (get_cu_state(s) != cu_idle) {
|
642 |
/* Intel documentation says that CU must be idle for the CU
|
643 |
* start command. Intel driver for Linux also starts the CU
|
644 |
* from suspended state. */
|
645 |
logout("CU state is %u, should be %u\n", get_cu_state(s), cu_idle);
|
646 |
//~ assert(!"wrong CU state");
|
647 |
} |
648 |
set_cu_state(s, cu_active); |
649 |
s->cu_offset = s->pointer; |
650 |
next_command:
|
651 |
cb_address = s->cu_base + s->cu_offset; |
652 |
cpu_physical_memory_read(cb_address, (uint8_t *) & tx, sizeof(tx));
|
653 |
uint16_t status = le16_to_cpu(tx.status); |
654 |
uint16_t command = le16_to_cpu(tx.command); |
655 |
logout |
656 |
("val=0x%02x (cu start), status=0x%04x, command=0x%04x, link=0x%08x\n",
|
657 |
val, status, command, tx.link); |
658 |
bool bit_el = ((command & 0x8000) != 0); |
659 |
bool bit_s = ((command & 0x4000) != 0); |
660 |
bool bit_i = ((command & 0x2000) != 0); |
661 |
bool bit_nc = ((command & 0x0010) != 0); |
662 |
//~ bool bit_sf = ((command & 0x0008) != 0);
|
663 |
uint16_t cmd = command & 0x0007;
|
664 |
s->cu_offset = le32_to_cpu(tx.link); |
665 |
switch (cmd) {
|
666 |
case CmdNOp:
|
667 |
/* Do nothing. */
|
668 |
break;
|
669 |
case CmdIASetup:
|
670 |
cpu_physical_memory_read(cb_address + 8, &s->macaddr[0], 6); |
671 |
logout("macaddr: %s\n", nic_dump(&s->macaddr[0], 6)); |
672 |
break;
|
673 |
case CmdConfigure:
|
674 |
cpu_physical_memory_read(cb_address + 8, &s->configuration[0], |
675 |
sizeof(s->configuration));
|
676 |
logout("configuration: %s\n", nic_dump(&s->configuration[0], 16)); |
677 |
break;
|
678 |
case CmdMulticastList:
|
679 |
//~ missing("multicast list");
|
680 |
break;
|
681 |
case CmdTx:
|
682 |
(void)0; |
683 |
uint32_t tbd_array = le32_to_cpu(tx.tx_desc_addr); |
684 |
uint16_t tcb_bytes = (le16_to_cpu(tx.tcb_bytes) & 0x3fff);
|
685 |
logout |
686 |
("transmit, TBD array address 0x%08x, TCB byte count 0x%04x, TBD count %u\n",
|
687 |
tbd_array, tcb_bytes, tx.tbd_count); |
688 |
assert(!bit_nc); |
689 |
//~ assert(!bit_sf);
|
690 |
assert(tcb_bytes <= 2600);
|
691 |
/* Next assertion fails for local configuration. */
|
692 |
//~ assert((tcb_bytes > 0) || (tbd_array != 0xffffffff));
|
693 |
if (!((tcb_bytes > 0) || (tbd_array != 0xffffffff))) { |
694 |
logout |
695 |
("illegal values of TBD array address and TCB byte count!\n");
|
696 |
} |
697 |
// sends larger than MAX_ETH_FRAME_SIZE are allowed, up to 2600 bytes
|
698 |
uint8_t buf[2600];
|
699 |
uint16_t size = 0;
|
700 |
uint32_t tbd_address = cb_address + 0x10;
|
701 |
assert(tcb_bytes <= sizeof(buf));
|
702 |
while (size < tcb_bytes) {
|
703 |
uint32_t tx_buffer_address = ldl_phys(tbd_address); |
704 |
uint16_t tx_buffer_size = lduw_phys(tbd_address + 4);
|
705 |
//~ uint16_t tx_buffer_el = lduw_phys(tbd_address + 6);
|
706 |
tbd_address += 8;
|
707 |
logout |
708 |
("TBD (simplified mode): buffer address 0x%08x, size 0x%04x\n",
|
709 |
tx_buffer_address, tx_buffer_size); |
710 |
tx_buffer_size = MIN(tx_buffer_size, sizeof(buf) - size);
|
711 |
cpu_physical_memory_read(tx_buffer_address, &buf[size], |
712 |
tx_buffer_size); |
713 |
size += tx_buffer_size; |
714 |
} |
715 |
if (tbd_array == 0xffffffff) { |
716 |
/* Simplified mode. Was already handled by code above. */
|
717 |
} else {
|
718 |
/* Flexible mode. */
|
719 |
uint8_t tbd_count = 0;
|
720 |
if ((s->device >= i82558B) && !(s->configuration[6] & BIT(4))) { |
721 |
/* Extended Flexible TCB. */
|
722 |
assert(tcb_bytes == 0);
|
723 |
for (; tbd_count < 2; tbd_count++) { |
724 |
uint32_t tx_buffer_address = ldl_phys(tbd_address); |
725 |
uint16_t tx_buffer_size = lduw_phys(tbd_address + 4);
|
726 |
uint16_t tx_buffer_el = lduw_phys(tbd_address + 6);
|
727 |
tbd_address += 8;
|
728 |
logout |
729 |
("TBD (extended flexible mode): buffer address 0x%08x, size 0x%04x\n",
|
730 |
tx_buffer_address, tx_buffer_size); |
731 |
tx_buffer_size = MIN(tx_buffer_size, sizeof(buf) - size);
|
732 |
cpu_physical_memory_read(tx_buffer_address, &buf[size], |
733 |
tx_buffer_size); |
734 |
size += tx_buffer_size; |
735 |
if (tx_buffer_el & 1) { |
736 |
break;
|
737 |
} |
738 |
} |
739 |
} |
740 |
tbd_address = tbd_array; |
741 |
for (; tbd_count < tx.tbd_count; tbd_count++) {
|
742 |
uint32_t tx_buffer_address = ldl_phys(tbd_address); |
743 |
uint16_t tx_buffer_size = lduw_phys(tbd_address + 4);
|
744 |
uint16_t tx_buffer_el = lduw_phys(tbd_address + 6);
|
745 |
tbd_address += 8;
|
746 |
logout |
747 |
("TBD (flexible mode): buffer address 0x%08x, size 0x%04x\n",
|
748 |
tx_buffer_address, tx_buffer_size); |
749 |
tx_buffer_size = MIN(tx_buffer_size, sizeof(buf) - size);
|
750 |
cpu_physical_memory_read(tx_buffer_address, &buf[size], |
751 |
tx_buffer_size); |
752 |
size += tx_buffer_size; |
753 |
if (tx_buffer_el & 1) { |
754 |
break;
|
755 |
} |
756 |
} |
757 |
} |
758 |
qemu_send_packet(s->vc, buf, size); |
759 |
s->statistics.tx_good_frames++; |
760 |
/* Transmit with bad status would raise an CX/TNO interrupt.
|
761 |
* (82557 only). Emulation never has bad status. */
|
762 |
//~ eepro100_cx_interrupt(s);
|
763 |
break;
|
764 |
case CmdTDR:
|
765 |
logout("load microcode\n");
|
766 |
/* Starting with offset 8, the command contains
|
767 |
* 64 dwords microcode which we just ignore here. */
|
768 |
break;
|
769 |
default:
|
770 |
missing("undefined command");
|
771 |
} |
772 |
/* Write new status (success). */
|
773 |
stw_phys(cb_address, status | 0x8000 | 0x2000); |
774 |
if (bit_i) {
|
775 |
/* CU completed action. */
|
776 |
eepro100_cx_interrupt(s); |
777 |
} |
778 |
if (bit_el) {
|
779 |
/* CU becomes idle. */
|
780 |
set_cu_state(s, cu_idle); |
781 |
eepro100_cna_interrupt(s); |
782 |
} else if (bit_s) { |
783 |
/* CU becomes suspended. */
|
784 |
set_cu_state(s, cu_suspended); |
785 |
eepro100_cna_interrupt(s); |
786 |
} else {
|
787 |
/* More entries in list. */
|
788 |
logout("CU list with at least one more entry\n");
|
789 |
goto next_command;
|
790 |
} |
791 |
logout("CU list empty\n");
|
792 |
/* List is empty. Now CU is idle or suspended. */
|
793 |
break;
|
794 |
case CU_RESUME:
|
795 |
if (get_cu_state(s) != cu_suspended) {
|
796 |
logout("bad CU resume from CU state %u\n", get_cu_state(s));
|
797 |
/* Workaround for bad Linux eepro100 driver which resumes
|
798 |
* from idle state. */
|
799 |
//~ missing("cu resume");
|
800 |
set_cu_state(s, cu_suspended); |
801 |
} |
802 |
if (get_cu_state(s) == cu_suspended) {
|
803 |
logout("CU resuming\n");
|
804 |
set_cu_state(s, cu_active); |
805 |
goto next_command;
|
806 |
} |
807 |
break;
|
808 |
case CU_STATSADDR:
|
809 |
/* Load dump counters address. */
|
810 |
s->statsaddr = s->pointer; |
811 |
logout("val=0x%02x (status address)\n", val);
|
812 |
break;
|
813 |
case CU_SHOWSTATS:
|
814 |
/* Dump statistical counters. */
|
815 |
dump_statistics(s); |
816 |
break;
|
817 |
case CU_CMD_BASE:
|
818 |
/* Load CU base. */
|
819 |
logout("val=0x%02x (CU base address)\n", val);
|
820 |
s->cu_base = s->pointer; |
821 |
break;
|
822 |
case CU_DUMPSTATS:
|
823 |
/* Dump and reset statistical counters. */
|
824 |
dump_statistics(s); |
825 |
memset(&s->statistics, 0, sizeof(s->statistics)); |
826 |
break;
|
827 |
case CU_SRESUME:
|
828 |
/* CU static resume. */
|
829 |
missing("CU static resume");
|
830 |
break;
|
831 |
default:
|
832 |
missing("Undefined CU command");
|
833 |
} |
834 |
} |
835 |
|
836 |
static void eepro100_ru_command(EEPRO100State * s, uint8_t val) |
837 |
{ |
838 |
switch (val) {
|
839 |
case RU_NOP:
|
840 |
/* No operation. */
|
841 |
break;
|
842 |
case RX_START:
|
843 |
/* RU start. */
|
844 |
if (get_ru_state(s) != ru_idle) {
|
845 |
logout("RU state is %u, should be %u\n", get_ru_state(s), ru_idle);
|
846 |
//~ assert(!"wrong RU state");
|
847 |
} |
848 |
set_ru_state(s, ru_ready); |
849 |
s->ru_offset = s->pointer; |
850 |
logout("val=0x%02x (rx start)\n", val);
|
851 |
break;
|
852 |
case RX_RESUME:
|
853 |
/* Restart RU. */
|
854 |
if (get_ru_state(s) != ru_suspended) {
|
855 |
logout("RU state is %u, should be %u\n", get_ru_state(s),
|
856 |
ru_suspended); |
857 |
//~ assert(!"wrong RU state");
|
858 |
} |
859 |
set_ru_state(s, ru_ready); |
860 |
break;
|
861 |
case RX_ADDR_LOAD:
|
862 |
/* Load RU base. */
|
863 |
logout("val=0x%02x (RU base address)\n", val);
|
864 |
s->ru_base = s->pointer; |
865 |
break;
|
866 |
default:
|
867 |
logout("val=0x%02x (undefined RU command)\n", val);
|
868 |
missing("Undefined SU command");
|
869 |
} |
870 |
} |
871 |
|
872 |
static void eepro100_write_command(EEPRO100State * s, uint8_t val) |
873 |
{ |
874 |
eepro100_ru_command(s, val & 0x0f);
|
875 |
eepro100_cu_command(s, val & 0xf0);
|
876 |
if ((val) == 0) { |
877 |
logout("val=0x%02x\n", val);
|
878 |
} |
879 |
/* Clear command byte after command was accepted. */
|
880 |
s->mem[SCBCmd] = 0;
|
881 |
} |
882 |
|
883 |
/*****************************************************************************
|
884 |
*
|
885 |
* EEPROM emulation.
|
886 |
*
|
887 |
****************************************************************************/
|
888 |
|
889 |
#define EEPROM_CS 0x02 |
890 |
#define EEPROM_SK 0x01 |
891 |
#define EEPROM_DI 0x04 |
892 |
#define EEPROM_DO 0x08 |
893 |
|
894 |
static uint16_t eepro100_read_eeprom(EEPRO100State * s)
|
895 |
{ |
896 |
uint16_t val; |
897 |
memcpy(&val, &s->mem[SCBeeprom], sizeof(val));
|
898 |
if (eeprom93xx_read(s->eeprom)) {
|
899 |
val |= EEPROM_DO; |
900 |
} else {
|
901 |
val &= ~EEPROM_DO; |
902 |
} |
903 |
return val;
|
904 |
} |
905 |
|
906 |
static void eepro100_write_eeprom(eeprom_t * eeprom, uint8_t val) |
907 |
{ |
908 |
logout("write val=0x%02x\n", val);
|
909 |
|
910 |
/* mask unwriteable bits */
|
911 |
//~ val = SET_MASKED(val, 0x31, eeprom->value);
|
912 |
|
913 |
int eecs = ((val & EEPROM_CS) != 0); |
914 |
int eesk = ((val & EEPROM_SK) != 0); |
915 |
int eedi = ((val & EEPROM_DI) != 0); |
916 |
eeprom93xx_write(eeprom, eecs, eesk, eedi); |
917 |
} |
918 |
|
919 |
static void eepro100_write_pointer(EEPRO100State * s, uint32_t val) |
920 |
{ |
921 |
s->pointer = le32_to_cpu(val); |
922 |
logout("val=0x%08x\n", val);
|
923 |
} |
924 |
|
925 |
/*****************************************************************************
|
926 |
*
|
927 |
* MDI emulation.
|
928 |
*
|
929 |
****************************************************************************/
|
930 |
|
931 |
#if defined(DEBUG_EEPRO100)
|
932 |
static const char *mdi_op_name[] = { |
933 |
"opcode 0",
|
934 |
"write",
|
935 |
"read",
|
936 |
"opcode 3"
|
937 |
}; |
938 |
|
939 |
static const char *mdi_reg_name[] = { |
940 |
"Control",
|
941 |
"Status",
|
942 |
"PHY Identification (Word 1)",
|
943 |
"PHY Identification (Word 2)",
|
944 |
"Auto-Negotiation Advertisement",
|
945 |
"Auto-Negotiation Link Partner Ability",
|
946 |
"Auto-Negotiation Expansion"
|
947 |
}; |
948 |
#endif /* DEBUG_EEPRO100 */ |
949 |
|
950 |
static uint32_t eepro100_read_mdi(EEPRO100State * s)
|
951 |
{ |
952 |
uint32_t val; |
953 |
memcpy(&val, &s->mem[0x10], sizeof(val)); |
954 |
|
955 |
#ifdef DEBUG_EEPRO100
|
956 |
uint8_t raiseint = (val & BIT(29)) >> 29; |
957 |
uint8_t opcode = (val & BITS(27, 26)) >> 26; |
958 |
uint8_t phy = (val & BITS(25, 21)) >> 21; |
959 |
uint8_t reg = (val & BITS(20, 16)) >> 16; |
960 |
uint16_t data = (val & BITS(15, 0)); |
961 |
#endif
|
962 |
/* Emulation takes no time to finish MDI transaction. */
|
963 |
val |= BIT(28);
|
964 |
TRACE(MDI, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n",
|
965 |
val, raiseint, mdi_op_name[opcode], phy, |
966 |
mdi_reg_name[reg], data)); |
967 |
return val;
|
968 |
} |
969 |
|
970 |
//~ #define BITS(val, upper, lower) (val & ???)
|
971 |
static void eepro100_write_mdi(EEPRO100State * s, uint32_t val) |
972 |
{ |
973 |
uint8_t raiseint = (val & BIT(29)) >> 29; |
974 |
uint8_t opcode = (val & BITS(27, 26)) >> 26; |
975 |
uint8_t phy = (val & BITS(25, 21)) >> 21; |
976 |
uint8_t reg = (val & BITS(20, 16)) >> 16; |
977 |
uint16_t data = (val & BITS(15, 0)); |
978 |
if (phy != 1) { |
979 |
/* Unsupported PHY address. */
|
980 |
//~ logout("phy must be 1 but is %u\n", phy);
|
981 |
data = 0;
|
982 |
} else if (opcode != 1 && opcode != 2) { |
983 |
/* Unsupported opcode. */
|
984 |
logout("opcode must be 1 or 2 but is %u\n", opcode);
|
985 |
data = 0;
|
986 |
} else if (reg > 6) { |
987 |
/* Unsupported register. */
|
988 |
logout("register must be 0...6 but is %u\n", reg);
|
989 |
data = 0;
|
990 |
} else {
|
991 |
TRACE(MDI, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n",
|
992 |
val, raiseint, mdi_op_name[opcode], phy, |
993 |
mdi_reg_name[reg], data)); |
994 |
if (opcode == 1) { |
995 |
/* MDI write */
|
996 |
switch (reg) {
|
997 |
case 0: /* Control Register */ |
998 |
if (data & 0x8000) { |
999 |
/* Reset status and control registers to default. */
|
1000 |
s->mdimem[0] = eepro100_mdi_default[0]; |
1001 |
s->mdimem[1] = eepro100_mdi_default[1]; |
1002 |
data = s->mdimem[reg]; |
1003 |
} else {
|
1004 |
/* Restart Auto Configuration = Normal Operation */
|
1005 |
data &= ~0x0200;
|
1006 |
} |
1007 |
break;
|
1008 |
case 1: /* Status Register */ |
1009 |
missing("not writable");
|
1010 |
data = s->mdimem[reg]; |
1011 |
break;
|
1012 |
case 2: /* PHY Identification Register (Word 1) */ |
1013 |
case 3: /* PHY Identification Register (Word 2) */ |
1014 |
missing("not implemented");
|
1015 |
break;
|
1016 |
case 4: /* Auto-Negotiation Advertisement Register */ |
1017 |
case 5: /* Auto-Negotiation Link Partner Ability Register */ |
1018 |
break;
|
1019 |
case 6: /* Auto-Negotiation Expansion Register */ |
1020 |
default:
|
1021 |
missing("not implemented");
|
1022 |
} |
1023 |
s->mdimem[reg] = data; |
1024 |
} else if (opcode == 2) { |
1025 |
/* MDI read */
|
1026 |
switch (reg) {
|
1027 |
case 0: /* Control Register */ |
1028 |
if (data & 0x8000) { |
1029 |
/* Reset status and control registers to default. */
|
1030 |
s->mdimem[0] = eepro100_mdi_default[0]; |
1031 |
s->mdimem[1] = eepro100_mdi_default[1]; |
1032 |
} |
1033 |
break;
|
1034 |
case 1: /* Status Register */ |
1035 |
s->mdimem[reg] |= 0x0020;
|
1036 |
break;
|
1037 |
case 2: /* PHY Identification Register (Word 1) */ |
1038 |
case 3: /* PHY Identification Register (Word 2) */ |
1039 |
case 4: /* Auto-Negotiation Advertisement Register */ |
1040 |
break;
|
1041 |
case 5: /* Auto-Negotiation Link Partner Ability Register */ |
1042 |
s->mdimem[reg] = 0x41fe;
|
1043 |
break;
|
1044 |
case 6: /* Auto-Negotiation Expansion Register */ |
1045 |
s->mdimem[reg] = 0x0001;
|
1046 |
break;
|
1047 |
} |
1048 |
data = s->mdimem[reg]; |
1049 |
} |
1050 |
/* Emulation takes no time to finish MDI transaction.
|
1051 |
* Set MDI bit in SCB status register. */
|
1052 |
s->mem[SCBAck] |= 0x08;
|
1053 |
val |= BIT(28);
|
1054 |
if (raiseint) {
|
1055 |
eepro100_mdi_interrupt(s); |
1056 |
} |
1057 |
} |
1058 |
val = (val & 0xffff0000) + data;
|
1059 |
memcpy(&s->mem[0x10], &val, sizeof(val)); |
1060 |
} |
1061 |
|
1062 |
/*****************************************************************************
|
1063 |
*
|
1064 |
* Port emulation.
|
1065 |
*
|
1066 |
****************************************************************************/
|
1067 |
|
1068 |
#define PORT_SOFTWARE_RESET 0 |
1069 |
#define PORT_SELFTEST 1 |
1070 |
#define PORT_SELECTIVE_RESET 2 |
1071 |
#define PORT_DUMP 3 |
1072 |
#define PORT_SELECTION_MASK 3 |
1073 |
|
1074 |
typedef struct { |
1075 |
uint32_t st_sign; /* Self Test Signature */
|
1076 |
uint32_t st_result; /* Self Test Results */
|
1077 |
} eepro100_selftest_t; |
1078 |
|
1079 |
static uint32_t eepro100_read_port(EEPRO100State * s)
|
1080 |
{ |
1081 |
return 0; |
1082 |
} |
1083 |
|
1084 |
static void eepro100_write_port(EEPRO100State * s, uint32_t val) |
1085 |
{ |
1086 |
val = le32_to_cpu(val); |
1087 |
uint32_t address = (val & ~PORT_SELECTION_MASK); |
1088 |
uint8_t selection = (val & PORT_SELECTION_MASK); |
1089 |
switch (selection) {
|
1090 |
case PORT_SOFTWARE_RESET:
|
1091 |
nic_reset(s); |
1092 |
break;
|
1093 |
case PORT_SELFTEST:
|
1094 |
logout("selftest address=0x%08x\n", address);
|
1095 |
eepro100_selftest_t data; |
1096 |
cpu_physical_memory_read(address, (uint8_t *) & data, sizeof(data));
|
1097 |
data.st_sign = 0xffffffff;
|
1098 |
data.st_result = 0;
|
1099 |
cpu_physical_memory_write(address, (uint8_t *) & data, sizeof(data));
|
1100 |
break;
|
1101 |
case PORT_SELECTIVE_RESET:
|
1102 |
logout("selective reset, selftest address=0x%08x\n", address);
|
1103 |
nic_selective_reset(s); |
1104 |
break;
|
1105 |
default:
|
1106 |
logout("val=0x%08x\n", val);
|
1107 |
missing("unknown port selection");
|
1108 |
} |
1109 |
} |
1110 |
|
1111 |
/*****************************************************************************
|
1112 |
*
|
1113 |
* General hardware emulation.
|
1114 |
*
|
1115 |
****************************************************************************/
|
1116 |
|
1117 |
static uint8_t eepro100_read1(EEPRO100State * s, uint32_t addr)
|
1118 |
{ |
1119 |
uint8_t val; |
1120 |
if (addr <= sizeof(s->mem) - sizeof(val)) { |
1121 |
memcpy(&val, &s->mem[addr], sizeof(val));
|
1122 |
} |
1123 |
|
1124 |
switch (addr) {
|
1125 |
case SCBStatus:
|
1126 |
//~ val = eepro100_read_status(s);
|
1127 |
logout("addr=%s val=0x%02x\n", regname(addr), val);
|
1128 |
break;
|
1129 |
case SCBAck:
|
1130 |
//~ val = eepro100_read_status(s);
|
1131 |
logout("addr=%s val=0x%02x\n", regname(addr), val);
|
1132 |
break;
|
1133 |
case SCBCmd:
|
1134 |
logout("addr=%s val=0x%02x\n", regname(addr), val);
|
1135 |
//~ val = eepro100_read_command(s);
|
1136 |
break;
|
1137 |
case SCBIntmask:
|
1138 |
logout("addr=%s val=0x%02x\n", regname(addr), val);
|
1139 |
break;
|
1140 |
case SCBPort + 3: |
1141 |
logout("addr=%s val=0x%02x\n", regname(addr), val);
|
1142 |
break;
|
1143 |
case SCBeeprom:
|
1144 |
val = eepro100_read_eeprom(s); |
1145 |
break;
|
1146 |
case 0x1b: /* PMDR (power management driver register) */ |
1147 |
val = 0;
|
1148 |
logout("addr=%s val=0x%02x\n", regname(addr), val);
|
1149 |
break;
|
1150 |
case 0x1d: /* general status register */ |
1151 |
/* 100 Mbps full duplex, valid link */
|
1152 |
val = 0x07;
|
1153 |
logout("addr=General Status val=%02x\n", val);
|
1154 |
break;
|
1155 |
default:
|
1156 |
logout("addr=%s val=0x%02x\n", regname(addr), val);
|
1157 |
missing("unknown byte read");
|
1158 |
} |
1159 |
return val;
|
1160 |
} |
1161 |
|
1162 |
static uint16_t eepro100_read2(EEPRO100State * s, uint32_t addr)
|
1163 |
{ |
1164 |
uint16_t val; |
1165 |
if (addr <= sizeof(s->mem) - sizeof(val)) { |
1166 |
memcpy(&val, &s->mem[addr], sizeof(val));
|
1167 |
} |
1168 |
|
1169 |
logout("addr=%s val=0x%04x\n", regname(addr), val);
|
1170 |
|
1171 |
switch (addr) {
|
1172 |
case SCBStatus:
|
1173 |
//~ val = eepro100_read_status(s);
|
1174 |
break;
|
1175 |
case SCBeeprom:
|
1176 |
val = eepro100_read_eeprom(s); |
1177 |
break;
|
1178 |
default:
|
1179 |
logout("addr=%s val=0x%04x\n", regname(addr), val);
|
1180 |
missing("unknown word read");
|
1181 |
} |
1182 |
return val;
|
1183 |
} |
1184 |
|
1185 |
static uint32_t eepro100_read4(EEPRO100State * s, uint32_t addr)
|
1186 |
{ |
1187 |
uint32_t val; |
1188 |
if (addr <= sizeof(s->mem) - sizeof(val)) { |
1189 |
memcpy(&val, &s->mem[addr], sizeof(val));
|
1190 |
} |
1191 |
|
1192 |
switch (addr) {
|
1193 |
case SCBStatus:
|
1194 |
//~ val = eepro100_read_status(s);
|
1195 |
logout("addr=%s val=0x%08x\n", regname(addr), val);
|
1196 |
break;
|
1197 |
case SCBPointer:
|
1198 |
//~ val = eepro100_read_pointer(s);
|
1199 |
logout("addr=%s val=0x%08x\n", regname(addr), val);
|
1200 |
break;
|
1201 |
case SCBPort:
|
1202 |
val = eepro100_read_port(s); |
1203 |
logout("addr=%s val=0x%08x\n", regname(addr), val);
|
1204 |
break;
|
1205 |
case SCBCtrlMDI:
|
1206 |
val = eepro100_read_mdi(s); |
1207 |
break;
|
1208 |
default:
|
1209 |
logout("addr=%s val=0x%08x\n", regname(addr), val);
|
1210 |
missing("unknown longword read");
|
1211 |
} |
1212 |
return val;
|
1213 |
} |
1214 |
|
1215 |
static void eepro100_write1(EEPRO100State * s, uint32_t addr, uint8_t val) |
1216 |
{ |
1217 |
if (addr <= sizeof(s->mem) - sizeof(val)) { |
1218 |
memcpy(&s->mem[addr], &val, sizeof(val));
|
1219 |
} |
1220 |
|
1221 |
logout("addr=%s val=0x%02x\n", regname(addr), val);
|
1222 |
|
1223 |
switch (addr) {
|
1224 |
case SCBStatus:
|
1225 |
//~ eepro100_write_status(s, val);
|
1226 |
break;
|
1227 |
case SCBAck:
|
1228 |
eepro100_acknowledge(s); |
1229 |
break;
|
1230 |
case SCBCmd:
|
1231 |
eepro100_write_command(s, val); |
1232 |
break;
|
1233 |
case SCBIntmask:
|
1234 |
if (val & BIT(1)) { |
1235 |
eepro100_swi_interrupt(s); |
1236 |
} |
1237 |
eepro100_interrupt(s, 0);
|
1238 |
break;
|
1239 |
case SCBPort + 3: |
1240 |
case SCBFlow:
|
1241 |
case SCBFlow + 1: |
1242 |
case SCBFlow + 2: |
1243 |
case SCBFlow + 3: |
1244 |
logout("addr=%s val=0x%02x\n", regname(addr), val);
|
1245 |
break;
|
1246 |
case SCBeeprom:
|
1247 |
eepro100_write_eeprom(s->eeprom, val); |
1248 |
break;
|
1249 |
default:
|
1250 |
logout("addr=%s val=0x%02x\n", regname(addr), val);
|
1251 |
missing("unknown byte write");
|
1252 |
} |
1253 |
} |
1254 |
|
1255 |
static void eepro100_write2(EEPRO100State * s, uint32_t addr, uint16_t val) |
1256 |
{ |
1257 |
if (addr <= sizeof(s->mem) - sizeof(val)) { |
1258 |
memcpy(&s->mem[addr], &val, sizeof(val));
|
1259 |
} |
1260 |
|
1261 |
logout("addr=%s val=0x%04x\n", regname(addr), val);
|
1262 |
|
1263 |
switch (addr) {
|
1264 |
case SCBStatus:
|
1265 |
//~ eepro100_write_status(s, val);
|
1266 |
eepro100_acknowledge(s); |
1267 |
break;
|
1268 |
case SCBCmd:
|
1269 |
eepro100_write_command(s, val); |
1270 |
eepro100_write1(s, SCBIntmask, val >> 8);
|
1271 |
break;
|
1272 |
case SCBeeprom:
|
1273 |
eepro100_write_eeprom(s->eeprom, val); |
1274 |
break;
|
1275 |
default:
|
1276 |
logout("addr=%s val=0x%04x\n", regname(addr), val);
|
1277 |
missing("unknown word write");
|
1278 |
} |
1279 |
} |
1280 |
|
1281 |
static void eepro100_write4(EEPRO100State * s, uint32_t addr, uint32_t val) |
1282 |
{ |
1283 |
if (addr <= sizeof(s->mem) - sizeof(val)) { |
1284 |
memcpy(&s->mem[addr], &val, sizeof(val));
|
1285 |
} |
1286 |
|
1287 |
switch (addr) {
|
1288 |
case SCBPointer:
|
1289 |
eepro100_write_pointer(s, val); |
1290 |
break;
|
1291 |
case SCBPort:
|
1292 |
logout("addr=%s val=0x%08x\n", regname(addr), val);
|
1293 |
eepro100_write_port(s, val); |
1294 |
break;
|
1295 |
case SCBCtrlMDI:
|
1296 |
eepro100_write_mdi(s, val); |
1297 |
break;
|
1298 |
default:
|
1299 |
logout("addr=%s val=0x%08x\n", regname(addr), val);
|
1300 |
missing("unknown longword write");
|
1301 |
} |
1302 |
} |
1303 |
|
1304 |
static uint32_t ioport_read1(void *opaque, uint32_t addr) |
1305 |
{ |
1306 |
EEPRO100State *s = opaque; |
1307 |
//~ logout("addr=%s\n", regname(addr));
|
1308 |
return eepro100_read1(s, addr - s->region[1]); |
1309 |
} |
1310 |
|
1311 |
static uint32_t ioport_read2(void *opaque, uint32_t addr) |
1312 |
{ |
1313 |
EEPRO100State *s = opaque; |
1314 |
return eepro100_read2(s, addr - s->region[1]); |
1315 |
} |
1316 |
|
1317 |
static uint32_t ioport_read4(void *opaque, uint32_t addr) |
1318 |
{ |
1319 |
EEPRO100State *s = opaque; |
1320 |
return eepro100_read4(s, addr - s->region[1]); |
1321 |
} |
1322 |
|
1323 |
static void ioport_write1(void *opaque, uint32_t addr, uint32_t val) |
1324 |
{ |
1325 |
EEPRO100State *s = opaque; |
1326 |
//~ logout("addr=%s val=0x%02x\n", regname(addr), val);
|
1327 |
eepro100_write1(s, addr - s->region[1], val);
|
1328 |
} |
1329 |
|
1330 |
static void ioport_write2(void *opaque, uint32_t addr, uint32_t val) |
1331 |
{ |
1332 |
EEPRO100State *s = opaque; |
1333 |
eepro100_write2(s, addr - s->region[1], val);
|
1334 |
} |
1335 |
|
1336 |
static void ioport_write4(void *opaque, uint32_t addr, uint32_t val) |
1337 |
{ |
1338 |
EEPRO100State *s = opaque; |
1339 |
eepro100_write4(s, addr - s->region[1], val);
|
1340 |
} |
1341 |
|
1342 |
/***********************************************************/
|
1343 |
/* PCI EEPRO100 definitions */
|
1344 |
|
1345 |
typedef struct PCIEEPRO100State { |
1346 |
PCIDevice dev; |
1347 |
EEPRO100State eepro100; |
1348 |
} PCIEEPRO100State; |
1349 |
|
1350 |
static void pci_map(PCIDevice * pci_dev, int region_num, |
1351 |
uint32_t addr, uint32_t size, int type)
|
1352 |
{ |
1353 |
PCIEEPRO100State *d = DO_UPCAST(PCIEEPRO100State, dev, pci_dev); |
1354 |
EEPRO100State *s = &d->eepro100; |
1355 |
|
1356 |
logout("region %d, addr=0x%08x, size=0x%08x, type=%d\n",
|
1357 |
region_num, addr, size, type); |
1358 |
|
1359 |
assert(region_num == 1);
|
1360 |
register_ioport_write(addr, size, 1, ioport_write1, s);
|
1361 |
register_ioport_read(addr, size, 1, ioport_read1, s);
|
1362 |
register_ioport_write(addr, size, 2, ioport_write2, s);
|
1363 |
register_ioport_read(addr, size, 2, ioport_read2, s);
|
1364 |
register_ioport_write(addr, size, 4, ioport_write4, s);
|
1365 |
register_ioport_read(addr, size, 4, ioport_read4, s);
|
1366 |
|
1367 |
s->region[region_num] = addr; |
1368 |
} |
1369 |
|
1370 |
static void pci_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) |
1371 |
{ |
1372 |
EEPRO100State *s = opaque; |
1373 |
//~ logout("addr=%s val=0x%02x\n", regname(addr), val);
|
1374 |
eepro100_write1(s, addr, val); |
1375 |
} |
1376 |
|
1377 |
static void pci_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val) |
1378 |
{ |
1379 |
EEPRO100State *s = opaque; |
1380 |
//~ logout("addr=%s val=0x%02x\n", regname(addr), val);
|
1381 |
eepro100_write2(s, addr, val); |
1382 |
} |
1383 |
|
1384 |
static void pci_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val) |
1385 |
{ |
1386 |
EEPRO100State *s = opaque; |
1387 |
//~ logout("addr=%s val=0x%02x\n", regname(addr), val);
|
1388 |
eepro100_write4(s, addr, val); |
1389 |
} |
1390 |
|
1391 |
static uint32_t pci_mmio_readb(void *opaque, target_phys_addr_t addr) |
1392 |
{ |
1393 |
EEPRO100State *s = opaque; |
1394 |
//~ logout("addr=%s\n", regname(addr));
|
1395 |
return eepro100_read1(s, addr);
|
1396 |
} |
1397 |
|
1398 |
static uint32_t pci_mmio_readw(void *opaque, target_phys_addr_t addr) |
1399 |
{ |
1400 |
EEPRO100State *s = opaque; |
1401 |
//~ logout("addr=%s\n", regname(addr));
|
1402 |
return eepro100_read2(s, addr);
|
1403 |
} |
1404 |
|
1405 |
static uint32_t pci_mmio_readl(void *opaque, target_phys_addr_t addr) |
1406 |
{ |
1407 |
EEPRO100State *s = opaque; |
1408 |
//~ logout("addr=%s\n", regname(addr));
|
1409 |
return eepro100_read4(s, addr);
|
1410 |
} |
1411 |
|
1412 |
static CPUWriteMemoryFunc * const pci_mmio_write[] = { |
1413 |
pci_mmio_writeb, |
1414 |
pci_mmio_writew, |
1415 |
pci_mmio_writel |
1416 |
}; |
1417 |
|
1418 |
static CPUReadMemoryFunc * const pci_mmio_read[] = { |
1419 |
pci_mmio_readb, |
1420 |
pci_mmio_readw, |
1421 |
pci_mmio_readl |
1422 |
}; |
1423 |
|
1424 |
static void pci_mmio_map(PCIDevice * pci_dev, int region_num, |
1425 |
uint32_t addr, uint32_t size, int type)
|
1426 |
{ |
1427 |
PCIEEPRO100State *d = DO_UPCAST(PCIEEPRO100State, dev, pci_dev); |
1428 |
|
1429 |
logout("region %d, addr=0x%08x, size=0x%08x, type=%d\n",
|
1430 |
region_num, addr, size, type); |
1431 |
|
1432 |
if (region_num == 0) { |
1433 |
/* Map control / status registers. */
|
1434 |
cpu_register_physical_memory(addr, size, d->eepro100.mmio_index); |
1435 |
d->eepro100.region[region_num] = addr; |
1436 |
} |
1437 |
} |
1438 |
|
1439 |
static int nic_can_receive(VLANClientState *vc) |
1440 |
{ |
1441 |
EEPRO100State *s = vc->opaque; |
1442 |
logout("%p\n", s);
|
1443 |
return get_ru_state(s) == ru_ready;
|
1444 |
//~ return !eepro100_buffer_full(s);
|
1445 |
} |
1446 |
|
1447 |
static ssize_t nic_receive(VLANClientState *vc, const uint8_t * buf, size_t size) |
1448 |
{ |
1449 |
/* TODO:
|
1450 |
* - Magic packets should set bit 30 in power management driver register.
|
1451 |
* - Interesting packets should set bit 29 in power management driver register.
|
1452 |
*/
|
1453 |
EEPRO100State *s = vc->opaque; |
1454 |
uint16_t rfd_status = 0xa000;
|
1455 |
static const uint8_t broadcast_macaddr[6] = |
1456 |
{ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; |
1457 |
|
1458 |
/* TODO: check multiple IA bit. */
|
1459 |
assert(!(s->configuration[20] & BIT(6))); |
1460 |
|
1461 |
if (s->configuration[8] & 0x80) { |
1462 |
/* CSMA is disabled. */
|
1463 |
logout("%p received while CSMA is disabled\n", s);
|
1464 |
return -1; |
1465 |
} else if (size < 64 && (s->configuration[7] & 1)) { |
1466 |
/* Short frame and configuration byte 7/0 (discard short receive) set:
|
1467 |
* Short frame is discarded */
|
1468 |
logout("%p received short frame (%d byte)\n", s, size);
|
1469 |
s->statistics.rx_short_frame_errors++; |
1470 |
//~ return -1;
|
1471 |
} else if ((size > MAX_ETH_FRAME_SIZE + 4) && !(s->configuration[18] & 8)) { |
1472 |
/* Long frame and configuration byte 18/3 (long receive ok) not set:
|
1473 |
* Long frames are discarded. */
|
1474 |
logout("%p received long frame (%d byte), ignored\n", s, size);
|
1475 |
return -1; |
1476 |
} else if (memcmp(buf, s->macaddr, 6) == 0) { // !!! |
1477 |
/* Frame matches individual address. */
|
1478 |
/* TODO: check configuration byte 15/4 (ignore U/L). */
|
1479 |
logout("%p received frame for me, len=%d\n", s, size);
|
1480 |
} else if (memcmp(buf, broadcast_macaddr, 6) == 0) { |
1481 |
/* Broadcast frame. */
|
1482 |
logout("%p received broadcast, len=%d\n", s, size);
|
1483 |
rfd_status |= 0x0002;
|
1484 |
} else if (buf[0] & 0x01) { // !!! |
1485 |
/* Multicast frame. */
|
1486 |
logout("%p received multicast, len=%d\n", s, size);
|
1487 |
/* TODO: check multicast all bit. */
|
1488 |
assert(!(s->configuration[21] & BIT(3))); |
1489 |
int mcast_idx = compute_mcast_idx(buf);
|
1490 |
if (!(s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7)))) { |
1491 |
return size;
|
1492 |
} |
1493 |
rfd_status |= 0x0002;
|
1494 |
} else if (s->configuration[15] & 1) { |
1495 |
/* Promiscuous: receive all. */
|
1496 |
logout("%p received frame in promiscuous mode, len=%d\n", s, size);
|
1497 |
rfd_status |= 0x0004;
|
1498 |
} else {
|
1499 |
logout("%p received frame, ignored, len=%d,%s\n", s, size,
|
1500 |
nic_dump(buf, size)); |
1501 |
return size;
|
1502 |
} |
1503 |
|
1504 |
if (get_ru_state(s) != ru_ready) {
|
1505 |
/* No ressources available. */
|
1506 |
logout("no ressources, state=%u\n", get_ru_state(s));
|
1507 |
s->statistics.rx_resource_errors++; |
1508 |
//~ assert(!"no ressources");
|
1509 |
return -1; |
1510 |
} |
1511 |
//~ !!!
|
1512 |
//~ $3 = {status = 0x0, command = 0xc000, link = 0x2d220, rx_buf_addr = 0x207dc, count = 0x0, size = 0x5f8, packet = {0x0 <repeats 1518 times>}}
|
1513 |
eepro100_rx_t rx; |
1514 |
cpu_physical_memory_read(s->ru_base + s->ru_offset, (uint8_t *) & rx, |
1515 |
offsetof(eepro100_rx_t, packet)); |
1516 |
uint16_t rfd_command = le16_to_cpu(rx.command); |
1517 |
uint16_t rfd_size = le16_to_cpu(rx.size); |
1518 |
assert(size <= rfd_size); |
1519 |
if (size < 64) { |
1520 |
rfd_status |= 0x0080;
|
1521 |
} |
1522 |
logout("command 0x%04x, link 0x%08x, addr 0x%08x, size %u\n", rfd_command,
|
1523 |
rx.link, rx.rx_buf_addr, rfd_size); |
1524 |
stw_phys(s->ru_base + s->ru_offset + offsetof(eepro100_rx_t, status), |
1525 |
rfd_status); |
1526 |
stw_phys(s->ru_base + s->ru_offset + offsetof(eepro100_rx_t, count), size); |
1527 |
/* Early receive interrupt not supported. */
|
1528 |
//~ eepro100_er_interrupt(s);
|
1529 |
/* Receive CRC Transfer not supported. */
|
1530 |
assert(!(s->configuration[18] & 4)); |
1531 |
/* TODO: check stripping enable bit. */
|
1532 |
//~ assert(!(s->configuration[17] & 1));
|
1533 |
cpu_physical_memory_write(s->ru_base + s->ru_offset + |
1534 |
offsetof(eepro100_rx_t, packet), buf, size); |
1535 |
s->statistics.rx_good_frames++; |
1536 |
eepro100_fr_interrupt(s); |
1537 |
s->ru_offset = le32_to_cpu(rx.link); |
1538 |
if (rfd_command & 0x8000) { |
1539 |
/* EL bit is set, so this was the last frame. */
|
1540 |
assert(0);
|
1541 |
} |
1542 |
if (rfd_command & 0x4000) { |
1543 |
/* S bit is set. */
|
1544 |
set_ru_state(s, ru_suspended); |
1545 |
} |
1546 |
return size;
|
1547 |
} |
1548 |
|
1549 |
static int nic_load(QEMUFile * f, void *opaque, int version_id) |
1550 |
{ |
1551 |
EEPRO100State *s = opaque; |
1552 |
int i;
|
1553 |
int ret;
|
1554 |
|
1555 |
if (version_id > 3) |
1556 |
return -EINVAL;
|
1557 |
|
1558 |
if (s->pci_dev && version_id >= 3) { |
1559 |
ret = pci_device_load(s->pci_dev, f); |
1560 |
if (ret < 0) |
1561 |
return ret;
|
1562 |
} |
1563 |
|
1564 |
if (version_id >= 2) { |
1565 |
qemu_get_8s(f, &s->rxcr); |
1566 |
} else {
|
1567 |
s->rxcr = 0x0c;
|
1568 |
} |
1569 |
|
1570 |
qemu_get_8s(f, &s->cmd); |
1571 |
qemu_get_be32s(f, &s->start); |
1572 |
qemu_get_be32s(f, &s->stop); |
1573 |
qemu_get_8s(f, &s->boundary); |
1574 |
qemu_get_8s(f, &s->tsr); |
1575 |
qemu_get_8s(f, &s->tpsr); |
1576 |
qemu_get_be16s(f, &s->tcnt); |
1577 |
qemu_get_be16s(f, &s->rcnt); |
1578 |
qemu_get_be32s(f, &s->rsar); |
1579 |
qemu_get_8s(f, &s->rsr); |
1580 |
qemu_get_8s(f, &s->isr); |
1581 |
qemu_get_8s(f, &s->dcfg); |
1582 |
qemu_get_8s(f, &s->imr); |
1583 |
qemu_get_buffer(f, s->phys, 6);
|
1584 |
qemu_get_8s(f, &s->curpag); |
1585 |
qemu_get_buffer(f, s->mult, 8);
|
1586 |
qemu_get_buffer(f, s->mem, sizeof(s->mem));
|
1587 |
|
1588 |
/* Restore all members of struct between scv_stat and mem */
|
1589 |
qemu_get_8s(f, &s->scb_stat); |
1590 |
qemu_get_8s(f, &s->int_stat); |
1591 |
for (i = 0; i < 3; i++) |
1592 |
qemu_get_be32s(f, &s->region[i]); |
1593 |
qemu_get_buffer(f, s->macaddr, 6);
|
1594 |
for (i = 0; i < 19; i++) |
1595 |
qemu_get_be32s(f, &s->statcounter[i]); |
1596 |
for (i = 0; i < 32; i++) |
1597 |
qemu_get_be16s(f, &s->mdimem[i]); |
1598 |
/* The eeprom should be saved and restored by its own routines */
|
1599 |
qemu_get_be32s(f, &s->device); |
1600 |
qemu_get_be32s(f, &s->pointer); |
1601 |
qemu_get_be32s(f, &s->cu_base); |
1602 |
qemu_get_be32s(f, &s->cu_offset); |
1603 |
qemu_get_be32s(f, &s->ru_base); |
1604 |
qemu_get_be32s(f, &s->ru_offset); |
1605 |
qemu_get_be32s(f, &s->statsaddr); |
1606 |
/* Restore epro100_stats_t statistics */
|
1607 |
qemu_get_be32s(f, &s->statistics.tx_good_frames); |
1608 |
qemu_get_be32s(f, &s->statistics.tx_max_collisions); |
1609 |
qemu_get_be32s(f, &s->statistics.tx_late_collisions); |
1610 |
qemu_get_be32s(f, &s->statistics.tx_underruns); |
1611 |
qemu_get_be32s(f, &s->statistics.tx_lost_crs); |
1612 |
qemu_get_be32s(f, &s->statistics.tx_deferred); |
1613 |
qemu_get_be32s(f, &s->statistics.tx_single_collisions); |
1614 |
qemu_get_be32s(f, &s->statistics.tx_multiple_collisions); |
1615 |
qemu_get_be32s(f, &s->statistics.tx_total_collisions); |
1616 |
qemu_get_be32s(f, &s->statistics.rx_good_frames); |
1617 |
qemu_get_be32s(f, &s->statistics.rx_crc_errors); |
1618 |
qemu_get_be32s(f, &s->statistics.rx_alignment_errors); |
1619 |
qemu_get_be32s(f, &s->statistics.rx_resource_errors); |
1620 |
qemu_get_be32s(f, &s->statistics.rx_overrun_errors); |
1621 |
qemu_get_be32s(f, &s->statistics.rx_cdt_errors); |
1622 |
qemu_get_be32s(f, &s->statistics.rx_short_frame_errors); |
1623 |
qemu_get_be32s(f, &s->statistics.fc_xmt_pause); |
1624 |
qemu_get_be32s(f, &s->statistics.fc_rcv_pause); |
1625 |
qemu_get_be32s(f, &s->statistics.fc_rcv_unsupported); |
1626 |
qemu_get_be16s(f, &s->statistics.xmt_tco_frames); |
1627 |
qemu_get_be16s(f, &s->statistics.rcv_tco_frames); |
1628 |
qemu_get_be32s(f, &s->statistics.complete); |
1629 |
#if 0
|
1630 |
qemu_get_be16s(f, &s->status);
|
1631 |
#endif
|
1632 |
|
1633 |
/* Configuration bytes. */
|
1634 |
qemu_get_buffer(f, s->configuration, sizeof(s->configuration));
|
1635 |
|
1636 |
return 0; |
1637 |
} |
1638 |
|
1639 |
static void nic_save(QEMUFile * f, void *opaque) |
1640 |
{ |
1641 |
EEPRO100State *s = opaque; |
1642 |
int i;
|
1643 |
|
1644 |
if (s->pci_dev)
|
1645 |
pci_device_save(s->pci_dev, f); |
1646 |
|
1647 |
qemu_put_8s(f, &s->rxcr); |
1648 |
|
1649 |
qemu_put_8s(f, &s->cmd); |
1650 |
qemu_put_be32s(f, &s->start); |
1651 |
qemu_put_be32s(f, &s->stop); |
1652 |
qemu_put_8s(f, &s->boundary); |
1653 |
qemu_put_8s(f, &s->tsr); |
1654 |
qemu_put_8s(f, &s->tpsr); |
1655 |
qemu_put_be16s(f, &s->tcnt); |
1656 |
qemu_put_be16s(f, &s->rcnt); |
1657 |
qemu_put_be32s(f, &s->rsar); |
1658 |
qemu_put_8s(f, &s->rsr); |
1659 |
qemu_put_8s(f, &s->isr); |
1660 |
qemu_put_8s(f, &s->dcfg); |
1661 |
qemu_put_8s(f, &s->imr); |
1662 |
qemu_put_buffer(f, s->phys, 6);
|
1663 |
qemu_put_8s(f, &s->curpag); |
1664 |
qemu_put_buffer(f, s->mult, 8);
|
1665 |
qemu_put_buffer(f, s->mem, sizeof(s->mem));
|
1666 |
|
1667 |
/* Save all members of struct between scv_stat and mem */
|
1668 |
qemu_put_8s(f, &s->scb_stat); |
1669 |
qemu_put_8s(f, &s->int_stat); |
1670 |
for (i = 0; i < 3; i++) |
1671 |
qemu_put_be32s(f, &s->region[i]); |
1672 |
qemu_put_buffer(f, s->macaddr, 6);
|
1673 |
for (i = 0; i < 19; i++) |
1674 |
qemu_put_be32s(f, &s->statcounter[i]); |
1675 |
for (i = 0; i < 32; i++) |
1676 |
qemu_put_be16s(f, &s->mdimem[i]); |
1677 |
/* The eeprom should be saved and restored by its own routines */
|
1678 |
qemu_put_be32s(f, &s->device); |
1679 |
qemu_put_be32s(f, &s->pointer); |
1680 |
qemu_put_be32s(f, &s->cu_base); |
1681 |
qemu_put_be32s(f, &s->cu_offset); |
1682 |
qemu_put_be32s(f, &s->ru_base); |
1683 |
qemu_put_be32s(f, &s->ru_offset); |
1684 |
qemu_put_be32s(f, &s->statsaddr); |
1685 |
/* Save epro100_stats_t statistics */
|
1686 |
qemu_put_be32s(f, &s->statistics.tx_good_frames); |
1687 |
qemu_put_be32s(f, &s->statistics.tx_max_collisions); |
1688 |
qemu_put_be32s(f, &s->statistics.tx_late_collisions); |
1689 |
qemu_put_be32s(f, &s->statistics.tx_underruns); |
1690 |
qemu_put_be32s(f, &s->statistics.tx_lost_crs); |
1691 |
qemu_put_be32s(f, &s->statistics.tx_deferred); |
1692 |
qemu_put_be32s(f, &s->statistics.tx_single_collisions); |
1693 |
qemu_put_be32s(f, &s->statistics.tx_multiple_collisions); |
1694 |
qemu_put_be32s(f, &s->statistics.tx_total_collisions); |
1695 |
qemu_put_be32s(f, &s->statistics.rx_good_frames); |
1696 |
qemu_put_be32s(f, &s->statistics.rx_crc_errors); |
1697 |
qemu_put_be32s(f, &s->statistics.rx_alignment_errors); |
1698 |
qemu_put_be32s(f, &s->statistics.rx_resource_errors); |
1699 |
qemu_put_be32s(f, &s->statistics.rx_overrun_errors); |
1700 |
qemu_put_be32s(f, &s->statistics.rx_cdt_errors); |
1701 |
qemu_put_be32s(f, &s->statistics.rx_short_frame_errors); |
1702 |
qemu_put_be32s(f, &s->statistics.fc_xmt_pause); |
1703 |
qemu_put_be32s(f, &s->statistics.fc_rcv_pause); |
1704 |
qemu_put_be32s(f, &s->statistics.fc_rcv_unsupported); |
1705 |
qemu_put_be16s(f, &s->statistics.xmt_tco_frames); |
1706 |
qemu_put_be16s(f, &s->statistics.rcv_tco_frames); |
1707 |
qemu_put_be32s(f, &s->statistics.complete); |
1708 |
#if 0
|
1709 |
qemu_put_be16s(f, &s->status);
|
1710 |
#endif
|
1711 |
|
1712 |
/* Configuration bytes. */
|
1713 |
qemu_put_buffer(f, s->configuration, sizeof(s->configuration));
|
1714 |
} |
1715 |
|
1716 |
static void nic_cleanup(VLANClientState *vc) |
1717 |
{ |
1718 |
EEPRO100State *s = vc->opaque; |
1719 |
|
1720 |
unregister_savevm(vc->model, s); |
1721 |
|
1722 |
eeprom93xx_free(s->eeprom); |
1723 |
} |
1724 |
|
1725 |
static int pci_nic_uninit(PCIDevice *dev) |
1726 |
{ |
1727 |
PCIEEPRO100State *d = DO_UPCAST(PCIEEPRO100State, dev, dev); |
1728 |
EEPRO100State *s = &d->eepro100; |
1729 |
|
1730 |
cpu_unregister_io_memory(s->mmio_index); |
1731 |
|
1732 |
return 0; |
1733 |
} |
1734 |
|
1735 |
static int nic_init(PCIDevice *pci_dev, uint32_t device) |
1736 |
{ |
1737 |
PCIEEPRO100State *d = DO_UPCAST(PCIEEPRO100State, dev, pci_dev); |
1738 |
EEPRO100State *s; |
1739 |
|
1740 |
logout("\n");
|
1741 |
|
1742 |
d->dev.unregister = pci_nic_uninit; |
1743 |
|
1744 |
s = &d->eepro100; |
1745 |
s->device = device; |
1746 |
s->pci_dev = &d->dev; |
1747 |
|
1748 |
pci_reset(s); |
1749 |
|
1750 |
/* Add 64 * 2 EEPROM. i82557 and i82558 support a 64 word EEPROM,
|
1751 |
* i82559 and later support 64 or 256 word EEPROM. */
|
1752 |
s->eeprom = eeprom93xx_new(EEPROM_SIZE); |
1753 |
|
1754 |
/* Handler for memory-mapped I/O */
|
1755 |
d->eepro100.mmio_index = |
1756 |
cpu_register_io_memory(pci_mmio_read, pci_mmio_write, s); |
1757 |
|
1758 |
pci_register_bar(&d->dev, 0, PCI_MEM_SIZE,
|
1759 |
PCI_ADDRESS_SPACE_MEM | |
1760 |
PCI_ADDRESS_SPACE_MEM_PREFETCH, pci_mmio_map); |
1761 |
pci_register_bar(&d->dev, 1, PCI_IO_SIZE, PCI_ADDRESS_SPACE_IO,
|
1762 |
pci_map); |
1763 |
pci_register_bar(&d->dev, 2, PCI_FLASH_SIZE, PCI_ADDRESS_SPACE_MEM,
|
1764 |
pci_mmio_map); |
1765 |
|
1766 |
qdev_get_macaddr(&d->dev.qdev, s->macaddr); |
1767 |
logout("macaddr: %s\n", nic_dump(&s->macaddr[0], 6)); |
1768 |
assert(s->region[1] == 0); |
1769 |
|
1770 |
nic_reset(s); |
1771 |
|
1772 |
s->vc = qdev_get_vlan_client(&d->dev.qdev, |
1773 |
nic_can_receive, nic_receive, NULL,
|
1774 |
nic_cleanup, s); |
1775 |
|
1776 |
qemu_format_nic_info_str(s->vc, s->macaddr); |
1777 |
|
1778 |
qemu_register_reset(nic_reset, s); |
1779 |
|
1780 |
register_savevm(s->vc->model, -1, 3, nic_save, nic_load, s); |
1781 |
return 0; |
1782 |
} |
1783 |
|
1784 |
static int pci_i82551_init(PCIDevice *dev) |
1785 |
{ |
1786 |
return nic_init(dev, i82551);
|
1787 |
} |
1788 |
|
1789 |
static int pci_i82557b_init(PCIDevice *dev) |
1790 |
{ |
1791 |
return nic_init(dev, i82557B);
|
1792 |
} |
1793 |
|
1794 |
static int pci_i82559er_init(PCIDevice *dev) |
1795 |
{ |
1796 |
return nic_init(dev, i82559ER);
|
1797 |
} |
1798 |
|
1799 |
static PCIDeviceInfo eepro100_info[] = {
|
1800 |
{ |
1801 |
.qdev.name = "i82551",
|
1802 |
.qdev.size = sizeof(PCIEEPRO100State),
|
1803 |
.init = pci_i82551_init, |
1804 |
},{ |
1805 |
.qdev.name = "i82557b",
|
1806 |
.qdev.size = sizeof(PCIEEPRO100State),
|
1807 |
.init = pci_i82557b_init, |
1808 |
},{ |
1809 |
.qdev.name = "i82559er",
|
1810 |
.qdev.size = sizeof(PCIEEPRO100State),
|
1811 |
.init = pci_i82559er_init, |
1812 |
},{ |
1813 |
/* end of list */
|
1814 |
} |
1815 |
}; |
1816 |
|
1817 |
static void eepro100_register_devices(void) |
1818 |
{ |
1819 |
pci_qdev_register_many(eepro100_info); |
1820 |
} |
1821 |
|
1822 |
device_init(eepro100_register_devices) |