root / hw / ppce500_pci.c @ 771124e1
History | View | Annotate | Download (10.3 kB)
1 | 74c62ba8 | aurel32 | /*
|
---|---|---|---|
2 | 74c62ba8 | aurel32 | * QEMU PowerPC E500 embedded processors pci controller emulation
|
3 | 74c62ba8 | aurel32 | *
|
4 | 74c62ba8 | aurel32 | * Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved.
|
5 | 74c62ba8 | aurel32 | *
|
6 | 74c62ba8 | aurel32 | * Author: Yu Liu, <yu.liu@freescale.com>
|
7 | 74c62ba8 | aurel32 | *
|
8 | 74c62ba8 | aurel32 | * This file is derived from hw/ppc4xx_pci.c,
|
9 | 74c62ba8 | aurel32 | * the copyright for that material belongs to the original owners.
|
10 | 74c62ba8 | aurel32 | *
|
11 | 74c62ba8 | aurel32 | * This is free software; you can redistribute it and/or modify
|
12 | 74c62ba8 | aurel32 | * it under the terms of the GNU General Public License as published by
|
13 | 74c62ba8 | aurel32 | * the Free Software Foundation; either version 2 of the License, or
|
14 | 74c62ba8 | aurel32 | * (at your option) any later version.
|
15 | 74c62ba8 | aurel32 | */
|
16 | 74c62ba8 | aurel32 | |
17 | 74c62ba8 | aurel32 | #include "hw.h" |
18 | 74c62ba8 | aurel32 | #include "pci.h" |
19 | 74c62ba8 | aurel32 | #include "pci_host.h" |
20 | 74c62ba8 | aurel32 | #include "bswap.h" |
21 | 74c62ba8 | aurel32 | |
22 | 74c62ba8 | aurel32 | #ifdef DEBUG_PCI
|
23 | 001faf32 | Blue Swirl | #define pci_debug(fmt, ...) fprintf(stderr, fmt, ## __VA_ARGS__) |
24 | 74c62ba8 | aurel32 | #else
|
25 | 001faf32 | Blue Swirl | #define pci_debug(fmt, ...)
|
26 | 74c62ba8 | aurel32 | #endif
|
27 | 74c62ba8 | aurel32 | |
28 | 74c62ba8 | aurel32 | #define PCIE500_CFGADDR 0x0 |
29 | 74c62ba8 | aurel32 | #define PCIE500_CFGDATA 0x4 |
30 | 74c62ba8 | aurel32 | #define PCIE500_REG_BASE 0xC00 |
31 | be13cc7a | Alexander Graf | #define PCIE500_ALL_SIZE 0x1000 |
32 | be13cc7a | Alexander Graf | #define PCIE500_REG_SIZE (PCIE500_ALL_SIZE - PCIE500_REG_BASE)
|
33 | 74c62ba8 | aurel32 | |
34 | 74c62ba8 | aurel32 | #define PPCE500_PCI_CONFIG_ADDR 0x0 |
35 | 74c62ba8 | aurel32 | #define PPCE500_PCI_CONFIG_DATA 0x4 |
36 | 74c62ba8 | aurel32 | #define PPCE500_PCI_INTACK 0x8 |
37 | 74c62ba8 | aurel32 | |
38 | 74c62ba8 | aurel32 | #define PPCE500_PCI_OW1 (0xC20 - PCIE500_REG_BASE) |
39 | 74c62ba8 | aurel32 | #define PPCE500_PCI_OW2 (0xC40 - PCIE500_REG_BASE) |
40 | 74c62ba8 | aurel32 | #define PPCE500_PCI_OW3 (0xC60 - PCIE500_REG_BASE) |
41 | 74c62ba8 | aurel32 | #define PPCE500_PCI_OW4 (0xC80 - PCIE500_REG_BASE) |
42 | 74c62ba8 | aurel32 | #define PPCE500_PCI_IW3 (0xDA0 - PCIE500_REG_BASE) |
43 | 74c62ba8 | aurel32 | #define PPCE500_PCI_IW2 (0xDC0 - PCIE500_REG_BASE) |
44 | 74c62ba8 | aurel32 | #define PPCE500_PCI_IW1 (0xDE0 - PCIE500_REG_BASE) |
45 | 74c62ba8 | aurel32 | |
46 | 74c62ba8 | aurel32 | #define PPCE500_PCI_GASKET_TIMR (0xE20 - PCIE500_REG_BASE) |
47 | 74c62ba8 | aurel32 | |
48 | 74c62ba8 | aurel32 | #define PCI_POTAR 0x0 |
49 | 74c62ba8 | aurel32 | #define PCI_POTEAR 0x4 |
50 | 74c62ba8 | aurel32 | #define PCI_POWBAR 0x8 |
51 | 74c62ba8 | aurel32 | #define PCI_POWAR 0x10 |
52 | 74c62ba8 | aurel32 | |
53 | 74c62ba8 | aurel32 | #define PCI_PITAR 0x0 |
54 | 74c62ba8 | aurel32 | #define PCI_PIWBAR 0x8 |
55 | 74c62ba8 | aurel32 | #define PCI_PIWBEAR 0xC |
56 | 74c62ba8 | aurel32 | #define PCI_PIWAR 0x10 |
57 | 74c62ba8 | aurel32 | |
58 | 74c62ba8 | aurel32 | #define PPCE500_PCI_NR_POBS 5 |
59 | 74c62ba8 | aurel32 | #define PPCE500_PCI_NR_PIBS 3 |
60 | 74c62ba8 | aurel32 | |
61 | 74c62ba8 | aurel32 | struct pci_outbound {
|
62 | 74c62ba8 | aurel32 | uint32_t potar; |
63 | 74c62ba8 | aurel32 | uint32_t potear; |
64 | 74c62ba8 | aurel32 | uint32_t powbar; |
65 | 74c62ba8 | aurel32 | uint32_t powar; |
66 | 74c62ba8 | aurel32 | }; |
67 | 74c62ba8 | aurel32 | |
68 | 74c62ba8 | aurel32 | struct pci_inbound {
|
69 | 74c62ba8 | aurel32 | uint32_t pitar; |
70 | 74c62ba8 | aurel32 | uint32_t piwbar; |
71 | 74c62ba8 | aurel32 | uint32_t piwbear; |
72 | 74c62ba8 | aurel32 | uint32_t piwar; |
73 | 74c62ba8 | aurel32 | }; |
74 | 74c62ba8 | aurel32 | |
75 | 74c62ba8 | aurel32 | struct PPCE500PCIState {
|
76 | be13cc7a | Alexander Graf | PCIHostState pci_state; |
77 | 74c62ba8 | aurel32 | struct pci_outbound pob[PPCE500_PCI_NR_POBS];
|
78 | 74c62ba8 | aurel32 | struct pci_inbound pib[PPCE500_PCI_NR_PIBS];
|
79 | 74c62ba8 | aurel32 | uint32_t gasket_time; |
80 | be13cc7a | Alexander Graf | qemu_irq irq[4];
|
81 | be13cc7a | Alexander Graf | /* mmio maps */
|
82 | cb4e15c7 | Benoît Canet | MemoryRegion container; |
83 | cd5cba79 | Avi Kivity | MemoryRegion iomem; |
84 | 74c62ba8 | aurel32 | }; |
85 | 74c62ba8 | aurel32 | |
86 | 74c62ba8 | aurel32 | typedef struct PPCE500PCIState PPCE500PCIState; |
87 | 74c62ba8 | aurel32 | |
88 | cd5cba79 | Avi Kivity | static uint64_t pci_reg_read4(void *opaque, target_phys_addr_t addr, |
89 | cd5cba79 | Avi Kivity | unsigned size)
|
90 | 74c62ba8 | aurel32 | { |
91 | 74c62ba8 | aurel32 | PPCE500PCIState *pci = opaque; |
92 | 74c62ba8 | aurel32 | unsigned long win; |
93 | 74c62ba8 | aurel32 | uint32_t value = 0;
|
94 | eeae2e7b | Liu Yu-B13201 | int idx;
|
95 | 74c62ba8 | aurel32 | |
96 | 74c62ba8 | aurel32 | win = addr & 0xfe0;
|
97 | 74c62ba8 | aurel32 | |
98 | 74c62ba8 | aurel32 | switch (win) {
|
99 | 74c62ba8 | aurel32 | case PPCE500_PCI_OW1:
|
100 | 74c62ba8 | aurel32 | case PPCE500_PCI_OW2:
|
101 | 74c62ba8 | aurel32 | case PPCE500_PCI_OW3:
|
102 | 74c62ba8 | aurel32 | case PPCE500_PCI_OW4:
|
103 | eeae2e7b | Liu Yu-B13201 | idx = (addr >> 5) & 0x7; |
104 | 74c62ba8 | aurel32 | switch (addr & 0xC) { |
105 | 6875dc8e | Liu Yu-B13201 | case PCI_POTAR:
|
106 | eeae2e7b | Liu Yu-B13201 | value = pci->pob[idx].potar; |
107 | 6875dc8e | Liu Yu-B13201 | break;
|
108 | 6875dc8e | Liu Yu-B13201 | case PCI_POTEAR:
|
109 | eeae2e7b | Liu Yu-B13201 | value = pci->pob[idx].potear; |
110 | 6875dc8e | Liu Yu-B13201 | break;
|
111 | 6875dc8e | Liu Yu-B13201 | case PCI_POWBAR:
|
112 | eeae2e7b | Liu Yu-B13201 | value = pci->pob[idx].powbar; |
113 | 6875dc8e | Liu Yu-B13201 | break;
|
114 | 6875dc8e | Liu Yu-B13201 | case PCI_POWAR:
|
115 | eeae2e7b | Liu Yu-B13201 | value = pci->pob[idx].powar; |
116 | 6875dc8e | Liu Yu-B13201 | break;
|
117 | 6875dc8e | Liu Yu-B13201 | default:
|
118 | 6875dc8e | Liu Yu-B13201 | break;
|
119 | 74c62ba8 | aurel32 | } |
120 | 74c62ba8 | aurel32 | break;
|
121 | 74c62ba8 | aurel32 | |
122 | 74c62ba8 | aurel32 | case PPCE500_PCI_IW3:
|
123 | 74c62ba8 | aurel32 | case PPCE500_PCI_IW2:
|
124 | 74c62ba8 | aurel32 | case PPCE500_PCI_IW1:
|
125 | eeae2e7b | Liu Yu-B13201 | idx = ((addr >> 5) & 0x3) - 1; |
126 | 74c62ba8 | aurel32 | switch (addr & 0xC) { |
127 | 6875dc8e | Liu Yu-B13201 | case PCI_PITAR:
|
128 | eeae2e7b | Liu Yu-B13201 | value = pci->pib[idx].pitar; |
129 | 6875dc8e | Liu Yu-B13201 | break;
|
130 | 6875dc8e | Liu Yu-B13201 | case PCI_PIWBAR:
|
131 | eeae2e7b | Liu Yu-B13201 | value = pci->pib[idx].piwbar; |
132 | 6875dc8e | Liu Yu-B13201 | break;
|
133 | 6875dc8e | Liu Yu-B13201 | case PCI_PIWBEAR:
|
134 | eeae2e7b | Liu Yu-B13201 | value = pci->pib[idx].piwbear; |
135 | 6875dc8e | Liu Yu-B13201 | break;
|
136 | 6875dc8e | Liu Yu-B13201 | case PCI_PIWAR:
|
137 | eeae2e7b | Liu Yu-B13201 | value = pci->pib[idx].piwar; |
138 | 6875dc8e | Liu Yu-B13201 | break;
|
139 | 6875dc8e | Liu Yu-B13201 | default:
|
140 | 6875dc8e | Liu Yu-B13201 | break;
|
141 | 74c62ba8 | aurel32 | }; |
142 | 74c62ba8 | aurel32 | break;
|
143 | 74c62ba8 | aurel32 | |
144 | 74c62ba8 | aurel32 | case PPCE500_PCI_GASKET_TIMR:
|
145 | 74c62ba8 | aurel32 | value = pci->gasket_time; |
146 | 74c62ba8 | aurel32 | break;
|
147 | 74c62ba8 | aurel32 | |
148 | 74c62ba8 | aurel32 | default:
|
149 | 74c62ba8 | aurel32 | break;
|
150 | 74c62ba8 | aurel32 | } |
151 | 74c62ba8 | aurel32 | |
152 | c0a2a096 | Blue Swirl | pci_debug("%s: win:%lx(addr:" TARGET_FMT_plx ") -> value:%x\n", __func__, |
153 | c0a2a096 | Blue Swirl | win, addr, value); |
154 | 74c62ba8 | aurel32 | return value;
|
155 | 74c62ba8 | aurel32 | } |
156 | 74c62ba8 | aurel32 | |
157 | c227f099 | Anthony Liguori | static void pci_reg_write4(void *opaque, target_phys_addr_t addr, |
158 | cd5cba79 | Avi Kivity | uint64_t value, unsigned size)
|
159 | 74c62ba8 | aurel32 | { |
160 | 74c62ba8 | aurel32 | PPCE500PCIState *pci = opaque; |
161 | 74c62ba8 | aurel32 | unsigned long win; |
162 | eeae2e7b | Liu Yu-B13201 | int idx;
|
163 | 74c62ba8 | aurel32 | |
164 | 74c62ba8 | aurel32 | win = addr & 0xfe0;
|
165 | 74c62ba8 | aurel32 | |
166 | c0a2a096 | Blue Swirl | pci_debug("%s: value:%x -> win:%lx(addr:" TARGET_FMT_plx ")\n", |
167 | cd5cba79 | Avi Kivity | __func__, (unsigned)value, win, addr);
|
168 | 74c62ba8 | aurel32 | |
169 | 74c62ba8 | aurel32 | switch (win) {
|
170 | 74c62ba8 | aurel32 | case PPCE500_PCI_OW1:
|
171 | 74c62ba8 | aurel32 | case PPCE500_PCI_OW2:
|
172 | 74c62ba8 | aurel32 | case PPCE500_PCI_OW3:
|
173 | 74c62ba8 | aurel32 | case PPCE500_PCI_OW4:
|
174 | eeae2e7b | Liu Yu-B13201 | idx = (addr >> 5) & 0x7; |
175 | 74c62ba8 | aurel32 | switch (addr & 0xC) { |
176 | 6875dc8e | Liu Yu-B13201 | case PCI_POTAR:
|
177 | eeae2e7b | Liu Yu-B13201 | pci->pob[idx].potar = value; |
178 | 6875dc8e | Liu Yu-B13201 | break;
|
179 | 6875dc8e | Liu Yu-B13201 | case PCI_POTEAR:
|
180 | eeae2e7b | Liu Yu-B13201 | pci->pob[idx].potear = value; |
181 | 6875dc8e | Liu Yu-B13201 | break;
|
182 | 6875dc8e | Liu Yu-B13201 | case PCI_POWBAR:
|
183 | eeae2e7b | Liu Yu-B13201 | pci->pob[idx].powbar = value; |
184 | 6875dc8e | Liu Yu-B13201 | break;
|
185 | 6875dc8e | Liu Yu-B13201 | case PCI_POWAR:
|
186 | eeae2e7b | Liu Yu-B13201 | pci->pob[idx].powar = value; |
187 | 6875dc8e | Liu Yu-B13201 | break;
|
188 | 6875dc8e | Liu Yu-B13201 | default:
|
189 | 6875dc8e | Liu Yu-B13201 | break;
|
190 | 74c62ba8 | aurel32 | }; |
191 | 74c62ba8 | aurel32 | break;
|
192 | 74c62ba8 | aurel32 | |
193 | 74c62ba8 | aurel32 | case PPCE500_PCI_IW3:
|
194 | 74c62ba8 | aurel32 | case PPCE500_PCI_IW2:
|
195 | 74c62ba8 | aurel32 | case PPCE500_PCI_IW1:
|
196 | eeae2e7b | Liu Yu-B13201 | idx = ((addr >> 5) & 0x3) - 1; |
197 | 74c62ba8 | aurel32 | switch (addr & 0xC) { |
198 | 6875dc8e | Liu Yu-B13201 | case PCI_PITAR:
|
199 | eeae2e7b | Liu Yu-B13201 | pci->pib[idx].pitar = value; |
200 | 6875dc8e | Liu Yu-B13201 | break;
|
201 | 6875dc8e | Liu Yu-B13201 | case PCI_PIWBAR:
|
202 | eeae2e7b | Liu Yu-B13201 | pci->pib[idx].piwbar = value; |
203 | 6875dc8e | Liu Yu-B13201 | break;
|
204 | 6875dc8e | Liu Yu-B13201 | case PCI_PIWBEAR:
|
205 | eeae2e7b | Liu Yu-B13201 | pci->pib[idx].piwbear = value; |
206 | 6875dc8e | Liu Yu-B13201 | break;
|
207 | 6875dc8e | Liu Yu-B13201 | case PCI_PIWAR:
|
208 | eeae2e7b | Liu Yu-B13201 | pci->pib[idx].piwar = value; |
209 | 6875dc8e | Liu Yu-B13201 | break;
|
210 | 6875dc8e | Liu Yu-B13201 | default:
|
211 | 6875dc8e | Liu Yu-B13201 | break;
|
212 | 74c62ba8 | aurel32 | }; |
213 | 74c62ba8 | aurel32 | break;
|
214 | 74c62ba8 | aurel32 | |
215 | 74c62ba8 | aurel32 | case PPCE500_PCI_GASKET_TIMR:
|
216 | 74c62ba8 | aurel32 | pci->gasket_time = value; |
217 | 74c62ba8 | aurel32 | break;
|
218 | 74c62ba8 | aurel32 | |
219 | 74c62ba8 | aurel32 | default:
|
220 | 74c62ba8 | aurel32 | break;
|
221 | 74c62ba8 | aurel32 | }; |
222 | 74c62ba8 | aurel32 | } |
223 | 74c62ba8 | aurel32 | |
224 | cd5cba79 | Avi Kivity | static const MemoryRegionOps e500_pci_reg_ops = { |
225 | cd5cba79 | Avi Kivity | .read = pci_reg_read4, |
226 | cd5cba79 | Avi Kivity | .write = pci_reg_write4, |
227 | cd5cba79 | Avi Kivity | .endianness = DEVICE_BIG_ENDIAN, |
228 | 74c62ba8 | aurel32 | }; |
229 | 74c62ba8 | aurel32 | |
230 | 74c62ba8 | aurel32 | static int mpc85xx_pci_map_irq(PCIDevice *pci_dev, int irq_num) |
231 | 74c62ba8 | aurel32 | { |
232 | 74c62ba8 | aurel32 | int devno = pci_dev->devfn >> 3, ret = 0; |
233 | 74c62ba8 | aurel32 | |
234 | 74c62ba8 | aurel32 | switch (devno) {
|
235 | 74c62ba8 | aurel32 | /* Two PCI slot */
|
236 | 74c62ba8 | aurel32 | case 0x11: |
237 | 74c62ba8 | aurel32 | case 0x12: |
238 | 74c62ba8 | aurel32 | ret = (irq_num + devno - 0x10) % 4; |
239 | 74c62ba8 | aurel32 | break;
|
240 | 74c62ba8 | aurel32 | default:
|
241 | 72b310e9 | Scott Wood | printf("Error:%s:unknown dev number\n", __func__);
|
242 | 74c62ba8 | aurel32 | } |
243 | 74c62ba8 | aurel32 | |
244 | 74c62ba8 | aurel32 | pci_debug("%s: devfn %x irq %d -> %d devno:%x\n", __func__,
|
245 | 74c62ba8 | aurel32 | pci_dev->devfn, irq_num, ret, devno); |
246 | 74c62ba8 | aurel32 | |
247 | 74c62ba8 | aurel32 | return ret;
|
248 | 74c62ba8 | aurel32 | } |
249 | 74c62ba8 | aurel32 | |
250 | 5d4e84c8 | Juan Quintela | static void mpc85xx_pci_set_irq(void *opaque, int irq_num, int level) |
251 | 74c62ba8 | aurel32 | { |
252 | 5d4e84c8 | Juan Quintela | qemu_irq *pic = opaque; |
253 | 5d4e84c8 | Juan Quintela | |
254 | 74c62ba8 | aurel32 | pci_debug("%s: PCI irq %d, level:%d\n", __func__, irq_num, level);
|
255 | 74c62ba8 | aurel32 | |
256 | 74c62ba8 | aurel32 | qemu_set_irq(pic[irq_num], level); |
257 | 74c62ba8 | aurel32 | } |
258 | 74c62ba8 | aurel32 | |
259 | e0433ecc | Juan Quintela | static const VMStateDescription vmstate_pci_outbound = { |
260 | e0433ecc | Juan Quintela | .name = "pci_outbound",
|
261 | e0433ecc | Juan Quintela | .version_id = 0,
|
262 | e0433ecc | Juan Quintela | .minimum_version_id = 0,
|
263 | e0433ecc | Juan Quintela | .minimum_version_id_old = 0,
|
264 | e0433ecc | Juan Quintela | .fields = (VMStateField[]) { |
265 | e0433ecc | Juan Quintela | VMSTATE_UINT32(potar, struct pci_outbound),
|
266 | e0433ecc | Juan Quintela | VMSTATE_UINT32(potear, struct pci_outbound),
|
267 | e0433ecc | Juan Quintela | VMSTATE_UINT32(powbar, struct pci_outbound),
|
268 | e0433ecc | Juan Quintela | VMSTATE_UINT32(powar, struct pci_outbound),
|
269 | e0433ecc | Juan Quintela | VMSTATE_END_OF_LIST() |
270 | 74c62ba8 | aurel32 | } |
271 | e0433ecc | Juan Quintela | }; |
272 | 74c62ba8 | aurel32 | |
273 | e0433ecc | Juan Quintela | static const VMStateDescription vmstate_pci_inbound = { |
274 | e0433ecc | Juan Quintela | .name = "pci_inbound",
|
275 | e0433ecc | Juan Quintela | .version_id = 0,
|
276 | e0433ecc | Juan Quintela | .minimum_version_id = 0,
|
277 | e0433ecc | Juan Quintela | .minimum_version_id_old = 0,
|
278 | e0433ecc | Juan Quintela | .fields = (VMStateField[]) { |
279 | e0433ecc | Juan Quintela | VMSTATE_UINT32(pitar, struct pci_inbound),
|
280 | e0433ecc | Juan Quintela | VMSTATE_UINT32(piwbar, struct pci_inbound),
|
281 | e0433ecc | Juan Quintela | VMSTATE_UINT32(piwbear, struct pci_inbound),
|
282 | e0433ecc | Juan Quintela | VMSTATE_UINT32(piwar, struct pci_inbound),
|
283 | e0433ecc | Juan Quintela | VMSTATE_END_OF_LIST() |
284 | 74c62ba8 | aurel32 | } |
285 | e0433ecc | Juan Quintela | }; |
286 | 74c62ba8 | aurel32 | |
287 | e0433ecc | Juan Quintela | static const VMStateDescription vmstate_ppce500_pci = { |
288 | e0433ecc | Juan Quintela | .name = "ppce500_pci",
|
289 | e0433ecc | Juan Quintela | .version_id = 1,
|
290 | e0433ecc | Juan Quintela | .minimum_version_id = 1,
|
291 | e0433ecc | Juan Quintela | .minimum_version_id_old = 1,
|
292 | e0433ecc | Juan Quintela | .fields = (VMStateField[]) { |
293 | e0433ecc | Juan Quintela | VMSTATE_STRUCT_ARRAY(pob, PPCE500PCIState, PPCE500_PCI_NR_POBS, 1,
|
294 | e0433ecc | Juan Quintela | vmstate_pci_outbound, struct pci_outbound),
|
295 | e0433ecc | Juan Quintela | VMSTATE_STRUCT_ARRAY(pib, PPCE500PCIState, PPCE500_PCI_NR_PIBS, 1,
|
296 | e0433ecc | Juan Quintela | vmstate_pci_outbound, struct pci_inbound),
|
297 | e0433ecc | Juan Quintela | VMSTATE_UINT32(gasket_time, PPCE500PCIState), |
298 | e0433ecc | Juan Quintela | VMSTATE_END_OF_LIST() |
299 | 74c62ba8 | aurel32 | } |
300 | e0433ecc | Juan Quintela | }; |
301 | 74c62ba8 | aurel32 | |
302 | 1e39101c | Avi Kivity | #include "exec-memory.h" |
303 | 1e39101c | Avi Kivity | |
304 | be13cc7a | Alexander Graf | static int e500_pcihost_initfn(SysBusDevice *dev) |
305 | be13cc7a | Alexander Graf | { |
306 | be13cc7a | Alexander Graf | PCIHostState *h; |
307 | be13cc7a | Alexander Graf | PPCE500PCIState *s; |
308 | be13cc7a | Alexander Graf | PCIBus *b; |
309 | be13cc7a | Alexander Graf | int i;
|
310 | aee97b84 | Avi Kivity | MemoryRegion *address_space_mem = get_system_memory(); |
311 | aee97b84 | Avi Kivity | MemoryRegion *address_space_io = get_system_io(); |
312 | be13cc7a | Alexander Graf | |
313 | be13cc7a | Alexander Graf | h = FROM_SYSBUS(PCIHostState, sysbus_from_qdev(dev)); |
314 | be13cc7a | Alexander Graf | s = DO_UPCAST(PPCE500PCIState, pci_state, h); |
315 | be13cc7a | Alexander Graf | |
316 | be13cc7a | Alexander Graf | for (i = 0; i < ARRAY_SIZE(s->irq); i++) { |
317 | be13cc7a | Alexander Graf | sysbus_init_irq(dev, &s->irq[i]); |
318 | be13cc7a | Alexander Graf | } |
319 | be13cc7a | Alexander Graf | |
320 | be13cc7a | Alexander Graf | b = pci_register_bus(&s->pci_state.busdev.qdev, NULL, mpc85xx_pci_set_irq,
|
321 | aee97b84 | Avi Kivity | mpc85xx_pci_map_irq, s->irq, address_space_mem, |
322 | aee97b84 | Avi Kivity | address_space_io, PCI_DEVFN(0x11, 0), 4); |
323 | be13cc7a | Alexander Graf | s->pci_state.bus = b; |
324 | be13cc7a | Alexander Graf | |
325 | be13cc7a | Alexander Graf | pci_create_simple(b, 0, "e500-host-bridge"); |
326 | be13cc7a | Alexander Graf | |
327 | cb4e15c7 | Benoît Canet | memory_region_init(&s->container, "pci-container", PCIE500_ALL_SIZE);
|
328 | d0ed8076 | Avi Kivity | memory_region_init_io(&h->conf_mem, &pci_host_conf_be_ops, h, |
329 | d0ed8076 | Avi Kivity | "pci-conf-idx", 4); |
330 | d0ed8076 | Avi Kivity | memory_region_init_io(&h->data_mem, &pci_host_data_le_ops, h, |
331 | d0ed8076 | Avi Kivity | "pci-conf-data", 4); |
332 | cd5cba79 | Avi Kivity | memory_region_init_io(&s->iomem, &e500_pci_reg_ops, s, |
333 | cd5cba79 | Avi Kivity | "pci.reg", PCIE500_REG_SIZE);
|
334 | cb4e15c7 | Benoît Canet | memory_region_add_subregion(&s->container, PCIE500_CFGADDR, &h->conf_mem); |
335 | cb4e15c7 | Benoît Canet | memory_region_add_subregion(&s->container, PCIE500_CFGDATA, &h->data_mem); |
336 | cb4e15c7 | Benoît Canet | memory_region_add_subregion(&s->container, PCIE500_REG_BASE, &s->iomem); |
337 | cb4e15c7 | Benoît Canet | sysbus_init_mmio(dev, &s->container); |
338 | be13cc7a | Alexander Graf | |
339 | be13cc7a | Alexander Graf | return 0; |
340 | be13cc7a | Alexander Graf | } |
341 | be13cc7a | Alexander Graf | |
342 | 40021f08 | Anthony Liguori | static void e500_host_bridge_class_init(ObjectClass *klass, void *data) |
343 | 40021f08 | Anthony Liguori | { |
344 | 40021f08 | Anthony Liguori | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
345 | 40021f08 | Anthony Liguori | |
346 | 40021f08 | Anthony Liguori | k->vendor_id = PCI_VENDOR_ID_FREESCALE; |
347 | 40021f08 | Anthony Liguori | k->device_id = PCI_DEVICE_ID_MPC8533E; |
348 | 40021f08 | Anthony Liguori | k->class_id = PCI_CLASS_PROCESSOR_POWERPC; |
349 | 40021f08 | Anthony Liguori | } |
350 | 40021f08 | Anthony Liguori | |
351 | 40021f08 | Anthony Liguori | static DeviceInfo e500_host_bridge_info = {
|
352 | 40021f08 | Anthony Liguori | .name = "e500-host-bridge",
|
353 | 40021f08 | Anthony Liguori | .desc = "Host bridge",
|
354 | 40021f08 | Anthony Liguori | .size = sizeof(PCIDevice),
|
355 | 40021f08 | Anthony Liguori | .class_init = e500_host_bridge_class_init, |
356 | be13cc7a | Alexander Graf | }; |
357 | be13cc7a | Alexander Graf | |
358 | 999e12bb | Anthony Liguori | static void e500_pcihost_class_init(ObjectClass *klass, void *data) |
359 | 999e12bb | Anthony Liguori | { |
360 | 999e12bb | Anthony Liguori | SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); |
361 | 999e12bb | Anthony Liguori | |
362 | 999e12bb | Anthony Liguori | k->init = e500_pcihost_initfn; |
363 | 999e12bb | Anthony Liguori | } |
364 | 999e12bb | Anthony Liguori | |
365 | 999e12bb | Anthony Liguori | static DeviceInfo e500_pcihost_info = {
|
366 | 999e12bb | Anthony Liguori | .name = "e500-pcihost",
|
367 | 999e12bb | Anthony Liguori | .size = sizeof(PPCE500PCIState),
|
368 | 999e12bb | Anthony Liguori | .vmsd = &vmstate_ppce500_pci, |
369 | 999e12bb | Anthony Liguori | .class_init = e500_pcihost_class_init, |
370 | be13cc7a | Alexander Graf | }; |
371 | be13cc7a | Alexander Graf | |
372 | be13cc7a | Alexander Graf | static void e500_pci_register(void) |
373 | 74c62ba8 | aurel32 | { |
374 | be13cc7a | Alexander Graf | sysbus_register_withprop(&e500_pcihost_info); |
375 | be13cc7a | Alexander Graf | pci_qdev_register(&e500_host_bridge_info); |
376 | 74c62ba8 | aurel32 | } |
377 | be13cc7a | Alexander Graf | device_init(e500_pci_register); |