Add Cortex-A15 CPU definition
Add a definition of a Cortex-A15 CPU. Note that for the moment we donot implement any of: * Large Physical Address Extensions (LPAE) * Virtualization Extensions * Generic Timer * TrustZone (this is also true of our existing Cortex-A9 model, etc)...
Add dummy implementation of generic timer cp15 registers
Add a dummy implementation of the cp15 registers for the generictimer (found in the Cortex-A15), just sufficient for Linux todecide that it can't use it. This requires at least CNTP_CTL andCNTFRQ to be implemented as RAZ/WI; we RAZ/WI all of c14....
target-arm: Fix implementation of TLB invalidate operations
Fix some bugs in the implementation of the TLB invalidateoperations on ARM: * the 'invalidate all' op was not passing flush_global=1 to tlb_flush(); this doesn't have a practical effect since...
target-arm/helper.c: Don't assume softfloat int32 is 32 bits only
In the helper routines for VCVT float-to-int conversions, addan explicit cast rather than relying on the softfloat int32type being exactly 32 bits wide (which it is not guaranteed to be)....
arm: store the config_base_register during cpu_reset
Long term, the config_base_register will be a QDM parameter. In themeantime, models that use it need to be able to preserve it acrosscpu_reset() calls.
Signed-off-by: Mark Langsdorf <mark.langsdorf@calxeda.com>...
target-arm: Fix errors in decode of M profile CPS
Fix errors in the decode of M profile CPS: * the decode of the I (affects PRIMASK) and F (affects FAULTMASK) bits was reversed * the FAULTMASK system register number is 19, not 17
This fixes an issue reported as LP:913925....
arm: Add dummy support for co-processor 15's secure config register
Signed-off-by: Rob Herring <rob.herring@calxeda.com>Signed-off-by: Mark Langsdorf <mark.langsdorf@calxeda.com>Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
target-arm: Don't use cpu_single_env in bank_number()
Avoid using cpu_single_env in bank_number() -- if we werecalled via the gdb stub reading or writing the CPSR thenit is NULL and we will segfault if we take the cpu_abort().
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
target-arm: Ignore attempts to set invalid modes in CPSR
Ignore attempts to set the CPSR mode field to an invalid value.This is UNPREDICTABLE, but we should not cpu_abort() for thingsa malicious guest (or a confused user on the gdbstub interface)can provoke....
arm: add dummy A9-specific cp15 registers
Add dummy register support for the cp15, CRn=c15 registers.
config_base_register and power_control_register currentlydefault to 0, but may have improved support after the QOMCPU patches are finished.
target-arm: Infer VFPv3 feature from VFPv4
VFP4 => VFP3
Signed-off-by: Andreas Färber <andreas.faerber@web.de>Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
target-arm: Infer ARMv5 feature from ARMv6
V6 => V5
target-arm: Infer ARMv6 feature from v6K
V6K => V6
target-arm: Infer ARMv6(K) feature from ARMv7
V7 && M => V6V7 && !M => V6K
target-arm: Infer AUXCR feature from ARMv6
V6 && !M => AUXCR
target-arm: Infer Thumb2 feature from ARMv7
V7 => THUMB2
target-arm: Infer Thumb division feature from M profile
M => THUMB_DIV
target-arm: Infer VFP feature from VFPv3
VFP3 => VFP
arm: Fix CP15 FSR (C5) domain setting
Return the correct value in the domain field in the cp15 DFSR(C5) -- bug noticed during Xvisor development.
Signed-off-by: Jean-Christophe DUBOIS <jcd@tribudubois.net>[Peter Maydell: reworded commit message]Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
target-arm: Infer ARMv4T feature from ARMv5
V5 => V4T
target-arm/helper.c: Don't allocate TCG resources unless TCG enabled
Don't call arm_translate_init() (which allocates TCG resources)unless TCG is enabled.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>
target-arm/translate.c: Fix slightly misleading comment in Thumb decoder
Clarify some slightly misleading comments in the Thumb decoder'shandling of the memory hint space -- in particular one code pathmarked as 'UNPREDICTABLE or unallocated hint' also includes some...
target-arm: Fix use of free() in cpu_arm_close()
env is allocated in cpu_arm_init() with g_malloc0(), so free with g_free().
Signed-off-by: Andreas Färber <afaerber@suse.de>Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
target-arm: Implement VFPv4 fused multiply-accumulate insns
Implement the fused multiply-accumulate instructions (VFMA, VFMS,VFNMA, VFNMS) which are new in VFPv4.
target-arm/machine.c: Restore VFP registers correctly
Fix the restoring of VFP registers on vmload.
Signed-off-by: Dmitry Koshelev <karaghiozis@gmail.com>Reviewed-by: Juan Quintela <quintela@redhat.com>[peter.maydell: improved commit message a little]...
target-arm: Rename ARM_FEATURE_DIV to _THUMB_DIV
Rename the ARM_FEATURE_DIV feature bit to _THUMB_DIV, tomake room for a new feature switch enabling DIV in the ARMencoding. (Cores may implement either (a) no divide insns(b) divide insns in Thumb encodings only (c) divide insns...
target-arm: Add ARM UDIV/SDIV support
Add support for UDIV and SDIV in ARM mode. This is a new optionalfeature for A profile cores (Thumb mode has had UDIV and SDIV forM profile cores for some time).
rsqrte_f32: No need to copy sign bit.
Indeed, the result is known to be always positive.
Signed-off-by: Christophe Lyon <christophe.lyon@st.com>Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
target-arm: v6 media multiply space: UNDEF on unassigned encodings
Clean up the decoding of the v6 media multiply space so that we UNDEFon unassigned encodings rather than randomly interpreting them assome instruction in this space.
Merge remote-tracking branch 'stefanha/trivial-patches' into staging
ARM: fix segfault
Fix a bug in bccd9ec5f098668576342c83d90d6d6833d61d33,target-arm/op_helper.c missed a change unlike all other targets.This lead to a NULL pointer dereferences.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
target-arm: Fix typo
The command line option is called -kernel, not -kenrel.
Cc: Paul Brook <paul@codesourcery.com>Reviewed-by: Peter Maydell <peter.maydell@linaro.org>Signed-off-by: Andreas Färber <andreas.faerber@web.de>Signed-off-by: Stefan Hajnoczi <stefanha@linux.vnet.ibm.com>
softmmu_header: pass CPUState to tlb_fill
Pass CPUState pointer to tlb_fill() instead of architecture localcpu_single_env hacks.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Use glib memory allocation and free functions
qemu_malloc/qemu_free no longer exist after this commit.
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
Merge remote-tracking branch 'pm-arm/for-upstream' into pm
Remove unused is_softmmu parameter from cpu_handle_mmu_fault
Parameter is_softmmu (and its evil mutant twin brother is_softmuu)is not used in cpu_*_handle_mmu_fault() functions, remove themand adjust callers.
Acked-by: Richard Henderson <rth@twiddle.net>...
exec.h cleanup
Move softmmu_exec.h include directives from target-*/exec.h totarget-*/op_helper.c. Move also various other stuff only used inop_helper.c there.
Define global env in dyngen-exec.h.
For i386, move wrappers for segment and FPU helpers from user-exec.c...
target-arm: support for ARM1176JZF-s cores
Add support for v6K ARM1176JZF-S. This core includes the VA<->PAtranslation capability and security extensions.
Signed-off-by: Jamie Iles <jamie@jamieiles.com>Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
target-arm: Mark 1136r1 as a v6K core
The 1136r1 is actually a v6K core (unlike the 1136r0); mark it as such,thus enabling the TLS registers, NOP hints, CLREX, half and byte wideexclusive load/stores, etc.
The VA-to-PA translation registers are not present on 1136r1, so...
target-arm: Support v6 barriers in linux-user mode
ARMv6 implemented various operations as special cases of cp15 accesseswhich are true instructions in v7; this includes barriers (DMB, DSB, ISB).Catch this special case at translate time, so that it works in linux-user...
target-arm: Handle UNDEF and UNPREDICTABLE cases for VLDM, VSTM
Handle the UNDEF and UNPREDICTABLE cases for VLDM and VSTM. Inparticular, we now generate an undef exception for overlarge imm8values rather than generating 1000+ TCG ops and hitting an assertion....
target-arm: UNDEF on a VCVTT/VCVTB UNPREDICTABLE to avoid TCG assert
VCVTT/VCVTB with bit 8 set is UNPREDICTABLE; we choose to UNDEF.This avoids a TCG assert later when the VCVTT/VCVTB code tries touse a source register that wasn't ever set up.
We pull the check for the presence of the half-precision extension...
target-arm: Don't print debug messages for various UNDEF cases
Remove some stray printfs for cases which don't generally happen(some VFP UNDEF cases, reads and writes to unknown cp14 registers);we should simply generate an UNDEF when the instruction is executed....
target-arm: make VMSAv7 remapping and AP dependent on V6K
The VMSAv7 remapping and access permissions were introduced in ARMv6Kand not ARMv7.
Correct spelling of licensed
Correct typos of "licenced" to "licensed".
Reviewed-by: Stefan Weil <weil@mail.berlios.de>Reviewed-by: Andreas F=E4rber <andreas.faerber@web.de>Signed-off-by: Matthew Fernandez <matthew.fernandez@gmail.com>Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
Merge branch 'for-upstream' of git://git.linaro.org/people/pmaydell/qemu-arm
arm: Add const attribute to some arm_boot_info pointers
Parameter 'info' is const, so add the missing attribute.
v2:Add 'const' to the local variable info in do_cpu_reset() and tothe boot_info field in CPUARMState (suggested by Peter Maydell).
Cc: Andrzej Zaborowski <balrogg@gmail.com>...
Remove exec-all.h include directives
Most exec-all.h include directives are now useless, remove them.
Move cpu_has_work and cpu_pc_from_tb to cpu.h
Move functions cpu_has_work() and cpu_pc_from_tb() from exec.h to cpu.h. This isneeded by later patches.
exec.h: fix coding style and change cpu_has_work to return bool
Before the next patch, fix coding style of the areas affected.
Change the type of the return value from cpu_has_work() andqemu_cpu_has_work() to bool.
cpu_loop_exit: avoid using AREG0
Make cpu_loop_exit() take a parameter for CPUState instead of relyingon global env.
target-arm: Fix BASEPRI, BASEPRI_MAX, and FAULTMASK access
Correct the decode of the register numbers for BASEPRI, BASEPRI_MAXand FAULTMASK, according to "ARMv7-M Architecture Reference Manual" issue D section "B5.2.3 MRS" and "B5.2.3 MSR".
Signed-off-by: Sebastian Huber <sebastian.huber@embedded-brains.de>...
target-arm: Minimal implementation of performance counters
Newer Linux kernels assume the existence of the performance countercp15 registers. Provide a minimal implementation of these registers.We support no events. This should be compliant with the ARM ARM,...
Revert "target-arm: Use global env in neon_helper.c helpers"
This effectively reverts commit 2a3f75b42ac255be09ec2939b96c549ec830efd3so that we return to passing CPUState to helpers as an explicit parameter.(There were a number of conflicts in target-arm/translate.c which had...
target-arm: Pass fp status pointer explicitly to neon fp helpers
Make the Neon helpers for various floating point operations take anexplicit pointer to the float_status they use, so they don't rely onthe global environment pointer any more. This also allows us to drop...
target-arm: Make VFP binop helpers take pointer to fpstatus, not CPUState
Make the VFP binop helper functions take a pointer to the fp status, notthe entire CPUState. This will allow us to use them for Neon operations too.
target-arm: Add helper function to generate code to get fpstatus pointer
Add and use a helper function which returns a TCGv which is a pointerto the fp_status for either Neon or VFP operations.
Revert "target-arm: Use global env in iwmmxt_helper.c helpers"
This reverts commit 947a2fa21b61703802a660a938cabd7b3600ee79,returning the iwmmxt helpers to passing env in as a parameter.
target-arm: BKPT instructions should raise prefetch aborts with IFSR type 00010
Signed-off-by: Alex Zuepke <azuepke@sysgo.com>Reviewed-by: Peter Maydell <peter.maydell@linaro.org>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-arm: Fix compilation failure for 64 bit hosts
Use the correct _ptr aliases for manipulating the pointer tothe fp_status; this fixes a compilation failure on 64 bit hosts.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>Acked-by: Stefan Weil <weil@mail.berlios.de>...
target-arm/exec.h: Remove unused #define of M0
Remove a preprocessor #define which is never used.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-arm: Signal Underflow when denormal flushed to zero on output
On ARM the architecture mandates that when an output denormal is flushed tozero we must set the FPSCR UFC (underflow) bit, so map softfloat'sfloat_flag_output_denormal accordingly.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>...
target-arm: Use correct float status for Neon int-float conversions
The Neon versions of int-float conversions must use the "standard FPSCR" rather than the default FPSCR. Implement this by having the helperfunctions take a pointer to the appropriate float_status value rather...
target-arm: Signal InvalidOp for Neon GE and GT compares of QNaN
If the input to a Neon float comparison is a quiet NaN, the ARM ARMspecifies that we should raise InvalidOp if the comparison is GE or GTbut not for EQ. (Signaling NaNs raise InvalidOp regardless). This means...
target-arm: Signal InputDenormal for VRECPE, VRSQRTE, VRECPS, VRSQRTS
The helpers for VRECPE.F32, VSQRTE.F32, VRECPS and VRSQRTS handle denormalsas special cases, so we must set the InputDenormal exception flag ourselves.
target-arm: Don't set FP exceptions in recip, recip_sqrt estimate fns
The functions which do the core estimation algorithms for the VRSQRTEand VRECPE instructions should not set floating point exception flags,so use a local fp status for doing these calculations....
target-arm: Fix VMLA, VMLS, VNMLS, VNMLA handling of NaNs
Correct handling of NaNs for VFP VMLA, VMLS, VNMLS and VNMLA requires thatwe implement the set of negations and additions specified by the ARM ARM;plausible looking simplifications like turning (-A + B) into (B - A) or...
Conflicts: cpu-all.h
target-arm: Privatize CPU_INTERRUPT_FIQ.
This interrupt name was only used by the ARM port.
Signed-off-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Fix typos in comments (neccessary -> necessary)
Signed-off-by: Stefan Weil <weil@mail.berlios.de>Signed-off-by: Stefan Hajnoczi <stefanha@linux.vnet.ibm.com>
Fix typos in comments and code (occured -> occurred and related)
The code changed here is an unused data type name (evt_flush_occurred).
target-arm: Don't update base register on abort in Thumb T1 LDM
Make sure the base register isn't updated if it is in the load listfor a Thumb LDM (T1 encoding) which aborts partway through the load.
target-arm: fix LDMIA bug on page boundarytarget-arm: fix LDMIA bug on page boundary
When consecutive memory locations are on page boundary, a base register may beloaded before page fault occurs. After page fault handling, it losts the memorylocation information. To solve this problem, loading a base register has to put back....
target-arm: Handle UNDEF cases for Neon VLD/VST multiple-structures
Correctly UNDEF for Neon VLD/VST "multiple structures" forms where thealign field is not valid.
target-arm: Handle UNDEFs for Neon single element load/stores
Handle the UNDEF and UNPREDICTABLE cases for Neon "single element toone lane" VLD and "single element from one lane" VST.
target-arm: Set Invalid flag for NaN in float-to-int conversions
When we catch the special case of an input NaN in ARM float to inthelper functions, set the Invalid flag as well as returning thecorrect result.
Implement basic part of SA-1110/SA-1100
Basic implementation of DEC/Intel SA-1100/SA-1110 chips emulation.Implemented: - IRQs - GPIO - PPC - RTC - UARTs (no IrDA/etc.) - OST reused from pxa25x
Everything else is TODO (esp. PM/idle/sleep!) - see the todo in the...
Remove unused function parameter from cpu_restore_state
The previous patch removed the need for parameter puc.Is is now unused, so remove it.
Cc: Aurelien Jarno <aurelien@aurel32.net>Reviewed-by: Peter Maydell <peter.maydell@linaro.org>Signed-off-by: Stefan Weil <weil@mail.berlios.de>
Remove unused function parameters from gen_pc_load and rename the function
Function gen_pc_load was introduced in commitd2856f1ad4c259e5766847c49acbb4e390731bd4.The only reason for parameter searched_pc wasa debug statement in target-i386/translate.c....
move helpers.h to helper.h
This provides a consistent naming scheme across all targets.
Signed-off-by: Lluís Vilanova <vilanova@ac.upc.edu>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Fix some typos in comments and documentation
helpfull -> helpfulusefull -> usefulcotrol -> control
and a grammar fix.
target-arm: Don't overflow when calculating value for signed VABAL
In the VABAL instruction we take the absolute difference of twovalues of size x and store it in a result of size 2x. This meanswe have to be careful to calculate the absolute difference using...
target-arm: Handle UNDEF cases for Neon invalid modified-immediates
For Neon "one register and a modified immediate value" forms, thecombination op=1 cmode=1111 is unallocated and should UNDEF.All instructions of this form also UNDEF if Q 1 and Vd<0> 1....
target-arm: Handle UNDEF cases for Neon 3-regs-different-widths
Add missing UNDEF checks for instructions in the Neon "3 registers ofdifferent widths" data processing space.
target-arm: Handle UNDEF cases for Neon 2 regs + scalar forms
Add missing checks for cases which must UNDEF in the Neon "2 registers anda scalar" data processing instruction space.
target-arm: Handle UNDEF cases for VEXT
VEXT must UNDEF if Q 1 && (Vd<0> 1 || Vr<0> 1 || Vm<0> 1)
target-arm: Simplify checking of size field in Neon 2reg-misc forms
Many of the Neon "2 register misc" instruction forms require invalidsize fields to cause the instruction to UNDEF. Pull this informationout into an array; this simplifies the code and also means we can do...
target-arm: Handle UNDEF cases for Neon 2 register misc forms
Add missing UNDEF checks for Neon "two register miscellaneous" forms: * all instructions except VMOVN,VQMOVN must UNDEF if Q==1 && (Vd<0> 1 || Vm<0> 1) * VMOVN,VQMOVN,VCVT.F16.F32 UNDEF if Q 1 || Vm<0> 1...
target-arm: Treat UNPREDICTABLE VTBL, VTBX case as UNDEF
Catch the UNPREDICTABLE case for Neon VTBL,VTBX, and UNDEF itrather than allowing the helper function to index off the endof the register file.
target-arm: Handle UNDEF cases for VDUP (scalar)
Handle the UNDEF cases for VDUP: imm4 x000 Q 1 && Vd<0> == 1
Signed-off-by: Juha Riihimäki <juha.riihimaki@nokia.com>Reviewed-by: Peter Maydell <peter.maydell@linaro.org>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-arm: Detect tininess before rounding for FP operations
The ARM architecture mandates that we detect tininess before rounding,so set the softfloat fp_status up appropriately.
target-arm: Collapse VSRI case into VSHL, VSLI
Collapse some switch cases for VSRI into those for VSHL, VSLI,since the bodies are the same. (This is not completely obviousfor the size < 3 case, but since for VSRI we know U=1 theGEN_NEON_INTEGER_OP() expansion is equivalent to the open-coded...
target-arm: Use lookup table for size check on Neon 3-reg-same insns
Simplify the checks for invalid size values for the Neon "three registersof the same size" instruction forms (and add them where they were missing)by using a lookup table.
This includes adding symbolic constants for the op values in this space,...
target-arm: Handle UNDEF cases for Neon 3-regs-same insns
Correct the handling of UNDEF cases for the NEON "3 registers samesize" forms, by adding missing checks and rationalising some othersso they are done early enough to avoid leaking TCG temporaries....
target-arm: Simplify three-register pairwise code
Since we know that the case of (pairwise && q) has been caughtearlier, we can simplify the register setup code for each passin the three-register-same-size Neon loop.
Signed-off-by: Juha Riihimäki <juha.riihimaki@nokia.com>...
target-arm: Handle UNDEF cases for Neon "2 regs and shift" insns
Correctly handle all the UNDEF cases for Neon instructions of the"2 registers and shift" form, and make sure that we check for thesecases early enough not to leak TCG temporaries.
arm: basic support for ARMv4/ARMv4T emulation
Currently target-arm/ assumes at least ARMv5 core. Add support forhandling also ARMv4/ARMv4T. This changes the following instructions:
BX
BKPT, BLX, CDP2, CLZ, LDC2, LDRD, MCRR, MCRR2, MRRC, MCRR, MRC2, MRRC,...
Fix conversions from pointer to tcg_target_long
tcg_gen_exit_tb takes a parameter of type tcg_target_long,so the type casts of pointer to long should be replaced bytype casts of pointer to tcg_target_long (suggested by Blue Swirl).
These changes are needed for build environments where...
target-arm: Use global env in iwmmxt_helper.c helpers
Use the global 'env' variable in the helper functions in iwmmxt_helper.c.This means we don't need to pass env as an argument to them any more.
target-arm: Make Neon helper routines use correct FP status
Make the Neon helper routines use the correct FP status fromthe CPUEnv rather than using a dummy static one. This meansthey will correctly handle denormals and NaNs and will setFPSCR exception bits properly....