Revision 774d5c5b target-cris/translate_v10.c
| b/target-cris/translate_v10.c | ||
|---|---|---|
| 62 | 62 |
t_gen_raise_exception(EXCP_BREAK); |
| 63 | 63 |
} |
| 64 | 64 |
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| 65 |
static void gen_store_v10_conditional(DisasContext *dc, TCGv addr, TCGv val, |
|
| 66 |
unsigned int size, int mem_index) |
|
| 67 |
{
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int l1 = gen_new_label(); |
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| 69 |
TCGv taddr = tcg_temp_local_new(); |
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| 70 |
TCGv tval = tcg_temp_local_new(); |
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TCGv t1 = tcg_temp_local_new(); |
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| 72 |
dc->postinc = 0; |
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| 73 |
cris_evaluate_flags(dc); |
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| 74 |
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tcg_gen_mov_tl(taddr, addr); |
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tcg_gen_mov_tl(tval, val); |
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| 77 |
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/* Store only if F flag isn't set */ |
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tcg_gen_andi_tl(t1, cpu_PR[PR_CCS], F_FLAG_V10); |
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tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1); |
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if (size == 1) {
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tcg_gen_qemu_st8(tval, taddr, mem_index); |
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} else if (size == 2) {
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tcg_gen_qemu_st16(tval, taddr, mem_index); |
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} else {
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tcg_gen_qemu_st32(tval, taddr, mem_index); |
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} |
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gen_set_label(l1); |
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tcg_gen_shri_tl(t1, t1, 1); /* shift F to P position */ |
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tcg_gen_or_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], t1); /*P=F*/ |
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tcg_temp_free(t1); |
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tcg_temp_free(tval); |
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tcg_temp_free(taddr); |
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} |
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|
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static void gen_store_v10(DisasContext *dc, TCGv addr, TCGv val, |
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unsigned int size) |
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{
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int mem_index = cpu_mmu_index(dc->env); |
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/* If we get a fault on a delayslot we must keep the jmp state in |
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the cpu-state to be able to re-execute the jmp. */ |
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if (dc->delayed_branch == 1) {
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cris_store_direct_jmp(dc); |
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} |
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/* Conditional writes. We only support the kind were X is known |
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at translation time. */ |
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if (dc->flagx_known && dc->flags_x) {
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gen_store_v10_conditional(dc, addr, val, size, mem_index); |
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return; |
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} |
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if (size == 1) {
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tcg_gen_qemu_st8(val, addr, mem_index); |
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} else if (size == 2) {
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tcg_gen_qemu_st16(val, addr, mem_index); |
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} else {
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tcg_gen_qemu_st32(val, addr, mem_index); |
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} |
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} |
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|
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| 65 | 124 |
/* Prefix flag and register are used to handle the more complex |
| 66 | 125 |
addressing modes. */ |
| 67 | 126 |
static void cris_set_prefix(DisasContext *dc) |
| ... | ... | |
| 313 | 372 |
if (set) {
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| 314 | 373 |
tcg_gen_ori_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], flags); |
| 315 | 374 |
} else {
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tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~flags); |
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tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], |
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~(flags|F_FLAG_V10|P_FLAG_V10)); |
|
| 317 | 377 |
} |
| 318 | 378 |
|
| 319 | 379 |
dc->flags_uptodate = 1; |
| ... | ... | |
| 723 | 783 |
LOG_DIS("move.%d $r%d, [$r%d]\n", dc->size, dc->src, dc->dst);
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| 724 | 784 |
addr = tcg_temp_new(); |
| 725 | 785 |
crisv10_prepare_memaddr(dc, addr, size); |
| 726 |
gen_store(dc, addr, cpu_R[dc->dst], size); |
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gen_store_v10(dc, addr, cpu_R[dc->dst], size);
|
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| 727 | 787 |
insn_len += crisv10_post_memaddr(dc, size); |
| 728 | 788 |
|
| 729 | 789 |
return insn_len; |
| ... | ... | |
| 767 | 827 |
t0 = tcg_temp_new(); |
| 768 | 828 |
cris_evaluate_flags(dc); |
| 769 | 829 |
tcg_gen_andi_tl(t0, cpu_PR[PR_CCS], ~PFIX_FLAG); |
| 770 |
gen_store(dc, addr, t0, size); |
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gen_store_v10(dc, addr, t0, size);
|
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| 771 | 831 |
tcg_temp_free(t0); |
| 772 | 832 |
} else {
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gen_store(dc, addr, cpu_PR[dc->dst], size); |
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gen_store_v10(dc, addr, cpu_PR[dc->dst], size);
|
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| 774 | 834 |
} |
| 775 | 835 |
t0 = tcg_temp_new(); |
| 776 | 836 |
insn_len += crisv10_post_memaddr(dc, size); |
| ... | ... | |
| 793 | 853 |
tcg_gen_mov_tl(t0, addr); |
| 794 | 854 |
for (i = dc->dst; i >= 0; i--) {
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| 795 | 855 |
if ((pfix && dc->mode == CRISV10_MODE_AUTOINC) && dc->src == i) {
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gen_store(dc, addr, t0, 4); |
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gen_store_v10(dc, addr, t0, 4);
|
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| 797 | 857 |
} else {
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gen_store(dc, addr, cpu_R[i], 4); |
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gen_store_v10(dc, addr, cpu_R[i], 4);
|
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| 799 | 859 |
} |
| 800 | 860 |
tcg_gen_addi_tl(addr, addr, 4); |
| 801 | 861 |
} |
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