Revision 777dc784 target-arm/helper.c
| b/target-arm/helper.c | ||
|---|---|---|
| 46 | 46 |
static uint32_t arm1176_cp15_c0_c2[8] = |
| 47 | 47 |
{ 0x0140011, 0x12002111, 0x11231121, 0x01102131, 0x01141, 0, 0, 0 };
|
| 48 | 48 |
|
| 49 |
static uint32_t cpu_arm_find_by_name(const char *name); |
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| 50 |
|
|
| 51 | 49 |
static inline void set_feature(CPUARMState *env, int feature) |
| 52 | 50 |
{
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| 53 | 51 |
env->features |= 1u << feature; |
| ... | ... | |
| 55 | 53 |
|
| 56 | 54 |
static void cpu_reset_model_id(CPUARMState *env, uint32_t id) |
| 57 | 55 |
{
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env->cp15.c0_cpuid = id; |
|
| 59 | 56 |
switch (id) {
|
| 60 | 57 |
case ARM_CPUID_ARM926: |
| 61 | 58 |
set_feature(env, ARM_FEATURE_V5); |
| ... | ... | |
| 201 | 198 |
case ARM_CPUID_TI925T: |
| 202 | 199 |
set_feature(env, ARM_FEATURE_V4T); |
| 203 | 200 |
set_feature(env, ARM_FEATURE_OMAPCP); |
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env->cp15.c0_cpuid = ARM_CPUID_TI925T; /* Depends on wiring. */ |
|
| 205 | 201 |
env->cp15.c0_cachetype = 0x5109149; |
| 206 | 202 |
env->cp15.c1_sys = 0x00000070; |
| 207 | 203 |
env->cp15.c15_i_max = 0x000; |
| ... | ... | |
| 287 | 283 |
{
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uint32_t id; |
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uint32_t tmp = 0; |
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ARMCPU *cpu = arm_env_get_cpu(env); |
|
| 290 | 287 |
|
| 291 | 288 |
if (qemu_loglevel_mask(CPU_LOG_RESET)) {
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| 292 | 289 |
qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
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| 293 | 290 |
log_cpu_state(env, 0); |
| 294 | 291 |
} |
| 295 | 292 |
|
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id = env->cp15.c0_cpuid;
|
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id = cpu->midr;
|
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| 297 | 294 |
tmp = env->cp15.c15_config_base_address; |
| 298 | 295 |
memset(env, 0, offsetof(CPUARMState, breakpoints)); |
| 299 | 296 |
if (id) |
| 300 | 297 |
cpu_reset_model_id(env, id); |
| 301 | 298 |
env->cp15.c15_config_base_address = tmp; |
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env->cp15.c0_cpuid = cpu->midr; |
|
| 302 | 300 |
#if defined (CONFIG_USER_ONLY) |
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env->uncached_cpsr = ARM_CPU_MODE_USR; |
| 304 | 302 |
/* For user mode we must enable access to coprocessors */ |
| ... | ... | |
| 407 | 405 |
{
|
| 408 | 406 |
ARMCPU *cpu; |
| 409 | 407 |
CPUARMState *env; |
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uint32_t id; |
|
| 411 | 408 |
static int inited = 0; |
| 412 | 409 |
|
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id = cpu_arm_find_by_name(cpu_model); |
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if (id == 0) |
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if (!object_class_by_name(cpu_model)) {
|
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| 415 | 411 |
return NULL; |
| 416 |
cpu = ARM_CPU(object_new(TYPE_ARM_CPU)); |
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} |
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cpu = ARM_CPU(object_new(cpu_model)); |
|
| 417 | 414 |
env = &cpu->env; |
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cpu_exec_init(env); |
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env->cpu_model_str = cpu_model; |
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|
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| 419 | 417 |
if (tcg_enabled() && !inited) {
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| 420 | 418 |
inited = 1; |
| 421 | 419 |
arm_translate_init(); |
| 422 | 420 |
} |
| 423 | 421 |
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env->cpu_model_str = cpu_model; |
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env->cp15.c0_cpuid = id; |
|
| 426 | 422 |
cpu_state_reset(env); |
| 427 | 423 |
if (arm_feature(env, ARM_FEATURE_NEON)) {
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| 428 | 424 |
gdb_register_coprocessor(env, vfp_gdb_get_reg, vfp_gdb_set_reg, |
| ... | ... | |
| 438 | 434 |
return env; |
| 439 | 435 |
} |
| 440 | 436 |
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struct arm_cpu_t {
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uint32_t id; |
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const char *name; |
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}; |
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|
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static const struct arm_cpu_t arm_cpu_names[] = {
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{ ARM_CPUID_ARM926, "arm926"},
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{ ARM_CPUID_ARM946, "arm946"},
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{ ARM_CPUID_ARM1026, "arm1026"},
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{ ARM_CPUID_ARM1136, "arm1136"},
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{ ARM_CPUID_ARM1136_R2, "arm1136-r2"},
|
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{ ARM_CPUID_ARM1176, "arm1176"},
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{ ARM_CPUID_ARM11MPCORE, "arm11mpcore"},
|
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{ ARM_CPUID_CORTEXM3, "cortex-m3"},
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{ ARM_CPUID_CORTEXA8, "cortex-a8"},
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{ ARM_CPUID_CORTEXA9, "cortex-a9"},
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{ ARM_CPUID_CORTEXA15, "cortex-a15" },
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{ ARM_CPUID_TI925T, "ti925t" },
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{ ARM_CPUID_PXA250, "pxa250" },
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{ ARM_CPUID_SA1100, "sa1100" },
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{ ARM_CPUID_SA1110, "sa1110" },
|
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{ ARM_CPUID_PXA255, "pxa255" },
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{ ARM_CPUID_PXA260, "pxa260" },
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{ ARM_CPUID_PXA261, "pxa261" },
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{ ARM_CPUID_PXA262, "pxa262" },
|
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{ ARM_CPUID_PXA270, "pxa270" },
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{ ARM_CPUID_PXA270_A0, "pxa270-a0" },
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{ ARM_CPUID_PXA270_A1, "pxa270-a1" },
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{ ARM_CPUID_PXA270_B0, "pxa270-b0" },
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{ ARM_CPUID_PXA270_B1, "pxa270-b1" },
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{ ARM_CPUID_PXA270_C0, "pxa270-c0" },
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{ ARM_CPUID_PXA270_C5, "pxa270-c5" },
|
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{ ARM_CPUID_ANY, "any"},
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{ 0, NULL}
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}; |
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typedef struct ARMCPUListState {
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fprintf_function cpu_fprintf; |
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FILE *file; |
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} ARMCPUListState; |
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| 476 | 441 |
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void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf) |
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/* Sort alphabetically by type name, except for "any". */ |
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static gint arm_cpu_list_compare(gconstpointer a, gconstpointer b) |
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| 478 | 444 |
{
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int i; |
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ObjectClass *class_a = (ObjectClass *)a; |
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ObjectClass *class_b = (ObjectClass *)b; |
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const char *name_a, *name_b; |
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| 480 | 448 |
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(*cpu_fprintf)(f, "Available CPUs:\n"); |
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for (i = 0; arm_cpu_names[i].name; i++) {
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(*cpu_fprintf)(f, " %s\n", arm_cpu_names[i].name); |
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name_a = object_class_get_name(class_a); |
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name_b = object_class_get_name(class_b); |
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if (strcmp(name_a, "any") == 0) {
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return 1; |
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} else if (strcmp(name_b, "any") == 0) {
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return -1; |
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} else {
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return strcmp(name_a, name_b); |
|
| 484 | 457 |
} |
| 485 | 458 |
} |
| 486 | 459 |
|
| 487 |
/* return 0 if not found */ |
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static uint32_t cpu_arm_find_by_name(const char *name) |
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static void arm_cpu_list_entry(gpointer data, gpointer user_data) |
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| 489 | 461 |
{
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| 490 |
int i;
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uint32_t id;
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ObjectClass *oc = data;
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ARMCPUListState *s = user_data;
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| 492 | 464 |
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id = 0; |
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for (i = 0; arm_cpu_names[i].name; i++) {
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if (strcmp(name, arm_cpu_names[i].name) == 0) {
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id = arm_cpu_names[i].id; |
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break; |
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} |
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} |
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return id; |
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(*s->cpu_fprintf)(s->file, " %s\n", |
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object_class_get_name(oc)); |
|
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} |
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| 468 |
|
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void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf) |
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{
|
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| 471 |
ARMCPUListState s = {
|
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.file = f, |
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.cpu_fprintf = cpu_fprintf, |
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}; |
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GSList *list; |
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| 476 |
|
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list = object_class_get_list(TYPE_ARM_CPU, false); |
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list = g_slist_sort(list, arm_cpu_list_compare); |
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(*cpu_fprintf)(f, "Available CPUs:\n"); |
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| 480 |
g_slist_foreach(list, arm_cpu_list_entry, &s); |
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| 481 |
g_slist_free(list); |
|
| 501 | 482 |
} |
| 502 | 483 |
|
| 503 | 484 |
static int bad_mode_switch(CPUARMState *env, int mode) |
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