root / target-ppc / exec.h @ 77b73de6
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1 | 79aceca5 | bellard | /*
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2 | 3fc6c082 | bellard | * PowerPC emulation definitions for qemu.
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3 | 5fafdf24 | ths | *
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4 | 76a66253 | j_mayer | * Copyright (c) 2003-2007 Jocelyn Mayer
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5 | 79aceca5 | bellard | *
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6 | 79aceca5 | bellard | * This library is free software; you can redistribute it and/or
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7 | 79aceca5 | bellard | * modify it under the terms of the GNU Lesser General Public
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8 | 79aceca5 | bellard | * License as published by the Free Software Foundation; either
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9 | 79aceca5 | bellard | * version 2 of the License, or (at your option) any later version.
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10 | 79aceca5 | bellard | *
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11 | 79aceca5 | bellard | * This library is distributed in the hope that it will be useful,
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12 | 79aceca5 | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | 79aceca5 | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | 79aceca5 | bellard | * Lesser General Public License for more details.
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15 | 79aceca5 | bellard | *
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16 | 79aceca5 | bellard | * You should have received a copy of the GNU Lesser General Public
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17 | 79aceca5 | bellard | * License along with this library; if not, write to the Free Software
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18 | 79aceca5 | bellard | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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19 | 79aceca5 | bellard | */
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20 | 79aceca5 | bellard | #if !defined (__PPC_H__)
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21 | 79aceca5 | bellard | #define __PPC_H__
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22 | 79aceca5 | bellard | |
23 | fdabc366 | bellard | #include "config.h" |
24 | fdabc366 | bellard | |
25 | 79aceca5 | bellard | #include "dyngen-exec.h" |
26 | 79aceca5 | bellard | |
27 | 76a66253 | j_mayer | #include "cpu.h" |
28 | 76a66253 | j_mayer | #include "exec-all.h" |
29 | fdabc366 | bellard | |
30 | 1cdb9c3d | aurel32 | /* For normal operations, precise emulation should not be needed */
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31 | 1cdb9c3d | aurel32 | //#define USE_PRECISE_EMULATION 1
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32 | 1cdb9c3d | aurel32 | #define USE_PRECISE_EMULATION 0 |
33 | 1cdb9c3d | aurel32 | |
34 | 79aceca5 | bellard | register struct CPUPPCState *env asm(AREG0); |
35 | 76a66253 | j_mayer | #if TARGET_LONG_BITS > HOST_LONG_BITS
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36 | 76a66253 | j_mayer | /* no registers can be used */
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37 | 76a66253 | j_mayer | #define T0 (env->t0)
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38 | 76a66253 | j_mayer | #define T1 (env->t1)
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39 | 76a66253 | j_mayer | #define T2 (env->t2)
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40 | 6b542af7 | j_mayer | #define TDX "%016" PRIx64 |
41 | 76a66253 | j_mayer | #else
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42 | 76a66253 | j_mayer | register unsigned long T0 asm(AREG1); |
43 | 76a66253 | j_mayer | register unsigned long T1 asm(AREG2); |
44 | 76a66253 | j_mayer | register unsigned long T2 asm(AREG3); |
45 | 6b542af7 | j_mayer | #define TDX "%016lx" |
46 | 76a66253 | j_mayer | #endif
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47 | 57c26279 | j_mayer | /* We may, sometime, need 64 bits registers on 32 bits targets */
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48 | 57c26279 | j_mayer | #if (HOST_LONG_BITS == 32) |
49 | d9bce9d9 | j_mayer | /* no registers can be used */
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50 | d9bce9d9 | j_mayer | #define T0_64 (env->t0)
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51 | d9bce9d9 | j_mayer | #define T1_64 (env->t1)
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52 | d9bce9d9 | j_mayer | #define T2_64 (env->t2)
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53 | 3c4c9f9f | ths | #else
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54 | 3c4c9f9f | ths | #define T0_64 T0
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55 | 3c4c9f9f | ths | #define T1_64 T1
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56 | 3c4c9f9f | ths | #define T2_64 T2
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57 | 76a66253 | j_mayer | #endif
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58 | d9bce9d9 | j_mayer | /* Provision for Altivec */
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59 | a9d9eb8f | j_mayer | #define AVR0 (env->avr0)
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60 | a9d9eb8f | j_mayer | #define AVR1 (env->avr1)
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61 | a9d9eb8f | j_mayer | #define AVR2 (env->avr2)
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62 | 79aceca5 | bellard | |
63 | fb0eaffc | bellard | #define FT0 (env->ft0)
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64 | fb0eaffc | bellard | #define FT1 (env->ft1)
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65 | fb0eaffc | bellard | #define FT2 (env->ft2)
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66 | 79aceca5 | bellard | |
67 | a541f297 | bellard | #if defined (DEBUG_OP)
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68 | 70ead434 | ths | # define RETURN() __asm__ __volatile__("nop" : : : "memory"); |
69 | a541f297 | bellard | #else
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70 | 70ead434 | ths | # define RETURN() __asm__ __volatile__("" : : : "memory"); |
71 | a541f297 | bellard | #endif
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72 | 79aceca5 | bellard | |
73 | b068d6a7 | j_mayer | static always_inline target_ulong rotl8 (target_ulong i, int n) |
74 | 76a66253 | j_mayer | { |
75 | 76a66253 | j_mayer | return (((uint8_t)i << n) | ((uint8_t)i >> (8 - n))); |
76 | 76a66253 | j_mayer | } |
77 | 76a66253 | j_mayer | |
78 | b068d6a7 | j_mayer | static always_inline target_ulong rotl16 (target_ulong i, int n) |
79 | 76a66253 | j_mayer | { |
80 | 76a66253 | j_mayer | return (((uint16_t)i << n) | ((uint16_t)i >> (16 - n))); |
81 | 76a66253 | j_mayer | } |
82 | 79aceca5 | bellard | |
83 | b068d6a7 | j_mayer | static always_inline target_ulong rotl32 (target_ulong i, int n) |
84 | 79aceca5 | bellard | { |
85 | 76a66253 | j_mayer | return (((uint32_t)i << n) | ((uint32_t)i >> (32 - n))); |
86 | 79aceca5 | bellard | } |
87 | 79aceca5 | bellard | |
88 | 76a66253 | j_mayer | #if defined(TARGET_PPC64)
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89 | b068d6a7 | j_mayer | static always_inline target_ulong rotl64 (target_ulong i, int n) |
90 | 76a66253 | j_mayer | { |
91 | 76a66253 | j_mayer | return (((uint64_t)i << n) | ((uint64_t)i >> (64 - n))); |
92 | 76a66253 | j_mayer | } |
93 | 76a66253 | j_mayer | #endif
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94 | 76a66253 | j_mayer | |
95 | 9a64fbe4 | bellard | #if !defined(CONFIG_USER_ONLY)
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96 | a9049a07 | bellard | #include "softmmu_exec.h" |
97 | 9a64fbe4 | bellard | #endif /* !defined(CONFIG_USER_ONLY) */ |
98 | 79aceca5 | bellard | |
99 | 9fddaa0c | bellard | void do_raise_exception_err (uint32_t exception, int error_code); |
100 | 9fddaa0c | bellard | void do_raise_exception (uint32_t exception);
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101 | 79aceca5 | bellard | |
102 | 76a66253 | j_mayer | int get_physical_address (CPUState *env, mmu_ctx_t *ctx, target_ulong vaddr,
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103 | faadf50e | j_mayer | int rw, int access_type); |
104 | 79aceca5 | bellard | |
105 | 76a66253 | j_mayer | void ppc6xx_tlb_store (CPUState *env, target_ulong EPN, int way, int is_code, |
106 | 76a66253 | j_mayer | target_ulong pte0, target_ulong pte1); |
107 | 9a64fbe4 | bellard | |
108 | b068d6a7 | j_mayer | static always_inline void env_to_regs (void) |
109 | 0d1a29f9 | bellard | { |
110 | 0d1a29f9 | bellard | } |
111 | 0d1a29f9 | bellard | |
112 | b068d6a7 | j_mayer | static always_inline void regs_to_env (void) |
113 | 0d1a29f9 | bellard | { |
114 | 0d1a29f9 | bellard | } |
115 | 0d1a29f9 | bellard | |
116 | 76a66253 | j_mayer | int cpu_ppc_handle_mmu_fault (CPUState *env, target_ulong address, int rw, |
117 | 6ebbf390 | j_mayer | int mmu_idx, int is_softmmu); |
118 | 0fa85d43 | bellard | |
119 | b068d6a7 | j_mayer | static always_inline int cpu_halted (CPUState *env) |
120 | 36081602 | j_mayer | { |
121 | bfed01fc | ths | if (!env->halted)
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122 | bfed01fc | ths | return 0; |
123 | 0411a972 | j_mayer | if (msr_ee && (env->interrupt_request & CPU_INTERRUPT_HARD)) {
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124 | bfed01fc | ths | env->halted = 0;
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125 | bfed01fc | ths | return 0; |
126 | bfed01fc | ths | } |
127 | bfed01fc | ths | return EXCP_HALTED;
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128 | bfed01fc | ths | } |
129 | bfed01fc | ths | |
130 | 79aceca5 | bellard | #endif /* !defined (__PPC_H__) */ |