Revision 77f193da hw/slavio_intctl.c
| b/hw/slavio_intctl.c | ||
|---|---|---|
| 99 | 99 |
return ret; |
| 100 | 100 |
} |
| 101 | 101 |
|
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static void slavio_intctl_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val) |
|
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static void slavio_intctl_mem_writel(void *opaque, target_phys_addr_t addr, |
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uint32_t val) |
|
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{
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SLAVIO_INTCTLState *s = opaque; |
| 105 | 106 |
uint32_t saddr; |
| ... | ... | |
| 115 | 116 |
val &= CPU_SOFTIRQ_MASK; |
| 116 | 117 |
s->intreg_pending[cpu] &= ~val; |
| 117 | 118 |
slavio_check_interrupts(s); |
| 118 |
DPRINTF("Cleared cpu %d irq mask %x, curmask %x\n", cpu, val, s->intreg_pending[cpu]);
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DPRINTF("Cleared cpu %d irq mask %x, curmask %x\n", cpu, val,
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s->intreg_pending[cpu]); |
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| 119 | 121 |
break; |
| 120 | 122 |
case 2: // set softint |
| 121 | 123 |
val &= CPU_SOFTIRQ_MASK; |
| 122 | 124 |
s->intreg_pending[cpu] |= val; |
| 123 | 125 |
slavio_check_interrupts(s); |
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DPRINTF("Set cpu %d irq mask %x, curmask %x\n", cpu, val, s->intreg_pending[cpu]);
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DPRINTF("Set cpu %d irq mask %x, curmask %x\n", cpu, val,
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s->intreg_pending[cpu]); |
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| 125 | 128 |
break; |
| 126 | 129 |
default: |
| 127 | 130 |
break; |
| ... | ... | |
| 166 | 169 |
return ret; |
| 167 | 170 |
} |
| 168 | 171 |
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static void slavio_intctlm_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val) |
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static void slavio_intctlm_mem_writel(void *opaque, target_phys_addr_t addr, |
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uint32_t val) |
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| 170 | 174 |
{
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SLAVIO_INTCTLState *s = opaque; |
| 172 | 176 |
uint32_t saddr; |
| ... | ... | |
| 178 | 182 |
// Force clear unused bits |
| 179 | 183 |
val &= MASTER_IRQ_MASK; |
| 180 | 184 |
s->intregm_disabled &= ~val; |
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DPRINTF("Enabled master irq mask %x, curmask %x\n", val, s->intregm_disabled);
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DPRINTF("Enabled master irq mask %x, curmask %x\n", val,
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s->intregm_disabled); |
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| 182 | 187 |
slavio_check_interrupts(s); |
| 183 | 188 |
break; |
| 184 | 189 |
case 3: // set (disable, clear pending) |
| ... | ... | |
| 187 | 192 |
s->intregm_disabled |= val; |
| 188 | 193 |
s->intregm_pending &= ~val; |
| 189 | 194 |
slavio_check_interrupts(s); |
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DPRINTF("Disabled master irq mask %x, curmask %x\n", val, s->intregm_disabled);
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DPRINTF("Disabled master irq mask %x, curmask %x\n", val,
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s->intregm_disabled); |
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| 191 | 197 |
break; |
| 192 | 198 |
case 4: |
| 193 | 199 |
s->target_cpu = val & (MAX_CPUS - 1); |
| ... | ... | |
| 219 | 225 |
for (i = 0; i < MAX_CPUS; i++) {
|
| 220 | 226 |
term_printf("per-cpu %d: pending 0x%08x\n", i, s->intreg_pending[i]);
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| 221 | 227 |
} |
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term_printf("master: pending 0x%08x, disabled 0x%08x\n", s->intregm_pending, s->intregm_disabled);
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term_printf("master: pending 0x%08x, disabled 0x%08x\n",
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s->intregm_pending, s->intregm_disabled); |
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| 223 | 230 |
} |
| 224 | 231 |
|
| 225 | 232 |
void slavio_irq_info(void *opaque) |
| ... | ... | |
| 376 | 383 |
|
| 377 | 384 |
s->intbit_to_level = intbit_to_level; |
| 378 | 385 |
for (i = 0; i < MAX_CPUS; i++) {
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slavio_intctl_io_memory = cpu_register_io_memory(0, slavio_intctl_mem_read, slavio_intctl_mem_write, s); |
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slavio_intctl_io_memory = cpu_register_io_memory(0, |
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slavio_intctl_mem_read, |
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slavio_intctl_mem_write, |
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s); |
|
| 380 | 390 |
cpu_register_physical_memory(addr + i * TARGET_PAGE_SIZE, INTCTL_SIZE, |
| 381 | 391 |
slavio_intctl_io_memory); |
| 382 | 392 |
s->cpu_irqs[i] = parent_irq[i]; |
| 383 | 393 |
} |
| 384 | 394 |
|
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slavio_intctlm_io_memory = cpu_register_io_memory(0, slavio_intctlm_mem_read, slavio_intctlm_mem_write, s); |
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slavio_intctlm_io_memory = cpu_register_io_memory(0, |
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slavio_intctlm_mem_read, |
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slavio_intctlm_mem_write, |
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s); |
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| 386 | 399 |
cpu_register_physical_memory(addrg, INTCTLM_SIZE, slavio_intctlm_io_memory); |
| 387 | 400 |
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register_savevm("slavio_intctl", addr, 1, slavio_intctl_save, slavio_intctl_load, s);
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register_savevm("slavio_intctl", addr, 1, slavio_intctl_save,
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slavio_intctl_load, s); |
|
| 389 | 403 |
qemu_register_reset(slavio_intctl_reset, s); |
| 390 | 404 |
*irq = qemu_allocate_irqs(slavio_set_irq, s, 32); |
| 391 | 405 |
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