Revision 77f193da target-sparc/helper.c
| b/target-sparc/helper.c | ||
|---|---|---|
| 193 | 193 |
return (3 << 8) | (4 << 2); |
| 194 | 194 |
case 2: /* L3 PTE */ |
| 195 | 195 |
virt_addr = address & TARGET_PAGE_MASK; |
| 196 |
page_offset = (address & TARGET_PAGE_MASK) & (TARGET_PAGE_SIZE - 1); |
|
| 196 |
page_offset = (address & TARGET_PAGE_MASK) & |
|
| 197 |
(TARGET_PAGE_SIZE - 1); |
|
| 197 | 198 |
} |
| 198 | 199 |
break; |
| 199 | 200 |
case 2: /* L2 PTE */ |
| ... | ... | |
| 243 | 244 |
target_ulong vaddr; |
| 244 | 245 |
int error_code = 0, prot, ret = 0, access_index; |
| 245 | 246 |
|
| 246 |
error_code = get_physical_address(env, &paddr, &prot, &access_index, address, rw, mmu_idx); |
|
| 247 |
error_code = get_physical_address(env, &paddr, &prot, &access_index, |
|
| 248 |
address, rw, mmu_idx); |
|
| 247 | 249 |
if (error_code == 0) {
|
| 248 | 250 |
vaddr = address & TARGET_PAGE_MASK; |
| 249 | 251 |
paddr &= TARGET_PAGE_MASK; |
| ... | ... | |
| 387 | 389 |
/* |
| 388 | 390 |
* UltraSparc IIi I/DMMUs |
| 389 | 391 |
*/ |
| 390 |
static int get_physical_address_data(CPUState *env, target_phys_addr_t *physical, int *prot, |
|
| 392 |
static int get_physical_address_data(CPUState *env, |
|
| 393 |
target_phys_addr_t *physical, int *prot, |
|
| 391 | 394 |
target_ulong address, int rw, int is_user) |
| 392 | 395 |
{
|
| 393 | 396 |
target_ulong mask; |
| ... | ... | |
| 423 | 426 |
((env->dtlb_tte[i] & 0x4) && is_user) || |
| 424 | 427 |
(!(env->dtlb_tte[i] & 0x2) && (rw == 1))) {
|
| 425 | 428 |
if (env->dmmuregs[3]) /* Fault status register */ |
| 426 |
env->dmmuregs[3] = 2; /* overflow (not read before another fault) */ |
|
| 429 |
env->dmmuregs[3] = 2; /* overflow (not read before |
|
| 430 |
another fault) */ |
|
| 427 | 431 |
env->dmmuregs[3] |= (is_user << 3) | ((rw == 1) << 2) | 1; |
| 428 | 432 |
env->dmmuregs[4] = address; /* Fault address register */ |
| 429 | 433 |
env->exception_index = TT_DFAULT; |
| ... | ... | |
| 432 | 436 |
#endif |
| 433 | 437 |
return 1; |
| 434 | 438 |
} |
| 435 |
*physical = (env->dtlb_tte[i] & mask & 0x1fffffff000ULL) + (address & ~mask & 0x1fffffff000ULL); |
|
| 439 |
*physical = (env->dtlb_tte[i] & mask & 0x1fffffff000ULL) + |
|
| 440 |
(address & ~mask & 0x1fffffff000ULL); |
|
| 436 | 441 |
*prot = PAGE_READ; |
| 437 | 442 |
if (env->dtlb_tte[i] & 0x2) |
| 438 | 443 |
*prot |= PAGE_WRITE; |
| ... | ... | |
| 446 | 451 |
return 1; |
| 447 | 452 |
} |
| 448 | 453 |
|
| 449 |
static int get_physical_address_code(CPUState *env, target_phys_addr_t *physical, int *prot, |
|
| 454 |
static int get_physical_address_code(CPUState *env, |
|
| 455 |
target_phys_addr_t *physical, int *prot, |
|
| 450 | 456 |
target_ulong address, int is_user) |
| 451 | 457 |
{
|
| 452 | 458 |
target_ulong mask; |
| ... | ... | |
| 481 | 487 |
if ((env->itlb_tte[i] & 0x8000000000000000ULL) == 0 || |
| 482 | 488 |
((env->itlb_tte[i] & 0x4) && is_user)) {
|
| 483 | 489 |
if (env->immuregs[3]) /* Fault status register */ |
| 484 |
env->immuregs[3] = 2; /* overflow (not read before another fault) */ |
|
| 490 |
env->immuregs[3] = 2; /* overflow (not read before |
|
| 491 |
another fault) */ |
|
| 485 | 492 |
env->immuregs[3] |= (is_user << 3) | 1; |
| 486 | 493 |
env->exception_index = TT_TFAULT; |
| 487 | 494 |
#ifdef DEBUG_MMU |
| ... | ... | |
| 489 | 496 |
#endif |
| 490 | 497 |
return 1; |
| 491 | 498 |
} |
| 492 |
*physical = (env->itlb_tte[i] & mask & 0x1fffffff000ULL) + (address & ~mask & 0x1fffffff000ULL); |
|
| 499 |
*physical = (env->itlb_tte[i] & mask & 0x1fffffff000ULL) + |
|
| 500 |
(address & ~mask & 0x1fffffff000ULL); |
|
| 493 | 501 |
*prot = PAGE_EXEC; |
| 494 | 502 |
return 0; |
| 495 | 503 |
} |
| ... | ... | |
| 523 | 531 |
target_phys_addr_t paddr; |
| 524 | 532 |
int error_code = 0, prot, ret = 0, access_index; |
| 525 | 533 |
|
| 526 |
error_code = get_physical_address(env, &paddr, &prot, &access_index, address, rw, mmu_idx); |
|
| 534 |
error_code = get_physical_address(env, &paddr, &prot, &access_index, |
|
| 535 |
address, rw, mmu_idx); |
|
| 527 | 536 |
if (error_code == 0) {
|
| 528 | 537 |
virt_addr = address & TARGET_PAGE_MASK; |
| 529 |
vaddr = virt_addr + ((address & TARGET_PAGE_MASK) & (TARGET_PAGE_SIZE - 1)); |
|
| 538 |
vaddr = virt_addr + ((address & TARGET_PAGE_MASK) & |
|
| 539 |
(TARGET_PAGE_SIZE - 1)); |
|
| 530 | 540 |
#ifdef DEBUG_MMU |
| 531 |
printf("Translate at 0x%" PRIx64 " -> 0x%" PRIx64 ", vaddr 0x%" PRIx64 "\n", address, paddr, vaddr);
|
|
| 541 |
printf("Translate at 0x%" PRIx64 " -> 0x%" PRIx64 ", vaddr 0x%" PRIx64
|
|
| 542 |
"\n", address, paddr, vaddr); |
|
| 532 | 543 |
#endif |
| 533 | 544 |
ret = tlb_set_page_exec(env, vaddr, paddr, prot, mmu_idx, is_softmmu); |
| 534 | 545 |
return ret; |
| ... | ... | |
| 543 | 554 |
unsigned int i; |
| 544 | 555 |
const char *mask; |
| 545 | 556 |
|
| 546 |
printf("MMU contexts: Primary: %" PRId64 ", Secondary: %" PRId64 "\n", env->dmmuregs[1], env->dmmuregs[2]);
|
|
| 557 |
printf("MMU contexts: Primary: %" PRId64 ", Secondary: %" PRId64 "\n",
|
|
| 558 |
env->dmmuregs[1], env->dmmuregs[2]); |
|
| 547 | 559 |
if ((env->lsu & DMMU_E) == 0) {
|
| 548 | 560 |
printf("DMMU disabled\n");
|
| 549 | 561 |
} else {
|
| ... | ... | |
| 565 | 577 |
break; |
| 566 | 578 |
} |
| 567 | 579 |
if ((env->dtlb_tte[i] & 0x8000000000000000ULL) != 0) {
|
| 568 |
printf("VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_lx ", %s, %s, %s, %s, ctx %" PRId64 "\n",
|
|
| 580 |
printf("VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_lx
|
|
| 581 |
", %s, %s, %s, %s, ctx %" PRId64 "\n", |
|
| 569 | 582 |
env->dtlb_tag[i] & ~0x1fffULL, |
| 570 | 583 |
env->dtlb_tte[i] & 0x1ffffffe000ULL, |
| 571 | 584 |
mask, |
| ... | ... | |
| 597 | 610 |
break; |
| 598 | 611 |
} |
| 599 | 612 |
if ((env->itlb_tte[i] & 0x8000000000000000ULL) != 0) {
|
| 600 |
printf("VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_lx ", %s, %s, %s, ctx %" PRId64 "\n",
|
|
| 613 |
printf("VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_lx
|
|
| 614 |
", %s, %s, %s, ctx %" PRId64 "\n", |
|
| 601 | 615 |
env->itlb_tag[i] & ~0x1fffULL, |
| 602 | 616 |
env->itlb_tte[i] & 0x1ffffffe000ULL, |
| 603 | 617 |
mask, |
| ... | ... | |
| 1206 | 1220 |
goto error; |
| 1207 | 1221 |
} |
| 1208 | 1222 |
} else {
|
| 1209 |
fprintf(stderr, "feature string `%s' not in format (+feature|-feature|feature=xyz)\n", featurestr); |
|
| 1223 |
fprintf(stderr, "feature string `%s' not in format " |
|
| 1224 |
"(+feature|-feature|feature=xyz)\n", featurestr); |
|
| 1210 | 1225 |
goto error; |
| 1211 | 1226 |
} |
| 1212 | 1227 |
featurestr = strtok(NULL, ","); |
| ... | ... | |
| 1224 | 1239 |
return -1; |
| 1225 | 1240 |
} |
| 1226 | 1241 |
|
| 1227 |
void sparc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...))
|
|
| 1242 |
void sparc_cpu_list(FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...)) |
|
| 1228 | 1243 |
{
|
| 1229 | 1244 |
unsigned int i; |
| 1230 | 1245 |
|
| ... | ... | |
| 1234 | 1249 |
sparc_defs[i].iu_version, |
| 1235 | 1250 |
sparc_defs[i].fpu_version, |
| 1236 | 1251 |
sparc_defs[i].mmu_version); |
| 1237 |
print_features(f, cpu_fprintf, CPU_DEFAULT_FEATURES & ~sparc_defs[i].features, "-"); |
|
| 1238 |
print_features(f, cpu_fprintf, ~CPU_DEFAULT_FEATURES & sparc_defs[i].features, "+"); |
|
| 1252 |
print_features(f, cpu_fprintf, CPU_DEFAULT_FEATURES & |
|
| 1253 |
~sparc_defs[i].features, "-"); |
|
| 1254 |
print_features(f, cpu_fprintf, ~CPU_DEFAULT_FEATURES & |
|
| 1255 |
sparc_defs[i].features, "+"); |
|
| 1239 | 1256 |
(*cpu_fprintf)(f, "\n"); |
| 1240 | 1257 |
} |
| 1241 | 1258 |
(*cpu_fprintf)(f, "CPU feature flags (+/-): "); |
| 1242 | 1259 |
print_features(f, cpu_fprintf, -1, NULL); |
| 1243 | 1260 |
(*cpu_fprintf)(f, "\n"); |
| 1244 |
(*cpu_fprintf)(f, "Numerical features (=): iu_version fpu_version mmu_version\n"); |
|
| 1261 |
(*cpu_fprintf)(f, "Numerical features (=): iu_version fpu_version " |
|
| 1262 |
"mmu_version\n"); |
|
| 1245 | 1263 |
} |
| 1246 | 1264 |
|
| 1247 | 1265 |
#define GET_FLAG(a,b) ((env->psr & a)?b:'-') |
| ... | ... | |
| 1252 | 1270 |
{
|
| 1253 | 1271 |
int i, x; |
| 1254 | 1272 |
|
| 1255 |
cpu_fprintf(f, "pc: " TARGET_FMT_lx " npc: " TARGET_FMT_lx "\n", env->pc, env->npc); |
|
| 1273 |
cpu_fprintf(f, "pc: " TARGET_FMT_lx " npc: " TARGET_FMT_lx "\n", env->pc, |
|
| 1274 |
env->npc); |
|
| 1256 | 1275 |
cpu_fprintf(f, "General Registers:\n"); |
| 1257 | 1276 |
for (i = 0; i < 4; i++) |
| 1258 | 1277 |
cpu_fprintf(f, "%%g%c: " TARGET_FMT_lx "\t", i + '0', env->gregs[i]); |
| ... | ... | |
| 1283 | 1302 |
#ifdef TARGET_SPARC64 |
| 1284 | 1303 |
cpu_fprintf(f, "pstate: 0x%08x ccr: 0x%02x asi: 0x%02x tl: %d fprs: %d\n", |
| 1285 | 1304 |
env->pstate, GET_CCR(env), env->asi, env->tl, env->fprs); |
| 1286 |
cpu_fprintf(f, "cansave: %d canrestore: %d otherwin: %d wstate %d cleanwin %d cwp %d\n", |
|
| 1305 |
cpu_fprintf(f, "cansave: %d canrestore: %d otherwin: %d wstate %d " |
|
| 1306 |
"cleanwin %d cwp %d\n", |
|
| 1287 | 1307 |
env->cansave, env->canrestore, env->otherwin, env->wstate, |
| 1288 | 1308 |
env->cleanwin, NWINDOWS - 1 - env->cwp); |
| 1289 | 1309 |
#else |
| 1290 |
cpu_fprintf(f, "psr: 0x%08x -> %c%c%c%c %c%c%c wim: 0x%08x\n", GET_PSR(env),
|
|
| 1291 |
GET_FLAG(PSR_ZERO, 'Z'), GET_FLAG(PSR_OVF, 'V'), |
|
| 1292 |
GET_FLAG(PSR_NEG, 'N'), GET_FLAG(PSR_CARRY, 'C'), |
|
| 1293 |
env->psrs?'S':'-', env->psrps?'P':'-', |
|
| 1294 |
env->psret?'E':'-', env->wim); |
|
| 1310 |
cpu_fprintf(f, "psr: 0x%08x -> %c%c%c%c %c%c%c wim: 0x%08x\n", |
|
| 1311 |
GET_PSR(env), GET_FLAG(PSR_ZERO, 'Z'), GET_FLAG(PSR_OVF, 'V'),
|
|
| 1312 |
GET_FLAG(PSR_NEG, 'N'), GET_FLAG(PSR_CARRY, 'C'),
|
|
| 1313 |
env->psrs?'S':'-', env->psrps?'P':'-',
|
|
| 1314 |
env->psret?'E':'-', env->wim);
|
|
| 1295 | 1315 |
#endif |
| 1296 | 1316 |
cpu_fprintf(f, "fsr: 0x%08x\n", GET_FSR32(env)); |
| 1297 | 1317 |
} |
Also available in: Unified diff