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1 | a541f297 | bellard | /*
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2 | 819385c5 | bellard | * QEMU M48T59 and M48T08 NVRAM emulation for PPC PREP and Sparc platforms
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3 | 5fafdf24 | ths | *
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4 | 3ccacc4a | blueswir1 | * Copyright (c) 2003-2005, 2007 Jocelyn Mayer
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5 | 5fafdf24 | ths | *
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6 | a541f297 | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | a541f297 | bellard | * of this software and associated documentation files (the "Software"), to deal
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8 | a541f297 | bellard | * in the Software without restriction, including without limitation the rights
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9 | a541f297 | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | a541f297 | bellard | * copies of the Software, and to permit persons to whom the Software is
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11 | a541f297 | bellard | * furnished to do so, subject to the following conditions:
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12 | a541f297 | bellard | *
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13 | a541f297 | bellard | * The above copyright notice and this permission notice shall be included in
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14 | a541f297 | bellard | * all copies or substantial portions of the Software.
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15 | a541f297 | bellard | *
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16 | a541f297 | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | a541f297 | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | a541f297 | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | a541f297 | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | a541f297 | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | a541f297 | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | a541f297 | bellard | * THE SOFTWARE.
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23 | a541f297 | bellard | */
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24 | 87ecb68b | pbrook | #include "hw.h" |
25 | 87ecb68b | pbrook | #include "nvram.h" |
26 | 1de7afc9 | Paolo Bonzini | #include "qemu/timer.h" |
27 | 9c17d615 | Paolo Bonzini | #include "sysemu/sysemu.h" |
28 | d27cf0ae | Blue Swirl | #include "sysbus.h" |
29 | f80237d4 | Blue Swirl | #include "isa.h" |
30 | 022c62cb | Paolo Bonzini | #include "exec/address-spaces.h" |
31 | a541f297 | bellard | |
32 | 13ab5daa | bellard | //#define DEBUG_NVRAM
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33 | a541f297 | bellard | |
34 | 13ab5daa | bellard | #if defined(DEBUG_NVRAM)
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35 | 001faf32 | Blue Swirl | #define NVRAM_PRINTF(fmt, ...) do { printf(fmt , ## __VA_ARGS__); } while (0) |
36 | a541f297 | bellard | #else
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37 | 001faf32 | Blue Swirl | #define NVRAM_PRINTF(fmt, ...) do { } while (0) |
38 | a541f297 | bellard | #endif
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39 | a541f297 | bellard | |
40 | 819385c5 | bellard | /*
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41 | 4aed2c33 | blueswir1 | * The M48T02, M48T08 and M48T59 chips are very similar. The newer '59 has
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42 | 819385c5 | bellard | * alarm and a watchdog timer and related control registers. In the
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43 | 819385c5 | bellard | * PPC platform there is also a nvram lock function.
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44 | 819385c5 | bellard | */
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45 | 930f3fe1 | Blue Swirl | |
46 | 930f3fe1 | Blue Swirl | /*
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47 | 930f3fe1 | Blue Swirl | * Chipset docs:
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48 | 930f3fe1 | Blue Swirl | * http://www.st.com/stonline/products/literature/ds/2410/m48t02.pdf
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49 | 930f3fe1 | Blue Swirl | * http://www.st.com/stonline/products/literature/ds/2411/m48t08.pdf
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50 | 930f3fe1 | Blue Swirl | * http://www.st.com/stonline/products/literature/od/7001/m48t59y.pdf
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51 | 930f3fe1 | Blue Swirl | */
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52 | 930f3fe1 | Blue Swirl | |
53 | 43a34704 | Blue Swirl | struct M48t59State {
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54 | a541f297 | bellard | /* Hardware parameters */
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55 | d537cf6c | pbrook | qemu_irq IRQ; |
56 | 5a31cd68 | Avi Kivity | MemoryRegion iomem; |
57 | a541f297 | bellard | uint32_t io_base; |
58 | ee6847d1 | Gerd Hoffmann | uint32_t size; |
59 | a541f297 | bellard | /* RTC management */
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60 | a541f297 | bellard | time_t time_offset; |
61 | a541f297 | bellard | time_t stop_time; |
62 | a541f297 | bellard | /* Alarm & watchdog */
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63 | f6503059 | balrog | struct tm alarm;
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64 | a541f297 | bellard | struct QEMUTimer *alrm_timer;
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65 | a541f297 | bellard | struct QEMUTimer *wd_timer;
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66 | a541f297 | bellard | /* NVRAM storage */
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67 | a541f297 | bellard | uint8_t *buffer; |
68 | 42c812b9 | Blue Swirl | /* Model parameters */
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69 | 7bc3018b | Paolo Bonzini | uint32_t model; /* 2 = m48t02, 8 = m48t08, 59 = m48t59 */
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70 | 42c812b9 | Blue Swirl | /* NVRAM storage */
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71 | 42c812b9 | Blue Swirl | uint16_t addr; |
72 | 42c812b9 | Blue Swirl | uint8_t lock; |
73 | c5df018e | bellard | }; |
74 | a541f297 | bellard | |
75 | f80237d4 | Blue Swirl | typedef struct M48t59ISAState { |
76 | f80237d4 | Blue Swirl | ISADevice busdev; |
77 | 43a34704 | Blue Swirl | M48t59State state; |
78 | 9936d6e4 | Richard Henderson | MemoryRegion io; |
79 | f80237d4 | Blue Swirl | } M48t59ISAState; |
80 | f80237d4 | Blue Swirl | |
81 | f80237d4 | Blue Swirl | typedef struct M48t59SysBusState { |
82 | f80237d4 | Blue Swirl | SysBusDevice busdev; |
83 | 43a34704 | Blue Swirl | M48t59State state; |
84 | 087bd055 | Alexander Graf | MemoryRegion io; |
85 | f80237d4 | Blue Swirl | } M48t59SysBusState; |
86 | f80237d4 | Blue Swirl | |
87 | a541f297 | bellard | /* Fake timer functions */
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88 | a541f297 | bellard | |
89 | a541f297 | bellard | /* Alarm management */
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90 | a541f297 | bellard | static void alarm_cb (void *opaque) |
91 | a541f297 | bellard | { |
92 | f6503059 | balrog | struct tm tm;
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93 | a541f297 | bellard | uint64_t next_time; |
94 | 43a34704 | Blue Swirl | M48t59State *NVRAM = opaque; |
95 | a541f297 | bellard | |
96 | d537cf6c | pbrook | qemu_set_irq(NVRAM->IRQ, 1);
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97 | 5fafdf24 | ths | if ((NVRAM->buffer[0x1FF5] & 0x80) == 0 && |
98 | a541f297 | bellard | (NVRAM->buffer[0x1FF4] & 0x80) == 0 && |
99 | a541f297 | bellard | (NVRAM->buffer[0x1FF3] & 0x80) == 0 && |
100 | a541f297 | bellard | (NVRAM->buffer[0x1FF2] & 0x80) == 0) { |
101 | f6503059 | balrog | /* Repeat once a month */
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102 | f6503059 | balrog | qemu_get_timedate(&tm, NVRAM->time_offset); |
103 | f6503059 | balrog | tm.tm_mon++; |
104 | f6503059 | balrog | if (tm.tm_mon == 13) { |
105 | f6503059 | balrog | tm.tm_mon = 1;
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106 | f6503059 | balrog | tm.tm_year++; |
107 | f6503059 | balrog | } |
108 | f6503059 | balrog | next_time = qemu_timedate_diff(&tm) - NVRAM->time_offset; |
109 | a541f297 | bellard | } else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 && |
110 | a541f297 | bellard | (NVRAM->buffer[0x1FF4] & 0x80) == 0 && |
111 | a541f297 | bellard | (NVRAM->buffer[0x1FF3] & 0x80) == 0 && |
112 | a541f297 | bellard | (NVRAM->buffer[0x1FF2] & 0x80) == 0) { |
113 | f6503059 | balrog | /* Repeat once a day */
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114 | f6503059 | balrog | next_time = 24 * 60 * 60; |
115 | a541f297 | bellard | } else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 && |
116 | a541f297 | bellard | (NVRAM->buffer[0x1FF4] & 0x80) != 0 && |
117 | a541f297 | bellard | (NVRAM->buffer[0x1FF3] & 0x80) == 0 && |
118 | a541f297 | bellard | (NVRAM->buffer[0x1FF2] & 0x80) == 0) { |
119 | f6503059 | balrog | /* Repeat once an hour */
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120 | f6503059 | balrog | next_time = 60 * 60; |
121 | a541f297 | bellard | } else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 && |
122 | a541f297 | bellard | (NVRAM->buffer[0x1FF4] & 0x80) != 0 && |
123 | a541f297 | bellard | (NVRAM->buffer[0x1FF3] & 0x80) != 0 && |
124 | a541f297 | bellard | (NVRAM->buffer[0x1FF2] & 0x80) == 0) { |
125 | f6503059 | balrog | /* Repeat once a minute */
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126 | f6503059 | balrog | next_time = 60;
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127 | a541f297 | bellard | } else {
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128 | f6503059 | balrog | /* Repeat once a second */
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129 | f6503059 | balrog | next_time = 1;
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130 | a541f297 | bellard | } |
131 | 1d849502 | Paolo Bonzini | qemu_mod_timer(NVRAM->alrm_timer, qemu_get_clock_ns(rtc_clock) + |
132 | f6503059 | balrog | next_time * 1000);
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133 | d537cf6c | pbrook | qemu_set_irq(NVRAM->IRQ, 0);
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134 | a541f297 | bellard | } |
135 | a541f297 | bellard | |
136 | 43a34704 | Blue Swirl | static void set_alarm(M48t59State *NVRAM) |
137 | f6503059 | balrog | { |
138 | f6503059 | balrog | int diff;
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139 | f6503059 | balrog | if (NVRAM->alrm_timer != NULL) { |
140 | f6503059 | balrog | qemu_del_timer(NVRAM->alrm_timer); |
141 | f6503059 | balrog | diff = qemu_timedate_diff(&NVRAM->alarm) - NVRAM->time_offset; |
142 | f6503059 | balrog | if (diff > 0) |
143 | f6503059 | balrog | qemu_mod_timer(NVRAM->alrm_timer, diff * 1000);
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144 | f6503059 | balrog | } |
145 | f6503059 | balrog | } |
146 | a541f297 | bellard | |
147 | f6503059 | balrog | /* RTC management helpers */
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148 | 43a34704 | Blue Swirl | static inline void get_time(M48t59State *NVRAM, struct tm *tm) |
149 | a541f297 | bellard | { |
150 | f6503059 | balrog | qemu_get_timedate(tm, NVRAM->time_offset); |
151 | a541f297 | bellard | } |
152 | a541f297 | bellard | |
153 | 43a34704 | Blue Swirl | static void set_time(M48t59State *NVRAM, struct tm *tm) |
154 | a541f297 | bellard | { |
155 | f6503059 | balrog | NVRAM->time_offset = qemu_timedate_diff(tm); |
156 | f6503059 | balrog | set_alarm(NVRAM); |
157 | a541f297 | bellard | } |
158 | a541f297 | bellard | |
159 | a541f297 | bellard | /* Watchdog management */
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160 | a541f297 | bellard | static void watchdog_cb (void *opaque) |
161 | a541f297 | bellard | { |
162 | 43a34704 | Blue Swirl | M48t59State *NVRAM = opaque; |
163 | a541f297 | bellard | |
164 | a541f297 | bellard | NVRAM->buffer[0x1FF0] |= 0x80; |
165 | a541f297 | bellard | if (NVRAM->buffer[0x1FF7] & 0x80) { |
166 | a541f297 | bellard | NVRAM->buffer[0x1FF7] = 0x00; |
167 | a541f297 | bellard | NVRAM->buffer[0x1FFC] &= ~0x40; |
168 | 13ab5daa | bellard | /* May it be a hw CPU Reset instead ? */
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169 | d7d02e3c | bellard | qemu_system_reset_request(); |
170 | a541f297 | bellard | } else {
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171 | d537cf6c | pbrook | qemu_set_irq(NVRAM->IRQ, 1);
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172 | d537cf6c | pbrook | qemu_set_irq(NVRAM->IRQ, 0);
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173 | a541f297 | bellard | } |
174 | a541f297 | bellard | } |
175 | a541f297 | bellard | |
176 | 43a34704 | Blue Swirl | static void set_up_watchdog(M48t59State *NVRAM, uint8_t value) |
177 | a541f297 | bellard | { |
178 | a541f297 | bellard | uint64_t interval; /* in 1/16 seconds */
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179 | a541f297 | bellard | |
180 | 868d585a | j_mayer | NVRAM->buffer[0x1FF0] &= ~0x80; |
181 | a541f297 | bellard | if (NVRAM->wd_timer != NULL) { |
182 | a541f297 | bellard | qemu_del_timer(NVRAM->wd_timer); |
183 | 868d585a | j_mayer | if (value != 0) { |
184 | 868d585a | j_mayer | interval = (1 << (2 * (value & 0x03))) * ((value >> 2) & 0x1F); |
185 | 868d585a | j_mayer | qemu_mod_timer(NVRAM->wd_timer, ((uint64_t)time(NULL) * 1000) + |
186 | 868d585a | j_mayer | ((interval * 1000) >> 4)); |
187 | 868d585a | j_mayer | } |
188 | a541f297 | bellard | } |
189 | a541f297 | bellard | } |
190 | a541f297 | bellard | |
191 | a541f297 | bellard | /* Direct access to NVRAM */
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192 | 897b4c6c | j_mayer | void m48t59_write (void *opaque, uint32_t addr, uint32_t val) |
193 | a541f297 | bellard | { |
194 | 43a34704 | Blue Swirl | M48t59State *NVRAM = opaque; |
195 | a541f297 | bellard | struct tm tm;
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196 | a541f297 | bellard | int tmp;
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197 | a541f297 | bellard | |
198 | 819385c5 | bellard | if (addr > 0x1FF8 && addr < 0x2000) |
199 | 819385c5 | bellard | NVRAM_PRINTF("%s: 0x%08x => 0x%08x\n", __func__, addr, val);
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200 | 4aed2c33 | blueswir1 | |
201 | 4aed2c33 | blueswir1 | /* check for NVRAM access */
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202 | 7bc3018b | Paolo Bonzini | if ((NVRAM->model == 2 && addr < 0x7f8) || |
203 | 7bc3018b | Paolo Bonzini | (NVRAM->model == 8 && addr < 0x1ff8) || |
204 | 7bc3018b | Paolo Bonzini | (NVRAM->model == 59 && addr < 0x1ff0)) { |
205 | 819385c5 | bellard | goto do_write;
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206 | 7bc3018b | Paolo Bonzini | } |
207 | 4aed2c33 | blueswir1 | |
208 | 4aed2c33 | blueswir1 | /* TOD access */
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209 | 819385c5 | bellard | switch (addr) {
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210 | a541f297 | bellard | case 0x1FF0: |
211 | a541f297 | bellard | /* flags register : read-only */
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212 | a541f297 | bellard | break;
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213 | a541f297 | bellard | case 0x1FF1: |
214 | a541f297 | bellard | /* unused */
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215 | a541f297 | bellard | break;
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216 | a541f297 | bellard | case 0x1FF2: |
217 | a541f297 | bellard | /* alarm seconds */
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218 | abd0c6bd | Paul Brook | tmp = from_bcd(val & 0x7F);
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219 | 819385c5 | bellard | if (tmp >= 0 && tmp <= 59) { |
220 | f6503059 | balrog | NVRAM->alarm.tm_sec = tmp; |
221 | 819385c5 | bellard | NVRAM->buffer[0x1FF2] = val;
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222 | f6503059 | balrog | set_alarm(NVRAM); |
223 | 819385c5 | bellard | } |
224 | a541f297 | bellard | break;
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225 | a541f297 | bellard | case 0x1FF3: |
226 | a541f297 | bellard | /* alarm minutes */
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227 | abd0c6bd | Paul Brook | tmp = from_bcd(val & 0x7F);
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228 | 819385c5 | bellard | if (tmp >= 0 && tmp <= 59) { |
229 | f6503059 | balrog | NVRAM->alarm.tm_min = tmp; |
230 | 819385c5 | bellard | NVRAM->buffer[0x1FF3] = val;
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231 | f6503059 | balrog | set_alarm(NVRAM); |
232 | 819385c5 | bellard | } |
233 | a541f297 | bellard | break;
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234 | a541f297 | bellard | case 0x1FF4: |
235 | a541f297 | bellard | /* alarm hours */
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236 | abd0c6bd | Paul Brook | tmp = from_bcd(val & 0x3F);
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237 | 819385c5 | bellard | if (tmp >= 0 && tmp <= 23) { |
238 | f6503059 | balrog | NVRAM->alarm.tm_hour = tmp; |
239 | 819385c5 | bellard | NVRAM->buffer[0x1FF4] = val;
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240 | f6503059 | balrog | set_alarm(NVRAM); |
241 | 819385c5 | bellard | } |
242 | a541f297 | bellard | break;
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243 | a541f297 | bellard | case 0x1FF5: |
244 | a541f297 | bellard | /* alarm date */
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245 | 02f5da11 | Artyom Tarasenko | tmp = from_bcd(val & 0x3F);
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246 | 819385c5 | bellard | if (tmp != 0) { |
247 | f6503059 | balrog | NVRAM->alarm.tm_mday = tmp; |
248 | 819385c5 | bellard | NVRAM->buffer[0x1FF5] = val;
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249 | f6503059 | balrog | set_alarm(NVRAM); |
250 | 819385c5 | bellard | } |
251 | a541f297 | bellard | break;
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252 | a541f297 | bellard | case 0x1FF6: |
253 | a541f297 | bellard | /* interrupts */
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254 | 819385c5 | bellard | NVRAM->buffer[0x1FF6] = val;
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255 | a541f297 | bellard | break;
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256 | a541f297 | bellard | case 0x1FF7: |
257 | a541f297 | bellard | /* watchdog */
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258 | 819385c5 | bellard | NVRAM->buffer[0x1FF7] = val;
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259 | 819385c5 | bellard | set_up_watchdog(NVRAM, val); |
260 | a541f297 | bellard | break;
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261 | a541f297 | bellard | case 0x1FF8: |
262 | 4aed2c33 | blueswir1 | case 0x07F8: |
263 | a541f297 | bellard | /* control */
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264 | 4aed2c33 | blueswir1 | NVRAM->buffer[addr] = (val & ~0xA0) | 0x90; |
265 | a541f297 | bellard | break;
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266 | a541f297 | bellard | case 0x1FF9: |
267 | 4aed2c33 | blueswir1 | case 0x07F9: |
268 | a541f297 | bellard | /* seconds (BCD) */
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269 | abd0c6bd | Paul Brook | tmp = from_bcd(val & 0x7F);
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270 | a541f297 | bellard | if (tmp >= 0 && tmp <= 59) { |
271 | a541f297 | bellard | get_time(NVRAM, &tm); |
272 | a541f297 | bellard | tm.tm_sec = tmp; |
273 | a541f297 | bellard | set_time(NVRAM, &tm); |
274 | a541f297 | bellard | } |
275 | f6503059 | balrog | if ((val & 0x80) ^ (NVRAM->buffer[addr] & 0x80)) { |
276 | a541f297 | bellard | if (val & 0x80) { |
277 | a541f297 | bellard | NVRAM->stop_time = time(NULL);
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278 | a541f297 | bellard | } else {
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279 | a541f297 | bellard | NVRAM->time_offset += NVRAM->stop_time - time(NULL);
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280 | a541f297 | bellard | NVRAM->stop_time = 0;
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281 | a541f297 | bellard | } |
282 | a541f297 | bellard | } |
283 | f6503059 | balrog | NVRAM->buffer[addr] = val & 0x80;
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284 | a541f297 | bellard | break;
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285 | a541f297 | bellard | case 0x1FFA: |
286 | 4aed2c33 | blueswir1 | case 0x07FA: |
287 | a541f297 | bellard | /* minutes (BCD) */
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288 | abd0c6bd | Paul Brook | tmp = from_bcd(val & 0x7F);
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289 | a541f297 | bellard | if (tmp >= 0 && tmp <= 59) { |
290 | a541f297 | bellard | get_time(NVRAM, &tm); |
291 | a541f297 | bellard | tm.tm_min = tmp; |
292 | a541f297 | bellard | set_time(NVRAM, &tm); |
293 | a541f297 | bellard | } |
294 | a541f297 | bellard | break;
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295 | a541f297 | bellard | case 0x1FFB: |
296 | 4aed2c33 | blueswir1 | case 0x07FB: |
297 | a541f297 | bellard | /* hours (BCD) */
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298 | abd0c6bd | Paul Brook | tmp = from_bcd(val & 0x3F);
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299 | a541f297 | bellard | if (tmp >= 0 && tmp <= 23) { |
300 | a541f297 | bellard | get_time(NVRAM, &tm); |
301 | a541f297 | bellard | tm.tm_hour = tmp; |
302 | a541f297 | bellard | set_time(NVRAM, &tm); |
303 | a541f297 | bellard | } |
304 | a541f297 | bellard | break;
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305 | a541f297 | bellard | case 0x1FFC: |
306 | 4aed2c33 | blueswir1 | case 0x07FC: |
307 | a541f297 | bellard | /* day of the week / century */
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308 | abd0c6bd | Paul Brook | tmp = from_bcd(val & 0x07);
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309 | a541f297 | bellard | get_time(NVRAM, &tm); |
310 | a541f297 | bellard | tm.tm_wday = tmp; |
311 | a541f297 | bellard | set_time(NVRAM, &tm); |
312 | 4aed2c33 | blueswir1 | NVRAM->buffer[addr] = val & 0x40;
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313 | a541f297 | bellard | break;
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314 | a541f297 | bellard | case 0x1FFD: |
315 | 4aed2c33 | blueswir1 | case 0x07FD: |
316 | 02f5da11 | Artyom Tarasenko | /* date (BCD) */
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317 | 02f5da11 | Artyom Tarasenko | tmp = from_bcd(val & 0x3F);
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318 | a541f297 | bellard | if (tmp != 0) { |
319 | a541f297 | bellard | get_time(NVRAM, &tm); |
320 | a541f297 | bellard | tm.tm_mday = tmp; |
321 | a541f297 | bellard | set_time(NVRAM, &tm); |
322 | a541f297 | bellard | } |
323 | a541f297 | bellard | break;
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324 | a541f297 | bellard | case 0x1FFE: |
325 | 4aed2c33 | blueswir1 | case 0x07FE: |
326 | a541f297 | bellard | /* month */
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327 | abd0c6bd | Paul Brook | tmp = from_bcd(val & 0x1F);
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328 | a541f297 | bellard | if (tmp >= 1 && tmp <= 12) { |
329 | a541f297 | bellard | get_time(NVRAM, &tm); |
330 | a541f297 | bellard | tm.tm_mon = tmp - 1;
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331 | a541f297 | bellard | set_time(NVRAM, &tm); |
332 | a541f297 | bellard | } |
333 | a541f297 | bellard | break;
|
334 | a541f297 | bellard | case 0x1FFF: |
335 | 4aed2c33 | blueswir1 | case 0x07FF: |
336 | a541f297 | bellard | /* year */
|
337 | abd0c6bd | Paul Brook | tmp = from_bcd(val); |
338 | a541f297 | bellard | if (tmp >= 0 && tmp <= 99) { |
339 | a541f297 | bellard | get_time(NVRAM, &tm); |
340 | 7bc3018b | Paolo Bonzini | if (NVRAM->model == 8) { |
341 | abd0c6bd | Paul Brook | tm.tm_year = from_bcd(val) + 68; // Base year is 1968 |
342 | 7bc3018b | Paolo Bonzini | } else {
|
343 | abd0c6bd | Paul Brook | tm.tm_year = from_bcd(val); |
344 | 7bc3018b | Paolo Bonzini | } |
345 | a541f297 | bellard | set_time(NVRAM, &tm); |
346 | a541f297 | bellard | } |
347 | a541f297 | bellard | break;
|
348 | a541f297 | bellard | default:
|
349 | 13ab5daa | bellard | /* Check lock registers state */
|
350 | 819385c5 | bellard | if (addr >= 0x20 && addr <= 0x2F && (NVRAM->lock & 1)) |
351 | 13ab5daa | bellard | break;
|
352 | 819385c5 | bellard | if (addr >= 0x30 && addr <= 0x3F && (NVRAM->lock & 2)) |
353 | 13ab5daa | bellard | break;
|
354 | 819385c5 | bellard | do_write:
|
355 | 819385c5 | bellard | if (addr < NVRAM->size) {
|
356 | 819385c5 | bellard | NVRAM->buffer[addr] = val & 0xFF;
|
357 | a541f297 | bellard | } |
358 | a541f297 | bellard | break;
|
359 | a541f297 | bellard | } |
360 | a541f297 | bellard | } |
361 | a541f297 | bellard | |
362 | 897b4c6c | j_mayer | uint32_t m48t59_read (void *opaque, uint32_t addr)
|
363 | a541f297 | bellard | { |
364 | 43a34704 | Blue Swirl | M48t59State *NVRAM = opaque; |
365 | a541f297 | bellard | struct tm tm;
|
366 | a541f297 | bellard | uint32_t retval = 0xFF;
|
367 | a541f297 | bellard | |
368 | 4aed2c33 | blueswir1 | /* check for NVRAM access */
|
369 | 7bc3018b | Paolo Bonzini | if ((NVRAM->model == 2 && addr < 0x078f) || |
370 | 7bc3018b | Paolo Bonzini | (NVRAM->model == 8 && addr < 0x1ff8) || |
371 | 7bc3018b | Paolo Bonzini | (NVRAM->model == 59 && addr < 0x1ff0)) { |
372 | 819385c5 | bellard | goto do_read;
|
373 | 7bc3018b | Paolo Bonzini | } |
374 | 4aed2c33 | blueswir1 | |
375 | 4aed2c33 | blueswir1 | /* TOD access */
|
376 | 819385c5 | bellard | switch (addr) {
|
377 | a541f297 | bellard | case 0x1FF0: |
378 | a541f297 | bellard | /* flags register */
|
379 | a541f297 | bellard | goto do_read;
|
380 | a541f297 | bellard | case 0x1FF1: |
381 | a541f297 | bellard | /* unused */
|
382 | a541f297 | bellard | retval = 0;
|
383 | a541f297 | bellard | break;
|
384 | a541f297 | bellard | case 0x1FF2: |
385 | a541f297 | bellard | /* alarm seconds */
|
386 | a541f297 | bellard | goto do_read;
|
387 | a541f297 | bellard | case 0x1FF3: |
388 | a541f297 | bellard | /* alarm minutes */
|
389 | a541f297 | bellard | goto do_read;
|
390 | a541f297 | bellard | case 0x1FF4: |
391 | a541f297 | bellard | /* alarm hours */
|
392 | a541f297 | bellard | goto do_read;
|
393 | a541f297 | bellard | case 0x1FF5: |
394 | a541f297 | bellard | /* alarm date */
|
395 | a541f297 | bellard | goto do_read;
|
396 | a541f297 | bellard | case 0x1FF6: |
397 | a541f297 | bellard | /* interrupts */
|
398 | a541f297 | bellard | goto do_read;
|
399 | a541f297 | bellard | case 0x1FF7: |
400 | a541f297 | bellard | /* A read resets the watchdog */
|
401 | a541f297 | bellard | set_up_watchdog(NVRAM, NVRAM->buffer[0x1FF7]);
|
402 | a541f297 | bellard | goto do_read;
|
403 | a541f297 | bellard | case 0x1FF8: |
404 | 4aed2c33 | blueswir1 | case 0x07F8: |
405 | a541f297 | bellard | /* control */
|
406 | a541f297 | bellard | goto do_read;
|
407 | a541f297 | bellard | case 0x1FF9: |
408 | 4aed2c33 | blueswir1 | case 0x07F9: |
409 | a541f297 | bellard | /* seconds (BCD) */
|
410 | a541f297 | bellard | get_time(NVRAM, &tm); |
411 | abd0c6bd | Paul Brook | retval = (NVRAM->buffer[addr] & 0x80) | to_bcd(tm.tm_sec);
|
412 | a541f297 | bellard | break;
|
413 | a541f297 | bellard | case 0x1FFA: |
414 | 4aed2c33 | blueswir1 | case 0x07FA: |
415 | a541f297 | bellard | /* minutes (BCD) */
|
416 | a541f297 | bellard | get_time(NVRAM, &tm); |
417 | abd0c6bd | Paul Brook | retval = to_bcd(tm.tm_min); |
418 | a541f297 | bellard | break;
|
419 | a541f297 | bellard | case 0x1FFB: |
420 | 4aed2c33 | blueswir1 | case 0x07FB: |
421 | a541f297 | bellard | /* hours (BCD) */
|
422 | a541f297 | bellard | get_time(NVRAM, &tm); |
423 | abd0c6bd | Paul Brook | retval = to_bcd(tm.tm_hour); |
424 | a541f297 | bellard | break;
|
425 | a541f297 | bellard | case 0x1FFC: |
426 | 4aed2c33 | blueswir1 | case 0x07FC: |
427 | a541f297 | bellard | /* day of the week / century */
|
428 | a541f297 | bellard | get_time(NVRAM, &tm); |
429 | 4aed2c33 | blueswir1 | retval = NVRAM->buffer[addr] | tm.tm_wday; |
430 | a541f297 | bellard | break;
|
431 | a541f297 | bellard | case 0x1FFD: |
432 | 4aed2c33 | blueswir1 | case 0x07FD: |
433 | a541f297 | bellard | /* date */
|
434 | a541f297 | bellard | get_time(NVRAM, &tm); |
435 | abd0c6bd | Paul Brook | retval = to_bcd(tm.tm_mday); |
436 | a541f297 | bellard | break;
|
437 | a541f297 | bellard | case 0x1FFE: |
438 | 4aed2c33 | blueswir1 | case 0x07FE: |
439 | a541f297 | bellard | /* month */
|
440 | a541f297 | bellard | get_time(NVRAM, &tm); |
441 | abd0c6bd | Paul Brook | retval = to_bcd(tm.tm_mon + 1);
|
442 | a541f297 | bellard | break;
|
443 | a541f297 | bellard | case 0x1FFF: |
444 | 4aed2c33 | blueswir1 | case 0x07FF: |
445 | a541f297 | bellard | /* year */
|
446 | a541f297 | bellard | get_time(NVRAM, &tm); |
447 | 7bc3018b | Paolo Bonzini | if (NVRAM->model == 8) { |
448 | abd0c6bd | Paul Brook | retval = to_bcd(tm.tm_year - 68); // Base year is 1968 |
449 | 7bc3018b | Paolo Bonzini | } else {
|
450 | abd0c6bd | Paul Brook | retval = to_bcd(tm.tm_year); |
451 | 7bc3018b | Paolo Bonzini | } |
452 | a541f297 | bellard | break;
|
453 | a541f297 | bellard | default:
|
454 | 13ab5daa | bellard | /* Check lock registers state */
|
455 | 819385c5 | bellard | if (addr >= 0x20 && addr <= 0x2F && (NVRAM->lock & 1)) |
456 | 13ab5daa | bellard | break;
|
457 | 819385c5 | bellard | if (addr >= 0x30 && addr <= 0x3F && (NVRAM->lock & 2)) |
458 | 13ab5daa | bellard | break;
|
459 | 819385c5 | bellard | do_read:
|
460 | 819385c5 | bellard | if (addr < NVRAM->size) {
|
461 | 819385c5 | bellard | retval = NVRAM->buffer[addr]; |
462 | a541f297 | bellard | } |
463 | a541f297 | bellard | break;
|
464 | a541f297 | bellard | } |
465 | 819385c5 | bellard | if (addr > 0x1FF9 && addr < 0x2000) |
466 | 9ed1e667 | blueswir1 | NVRAM_PRINTF("%s: 0x%08x <= 0x%08x\n", __func__, addr, retval);
|
467 | a541f297 | bellard | |
468 | a541f297 | bellard | return retval;
|
469 | a541f297 | bellard | } |
470 | a541f297 | bellard | |
471 | 897b4c6c | j_mayer | void m48t59_toggle_lock (void *opaque, int lock) |
472 | 13ab5daa | bellard | { |
473 | 43a34704 | Blue Swirl | M48t59State *NVRAM = opaque; |
474 | 897b4c6c | j_mayer | |
475 | 13ab5daa | bellard | NVRAM->lock ^= 1 << lock;
|
476 | 13ab5daa | bellard | } |
477 | 13ab5daa | bellard | |
478 | a541f297 | bellard | /* IO access to NVRAM */
|
479 | 087bd055 | Alexander Graf | static void NVRAM_writeb(void *opaque, hwaddr addr, uint64_t val, |
480 | 087bd055 | Alexander Graf | unsigned size)
|
481 | a541f297 | bellard | { |
482 | 43a34704 | Blue Swirl | M48t59State *NVRAM = opaque; |
483 | a541f297 | bellard | |
484 | 9ed1e667 | blueswir1 | NVRAM_PRINTF("%s: 0x%08x => 0x%08x\n", __func__, addr, val);
|
485 | a541f297 | bellard | switch (addr) {
|
486 | a541f297 | bellard | case 0: |
487 | a541f297 | bellard | NVRAM->addr &= ~0x00FF;
|
488 | a541f297 | bellard | NVRAM->addr |= val; |
489 | a541f297 | bellard | break;
|
490 | a541f297 | bellard | case 1: |
491 | a541f297 | bellard | NVRAM->addr &= ~0xFF00;
|
492 | a541f297 | bellard | NVRAM->addr |= val << 8;
|
493 | a541f297 | bellard | break;
|
494 | a541f297 | bellard | case 3: |
495 | b1f88301 | Blue Swirl | m48t59_write(NVRAM, NVRAM->addr, val); |
496 | a541f297 | bellard | NVRAM->addr = 0x0000;
|
497 | a541f297 | bellard | break;
|
498 | a541f297 | bellard | default:
|
499 | a541f297 | bellard | break;
|
500 | a541f297 | bellard | } |
501 | a541f297 | bellard | } |
502 | a541f297 | bellard | |
503 | 087bd055 | Alexander Graf | static uint64_t NVRAM_readb(void *opaque, hwaddr addr, unsigned size) |
504 | a541f297 | bellard | { |
505 | 43a34704 | Blue Swirl | M48t59State *NVRAM = opaque; |
506 | 13ab5daa | bellard | uint32_t retval; |
507 | a541f297 | bellard | |
508 | 13ab5daa | bellard | switch (addr) {
|
509 | 13ab5daa | bellard | case 3: |
510 | 819385c5 | bellard | retval = m48t59_read(NVRAM, NVRAM->addr); |
511 | 13ab5daa | bellard | break;
|
512 | 13ab5daa | bellard | default:
|
513 | 13ab5daa | bellard | retval = -1;
|
514 | 13ab5daa | bellard | break;
|
515 | 13ab5daa | bellard | } |
516 | 9ed1e667 | blueswir1 | NVRAM_PRINTF("%s: 0x%08x <= 0x%08x\n", __func__, addr, retval);
|
517 | a541f297 | bellard | |
518 | 13ab5daa | bellard | return retval;
|
519 | a541f297 | bellard | } |
520 | a541f297 | bellard | |
521 | a8170e5e | Avi Kivity | static void nvram_writeb (void *opaque, hwaddr addr, uint32_t value) |
522 | e1bb04f7 | bellard | { |
523 | 43a34704 | Blue Swirl | M48t59State *NVRAM = opaque; |
524 | 3b46e624 | ths | |
525 | 819385c5 | bellard | m48t59_write(NVRAM, addr, value & 0xff);
|
526 | e1bb04f7 | bellard | } |
527 | e1bb04f7 | bellard | |
528 | a8170e5e | Avi Kivity | static void nvram_writew (void *opaque, hwaddr addr, uint32_t value) |
529 | e1bb04f7 | bellard | { |
530 | 43a34704 | Blue Swirl | M48t59State *NVRAM = opaque; |
531 | 3b46e624 | ths | |
532 | 819385c5 | bellard | m48t59_write(NVRAM, addr, (value >> 8) & 0xff); |
533 | 819385c5 | bellard | m48t59_write(NVRAM, addr + 1, value & 0xff); |
534 | e1bb04f7 | bellard | } |
535 | e1bb04f7 | bellard | |
536 | a8170e5e | Avi Kivity | static void nvram_writel (void *opaque, hwaddr addr, uint32_t value) |
537 | e1bb04f7 | bellard | { |
538 | 43a34704 | Blue Swirl | M48t59State *NVRAM = opaque; |
539 | 3b46e624 | ths | |
540 | 819385c5 | bellard | m48t59_write(NVRAM, addr, (value >> 24) & 0xff); |
541 | 819385c5 | bellard | m48t59_write(NVRAM, addr + 1, (value >> 16) & 0xff); |
542 | 819385c5 | bellard | m48t59_write(NVRAM, addr + 2, (value >> 8) & 0xff); |
543 | 819385c5 | bellard | m48t59_write(NVRAM, addr + 3, value & 0xff); |
544 | e1bb04f7 | bellard | } |
545 | e1bb04f7 | bellard | |
546 | a8170e5e | Avi Kivity | static uint32_t nvram_readb (void *opaque, hwaddr addr) |
547 | e1bb04f7 | bellard | { |
548 | 43a34704 | Blue Swirl | M48t59State *NVRAM = opaque; |
549 | 819385c5 | bellard | uint32_t retval; |
550 | 3b46e624 | ths | |
551 | 819385c5 | bellard | retval = m48t59_read(NVRAM, addr); |
552 | e1bb04f7 | bellard | return retval;
|
553 | e1bb04f7 | bellard | } |
554 | e1bb04f7 | bellard | |
555 | a8170e5e | Avi Kivity | static uint32_t nvram_readw (void *opaque, hwaddr addr) |
556 | e1bb04f7 | bellard | { |
557 | 43a34704 | Blue Swirl | M48t59State *NVRAM = opaque; |
558 | 819385c5 | bellard | uint32_t retval; |
559 | 3b46e624 | ths | |
560 | 819385c5 | bellard | retval = m48t59_read(NVRAM, addr) << 8;
|
561 | 819385c5 | bellard | retval |= m48t59_read(NVRAM, addr + 1);
|
562 | e1bb04f7 | bellard | return retval;
|
563 | e1bb04f7 | bellard | } |
564 | e1bb04f7 | bellard | |
565 | a8170e5e | Avi Kivity | static uint32_t nvram_readl (void *opaque, hwaddr addr) |
566 | e1bb04f7 | bellard | { |
567 | 43a34704 | Blue Swirl | M48t59State *NVRAM = opaque; |
568 | 819385c5 | bellard | uint32_t retval; |
569 | e1bb04f7 | bellard | |
570 | 819385c5 | bellard | retval = m48t59_read(NVRAM, addr) << 24;
|
571 | 819385c5 | bellard | retval |= m48t59_read(NVRAM, addr + 1) << 16; |
572 | 819385c5 | bellard | retval |= m48t59_read(NVRAM, addr + 2) << 8; |
573 | 819385c5 | bellard | retval |= m48t59_read(NVRAM, addr + 3);
|
574 | e1bb04f7 | bellard | return retval;
|
575 | e1bb04f7 | bellard | } |
576 | e1bb04f7 | bellard | |
577 | 5a31cd68 | Avi Kivity | static const MemoryRegionOps nvram_ops = { |
578 | 5a31cd68 | Avi Kivity | .old_mmio = { |
579 | 5a31cd68 | Avi Kivity | .read = { nvram_readb, nvram_readw, nvram_readl, }, |
580 | 5a31cd68 | Avi Kivity | .write = { nvram_writeb, nvram_writew, nvram_writel, }, |
581 | 5a31cd68 | Avi Kivity | }, |
582 | 5a31cd68 | Avi Kivity | .endianness = DEVICE_NATIVE_ENDIAN, |
583 | e1bb04f7 | bellard | }; |
584 | 819385c5 | bellard | |
585 | fd484ae4 | Juan Quintela | static const VMStateDescription vmstate_m48t59 = { |
586 | fd484ae4 | Juan Quintela | .name = "m48t59",
|
587 | fd484ae4 | Juan Quintela | .version_id = 1,
|
588 | fd484ae4 | Juan Quintela | .minimum_version_id = 1,
|
589 | fd484ae4 | Juan Quintela | .minimum_version_id_old = 1,
|
590 | fd484ae4 | Juan Quintela | .fields = (VMStateField[]) { |
591 | fd484ae4 | Juan Quintela | VMSTATE_UINT8(lock, M48t59State), |
592 | fd484ae4 | Juan Quintela | VMSTATE_UINT16(addr, M48t59State), |
593 | fd484ae4 | Juan Quintela | VMSTATE_VBUFFER_UINT32(buffer, M48t59State, 0, NULL, 0, size), |
594 | fd484ae4 | Juan Quintela | VMSTATE_END_OF_LIST() |
595 | fd484ae4 | Juan Quintela | } |
596 | fd484ae4 | Juan Quintela | }; |
597 | 3ccacc4a | blueswir1 | |
598 | 43a34704 | Blue Swirl | static void m48t59_reset_common(M48t59State *NVRAM) |
599 | 3ccacc4a | blueswir1 | { |
600 | 6e6b7363 | blueswir1 | NVRAM->addr = 0;
|
601 | 6e6b7363 | blueswir1 | NVRAM->lock = 0;
|
602 | 3ccacc4a | blueswir1 | if (NVRAM->alrm_timer != NULL) |
603 | 3ccacc4a | blueswir1 | qemu_del_timer(NVRAM->alrm_timer); |
604 | 3ccacc4a | blueswir1 | |
605 | 3ccacc4a | blueswir1 | if (NVRAM->wd_timer != NULL) |
606 | 3ccacc4a | blueswir1 | qemu_del_timer(NVRAM->wd_timer); |
607 | 3ccacc4a | blueswir1 | } |
608 | 3ccacc4a | blueswir1 | |
609 | 285e468d | Blue Swirl | static void m48t59_reset_isa(DeviceState *d) |
610 | 285e468d | Blue Swirl | { |
611 | 285e468d | Blue Swirl | M48t59ISAState *isa = container_of(d, M48t59ISAState, busdev.qdev); |
612 | 43a34704 | Blue Swirl | M48t59State *NVRAM = &isa->state; |
613 | 285e468d | Blue Swirl | |
614 | 285e468d | Blue Swirl | m48t59_reset_common(NVRAM); |
615 | 285e468d | Blue Swirl | } |
616 | 285e468d | Blue Swirl | |
617 | 285e468d | Blue Swirl | static void m48t59_reset_sysbus(DeviceState *d) |
618 | 285e468d | Blue Swirl | { |
619 | 285e468d | Blue Swirl | M48t59SysBusState *sys = container_of(d, M48t59SysBusState, busdev.qdev); |
620 | 43a34704 | Blue Swirl | M48t59State *NVRAM = &sys->state; |
621 | 285e468d | Blue Swirl | |
622 | 285e468d | Blue Swirl | m48t59_reset_common(NVRAM); |
623 | 285e468d | Blue Swirl | } |
624 | 285e468d | Blue Swirl | |
625 | 9936d6e4 | Richard Henderson | static const MemoryRegionOps m48t59_io_ops = { |
626 | 087bd055 | Alexander Graf | .read = NVRAM_readb, |
627 | 087bd055 | Alexander Graf | .write = NVRAM_writeb, |
628 | 087bd055 | Alexander Graf | .impl = { |
629 | 087bd055 | Alexander Graf | .min_access_size = 1,
|
630 | 087bd055 | Alexander Graf | .max_access_size = 1,
|
631 | 087bd055 | Alexander Graf | }, |
632 | 087bd055 | Alexander Graf | .endianness = DEVICE_LITTLE_ENDIAN, |
633 | 9936d6e4 | Richard Henderson | }; |
634 | 9936d6e4 | Richard Henderson | |
635 | a541f297 | bellard | /* Initialisation routine */
|
636 | a8170e5e | Avi Kivity | M48t59State *m48t59_init(qemu_irq IRQ, hwaddr mem_base, |
637 | 7bc3018b | Paolo Bonzini | uint32_t io_base, uint16_t size, int model)
|
638 | a541f297 | bellard | { |
639 | d27cf0ae | Blue Swirl | DeviceState *dev; |
640 | d27cf0ae | Blue Swirl | SysBusDevice *s; |
641 | f80237d4 | Blue Swirl | M48t59SysBusState *d; |
642 | 51f9b84e | Hervé Poussineau | M48t59State *state; |
643 | d27cf0ae | Blue Swirl | |
644 | d27cf0ae | Blue Swirl | dev = qdev_create(NULL, "m48t59"); |
645 | 7bc3018b | Paolo Bonzini | qdev_prop_set_uint32(dev, "model", model);
|
646 | ee6847d1 | Gerd Hoffmann | qdev_prop_set_uint32(dev, "size", size);
|
647 | ee6847d1 | Gerd Hoffmann | qdev_prop_set_uint32(dev, "io_base", io_base);
|
648 | e23a1b33 | Markus Armbruster | qdev_init_nofail(dev); |
649 | 1356b98d | Andreas Färber | s = SYS_BUS_DEVICE(dev); |
650 | 51f9b84e | Hervé Poussineau | d = FROM_SYSBUS(M48t59SysBusState, s); |
651 | 51f9b84e | Hervé Poussineau | state = &d->state; |
652 | d27cf0ae | Blue Swirl | sysbus_connect_irq(s, 0, IRQ);
|
653 | 087bd055 | Alexander Graf | memory_region_init_io(&d->io, &m48t59_io_ops, state, "m48t59", 4); |
654 | 819385c5 | bellard | if (io_base != 0) { |
655 | 087bd055 | Alexander Graf | memory_region_add_subregion(get_system_io(), io_base, &d->io); |
656 | 819385c5 | bellard | } |
657 | e1bb04f7 | bellard | if (mem_base != 0) { |
658 | d27cf0ae | Blue Swirl | sysbus_mmio_map(s, 0, mem_base);
|
659 | e1bb04f7 | bellard | } |
660 | d27cf0ae | Blue Swirl | |
661 | 51f9b84e | Hervé Poussineau | return state;
|
662 | d27cf0ae | Blue Swirl | } |
663 | d27cf0ae | Blue Swirl | |
664 | 48a18b3c | Hervé Poussineau | M48t59State *m48t59_init_isa(ISABus *bus, uint32_t io_base, uint16_t size, |
665 | 7bc3018b | Paolo Bonzini | int model)
|
666 | d27cf0ae | Blue Swirl | { |
667 | f80237d4 | Blue Swirl | M48t59ISAState *d; |
668 | f80237d4 | Blue Swirl | ISADevice *dev; |
669 | 43a34704 | Blue Swirl | M48t59State *s; |
670 | f80237d4 | Blue Swirl | |
671 | 48a18b3c | Hervé Poussineau | dev = isa_create(bus, "m48t59_isa");
|
672 | 7bc3018b | Paolo Bonzini | qdev_prop_set_uint32(&dev->qdev, "model", model);
|
673 | f80237d4 | Blue Swirl | qdev_prop_set_uint32(&dev->qdev, "size", size);
|
674 | f80237d4 | Blue Swirl | qdev_prop_set_uint32(&dev->qdev, "io_base", io_base);
|
675 | e23a1b33 | Markus Armbruster | qdev_init_nofail(&dev->qdev); |
676 | f80237d4 | Blue Swirl | d = DO_UPCAST(M48t59ISAState, busdev, dev); |
677 | f80237d4 | Blue Swirl | s = &d->state; |
678 | d27cf0ae | Blue Swirl | |
679 | 9936d6e4 | Richard Henderson | memory_region_init_io(&d->io, &m48t59_io_ops, s, "m48t59", 4); |
680 | f80237d4 | Blue Swirl | if (io_base != 0) { |
681 | 9936d6e4 | Richard Henderson | isa_register_ioport(dev, &d->io, io_base); |
682 | f80237d4 | Blue Swirl | } |
683 | d27cf0ae | Blue Swirl | |
684 | f80237d4 | Blue Swirl | return s;
|
685 | f80237d4 | Blue Swirl | } |
686 | d27cf0ae | Blue Swirl | |
687 | 43a34704 | Blue Swirl | static void m48t59_init_common(M48t59State *s) |
688 | f80237d4 | Blue Swirl | { |
689 | 7267c094 | Anthony Liguori | s->buffer = g_malloc0(s->size); |
690 | 7bc3018b | Paolo Bonzini | if (s->model == 59) { |
691 | 1d849502 | Paolo Bonzini | s->alrm_timer = qemu_new_timer_ns(rtc_clock, &alarm_cb, s); |
692 | 74475455 | Paolo Bonzini | s->wd_timer = qemu_new_timer_ns(vm_clock, &watchdog_cb, s); |
693 | 819385c5 | bellard | } |
694 | f6503059 | balrog | qemu_get_timedate(&s->alarm, 0);
|
695 | 13ab5daa | bellard | |
696 | fd484ae4 | Juan Quintela | vmstate_register(NULL, -1, &vmstate_m48t59, s); |
697 | f80237d4 | Blue Swirl | } |
698 | f80237d4 | Blue Swirl | |
699 | f80237d4 | Blue Swirl | static int m48t59_init_isa1(ISADevice *dev) |
700 | f80237d4 | Blue Swirl | { |
701 | f80237d4 | Blue Swirl | M48t59ISAState *d = DO_UPCAST(M48t59ISAState, busdev, dev); |
702 | 43a34704 | Blue Swirl | M48t59State *s = &d->state; |
703 | f80237d4 | Blue Swirl | |
704 | f80237d4 | Blue Swirl | isa_init_irq(dev, &s->IRQ, 8);
|
705 | f80237d4 | Blue Swirl | m48t59_init_common(s); |
706 | f80237d4 | Blue Swirl | |
707 | 81a322d4 | Gerd Hoffmann | return 0; |
708 | d27cf0ae | Blue Swirl | } |
709 | 3ccacc4a | blueswir1 | |
710 | f80237d4 | Blue Swirl | static int m48t59_init1(SysBusDevice *dev) |
711 | f80237d4 | Blue Swirl | { |
712 | f80237d4 | Blue Swirl | M48t59SysBusState *d = FROM_SYSBUS(M48t59SysBusState, dev); |
713 | 43a34704 | Blue Swirl | M48t59State *s = &d->state; |
714 | f80237d4 | Blue Swirl | |
715 | f80237d4 | Blue Swirl | sysbus_init_irq(dev, &s->IRQ); |
716 | f80237d4 | Blue Swirl | |
717 | 5a31cd68 | Avi Kivity | memory_region_init_io(&s->iomem, &nvram_ops, s, "m48t59.nvram", s->size);
|
718 | 750ecd44 | Avi Kivity | sysbus_init_mmio(dev, &s->iomem); |
719 | f80237d4 | Blue Swirl | m48t59_init_common(s); |
720 | f80237d4 | Blue Swirl | |
721 | f80237d4 | Blue Swirl | return 0; |
722 | f80237d4 | Blue Swirl | } |
723 | f80237d4 | Blue Swirl | |
724 | 39bffca2 | Anthony Liguori | static Property m48t59_isa_properties[] = {
|
725 | 39bffca2 | Anthony Liguori | DEFINE_PROP_UINT32("size", M48t59ISAState, state.size, -1), |
726 | 7bc3018b | Paolo Bonzini | DEFINE_PROP_UINT32("model", M48t59ISAState, state.model, -1), |
727 | 39bffca2 | Anthony Liguori | DEFINE_PROP_HEX32( "io_base", M48t59ISAState, state.io_base, 0), |
728 | 39bffca2 | Anthony Liguori | DEFINE_PROP_END_OF_LIST(), |
729 | 39bffca2 | Anthony Liguori | }; |
730 | 39bffca2 | Anthony Liguori | |
731 | 8f04ee08 | Anthony Liguori | static void m48t59_init_class_isa1(ObjectClass *klass, void *data) |
732 | 8f04ee08 | Anthony Liguori | { |
733 | 39bffca2 | Anthony Liguori | DeviceClass *dc = DEVICE_CLASS(klass); |
734 | 8f04ee08 | Anthony Liguori | ISADeviceClass *ic = ISA_DEVICE_CLASS(klass); |
735 | 8f04ee08 | Anthony Liguori | ic->init = m48t59_init_isa1; |
736 | 39bffca2 | Anthony Liguori | dc->no_user = 1;
|
737 | 39bffca2 | Anthony Liguori | dc->reset = m48t59_reset_isa; |
738 | 39bffca2 | Anthony Liguori | dc->props = m48t59_isa_properties; |
739 | 8f04ee08 | Anthony Liguori | } |
740 | 8f04ee08 | Anthony Liguori | |
741 | 8c43a6f0 | Andreas Färber | static const TypeInfo m48t59_isa_info = { |
742 | 39bffca2 | Anthony Liguori | .name = "m48t59_isa",
|
743 | 39bffca2 | Anthony Liguori | .parent = TYPE_ISA_DEVICE, |
744 | 39bffca2 | Anthony Liguori | .instance_size = sizeof(M48t59ISAState),
|
745 | 39bffca2 | Anthony Liguori | .class_init = m48t59_init_class_isa1, |
746 | f80237d4 | Blue Swirl | }; |
747 | f80237d4 | Blue Swirl | |
748 | 999e12bb | Anthony Liguori | static Property m48t59_properties[] = {
|
749 | 999e12bb | Anthony Liguori | DEFINE_PROP_UINT32("size", M48t59SysBusState, state.size, -1), |
750 | 7bc3018b | Paolo Bonzini | DEFINE_PROP_UINT32("model", M48t59SysBusState, state.model, -1), |
751 | 999e12bb | Anthony Liguori | DEFINE_PROP_HEX32( "io_base", M48t59SysBusState, state.io_base, 0), |
752 | 999e12bb | Anthony Liguori | DEFINE_PROP_END_OF_LIST(), |
753 | 999e12bb | Anthony Liguori | }; |
754 | 999e12bb | Anthony Liguori | |
755 | 999e12bb | Anthony Liguori | static void m48t59_class_init(ObjectClass *klass, void *data) |
756 | 999e12bb | Anthony Liguori | { |
757 | 39bffca2 | Anthony Liguori | DeviceClass *dc = DEVICE_CLASS(klass); |
758 | 999e12bb | Anthony Liguori | SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); |
759 | 999e12bb | Anthony Liguori | |
760 | 999e12bb | Anthony Liguori | k->init = m48t59_init1; |
761 | 39bffca2 | Anthony Liguori | dc->reset = m48t59_reset_sysbus; |
762 | 39bffca2 | Anthony Liguori | dc->props = m48t59_properties; |
763 | 999e12bb | Anthony Liguori | } |
764 | 999e12bb | Anthony Liguori | |
765 | 8c43a6f0 | Andreas Färber | static const TypeInfo m48t59_info = { |
766 | 39bffca2 | Anthony Liguori | .name = "m48t59",
|
767 | 39bffca2 | Anthony Liguori | .parent = TYPE_SYS_BUS_DEVICE, |
768 | 39bffca2 | Anthony Liguori | .instance_size = sizeof(M48t59SysBusState),
|
769 | 39bffca2 | Anthony Liguori | .class_init = m48t59_class_init, |
770 | ee6847d1 | Gerd Hoffmann | }; |
771 | ee6847d1 | Gerd Hoffmann | |
772 | 83f7d43a | Andreas Färber | static void m48t59_register_types(void) |
773 | d27cf0ae | Blue Swirl | { |
774 | 39bffca2 | Anthony Liguori | type_register_static(&m48t59_info); |
775 | 39bffca2 | Anthony Liguori | type_register_static(&m48t59_isa_info); |
776 | a541f297 | bellard | } |
777 | d27cf0ae | Blue Swirl | |
778 | 83f7d43a | Andreas Färber | type_init(m48t59_register_types) |