Revision 7839ff59
b/hw/i386/pc_piix.c | ||
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57 | 57 |
static const int ide_iobase2[MAX_IDE_BUS] = { 0x3f6, 0x376 }; |
58 | 58 |
static const int ide_irq[MAX_IDE_BUS] = { 14, 15 }; |
59 | 59 |
|
60 |
static bool has_pvpanic; |
|
61 | 60 |
static bool has_pci_info; |
62 | 61 |
static bool has_acpi_build = true; |
63 | 62 |
|
... | ... | |
229 | 228 |
if (pci_enabled) { |
230 | 229 |
pc_pci_device_init(pci_bus); |
231 | 230 |
} |
232 |
|
|
233 |
if (has_pvpanic) { |
|
234 |
pvpanic_init(isa_bus); |
|
235 |
} |
|
236 | 231 |
} |
237 | 232 |
|
238 | 233 |
static void pc_init_pci(QEMUMachineInitArgs *args) |
... | ... | |
250 | 245 |
static void pc_compat_1_5(QEMUMachineInitArgs *args) |
251 | 246 |
{ |
252 | 247 |
pc_compat_1_6(args); |
253 |
has_pvpanic = true; |
|
254 | 248 |
} |
255 | 249 |
|
256 | 250 |
static void pc_compat_1_4(QEMUMachineInitArgs *args) |
257 | 251 |
{ |
258 | 252 |
pc_compat_1_5(args); |
259 |
has_pvpanic = false; |
|
260 | 253 |
x86_cpu_compat_set_features("n270", FEAT_1_ECX, 0, CPUID_EXT_MOVBE); |
261 | 254 |
x86_cpu_compat_set_features("Westmere", FEAT_1_ECX, 0, CPUID_EXT_PCLMULQDQ); |
262 | 255 |
} |
b/hw/i386/pc_q35.c | ||
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47 | 47 |
/* ICH9 AHCI has 6 ports */ |
48 | 48 |
#define MAX_SATA_PORTS 6 |
49 | 49 |
|
50 |
static bool has_pvpanic; |
|
51 | 50 |
static bool has_pci_info; |
52 | 51 |
static bool has_acpi_build = true; |
53 | 52 |
|
... | ... | |
216 | 215 |
if (pci_enabled) { |
217 | 216 |
pc_pci_device_init(host_bus); |
218 | 217 |
} |
219 |
|
|
220 |
if (has_pvpanic) { |
|
221 |
pvpanic_init(isa_bus); |
|
222 |
} |
|
223 | 218 |
} |
224 | 219 |
|
225 | 220 |
static void pc_compat_1_6(QEMUMachineInitArgs *args) |
... | ... | |
232 | 227 |
static void pc_compat_1_5(QEMUMachineInitArgs *args) |
233 | 228 |
{ |
234 | 229 |
pc_compat_1_6(args); |
235 |
has_pvpanic = true; |
|
236 | 230 |
} |
237 | 231 |
|
238 | 232 |
static void pc_compat_1_4(QEMUMachineInitArgs *args) |
239 | 233 |
{ |
240 | 234 |
pc_compat_1_5(args); |
241 |
has_pvpanic = false; |
|
242 | 235 |
x86_cpu_compat_set_features("n270", FEAT_1_ECX, 0, CPUID_EXT_MOVBE); |
243 | 236 |
x86_cpu_compat_set_features("Westmere", FEAT_1_ECX, 0, CPUID_EXT_PCLMULQDQ); |
244 | 237 |
} |
b/hw/misc/pvpanic.c | ||
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112 | 112 |
isa_register_ioport(d, &s->io, s->ioport); |
113 | 113 |
} |
114 | 114 |
|
115 |
void pvpanic_init(ISABus *bus) |
|
116 |
{ |
|
117 |
isa_create_simple(bus, TYPE_ISA_PVPANIC_DEVICE); |
|
118 |
} |
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119 |
|
|
120 | 115 |
#define PVPANIC_IOPORT_PROP "ioport" |
121 | 116 |
|
122 | 117 |
uint16_t pvpanic_port(void) |
b/include/hw/i386/pc.h | ||
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235 | 235 |
bool isapc_ram_fw); |
236 | 236 |
|
237 | 237 |
/* pvpanic.c */ |
238 |
void pvpanic_init(ISABus *bus); |
|
239 | 238 |
uint16_t pvpanic_port(void); |
240 | 239 |
|
241 | 240 |
/* e820 types */ |
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