Revision 78723684 target-mips/translate.c
| b/target-mips/translate.c | ||
|---|---|---|
| 1088 | 1088 |
int base, int16_t offset) |
| 1089 | 1089 |
{
|
| 1090 | 1090 |
const char *opn = "ldst"; |
| 1091 |
TCGv t0 = tcg_temp_local_new(TCG_TYPE_TL); |
|
| 1092 |
TCGv t1 = tcg_temp_local_new(TCG_TYPE_TL); |
|
| 1091 | 1093 |
|
| 1092 | 1094 |
if (base == 0) {
|
| 1093 |
tcg_gen_movi_tl(cpu_T[0], offset);
|
|
| 1095 |
tcg_gen_movi_tl(t0, offset);
|
|
| 1094 | 1096 |
} else if (offset == 0) {
|
| 1095 |
gen_load_gpr(cpu_T[0], base);
|
|
| 1097 |
gen_load_gpr(t0, base);
|
|
| 1096 | 1098 |
} else {
|
| 1097 |
gen_load_gpr(cpu_T[0], base);
|
|
| 1098 |
tcg_gen_movi_tl(cpu_T[1], offset);
|
|
| 1099 |
gen_op_addr_add(cpu_T[0], cpu_T[1]);
|
|
| 1099 |
gen_load_gpr(t0, base);
|
|
| 1100 |
tcg_gen_movi_tl(t1, offset);
|
|
| 1101 |
gen_op_addr_add(t0, t1);
|
|
| 1100 | 1102 |
} |
| 1101 | 1103 |
/* Don't do NOP if destination is zero: we must perform the actual |
| 1102 | 1104 |
memory access. */ |
| 1103 | 1105 |
switch (opc) {
|
| 1104 | 1106 |
#if defined(TARGET_MIPS64) |
| 1105 | 1107 |
case OPC_LWU: |
| 1106 |
op_ldst_lwu(cpu_T[0], ctx);
|
|
| 1107 |
gen_store_gpr(cpu_T[0], rt);
|
|
| 1108 |
op_ldst_lwu(t0, ctx);
|
|
| 1109 |
gen_store_gpr(t0, rt);
|
|
| 1108 | 1110 |
opn = "lwu"; |
| 1109 | 1111 |
break; |
| 1110 | 1112 |
case OPC_LD: |
| 1111 |
op_ldst_ld(cpu_T[0], ctx);
|
|
| 1112 |
gen_store_gpr(cpu_T[0], rt);
|
|
| 1113 |
op_ldst_ld(t0, ctx);
|
|
| 1114 |
gen_store_gpr(t0, rt);
|
|
| 1113 | 1115 |
opn = "ld"; |
| 1114 | 1116 |
break; |
| 1115 | 1117 |
case OPC_LLD: |
| 1116 |
op_ldst_lld(cpu_T[0], cpu_T[1], ctx);
|
|
| 1117 |
gen_store_gpr(cpu_T[0], rt);
|
|
| 1118 |
op_ldst_lld(t0, t1, ctx);
|
|
| 1119 |
gen_store_gpr(t0, rt);
|
|
| 1118 | 1120 |
opn = "lld"; |
| 1119 | 1121 |
break; |
| 1120 | 1122 |
case OPC_SD: |
| 1121 |
gen_load_gpr(cpu_T[1], rt);
|
|
| 1122 |
op_ldst_sd(cpu_T[0], cpu_T[1], ctx);
|
|
| 1123 |
gen_load_gpr(t1, rt);
|
|
| 1124 |
op_ldst_sd(t0, t1, ctx);
|
|
| 1123 | 1125 |
opn = "sd"; |
| 1124 | 1126 |
break; |
| 1125 | 1127 |
case OPC_SCD: |
| 1126 | 1128 |
save_cpu_state(ctx, 1); |
| 1127 |
gen_load_gpr(cpu_T[1], rt);
|
|
| 1128 |
op_ldst_scd(cpu_T[0], cpu_T[1], ctx);
|
|
| 1129 |
gen_store_gpr(cpu_T[0], rt);
|
|
| 1129 |
gen_load_gpr(t1, rt);
|
|
| 1130 |
op_ldst_scd(t0, t1, ctx);
|
|
| 1131 |
gen_store_gpr(t0, rt);
|
|
| 1130 | 1132 |
opn = "scd"; |
| 1131 | 1133 |
break; |
| 1132 | 1134 |
case OPC_LDL: |
| 1133 | 1135 |
save_cpu_state(ctx, 1); |
| 1134 |
gen_load_gpr(cpu_T[1], rt);
|
|
| 1135 |
tcg_gen_helper_1_2i(do_ldl, cpu_T[1], cpu_T[0], cpu_T[1], ctx->mem_idx);
|
|
| 1136 |
gen_store_gpr(cpu_T[1], rt);
|
|
| 1136 |
gen_load_gpr(t1, rt);
|
|
| 1137 |
tcg_gen_helper_1_2i(do_ldl, t1, t0, t1, ctx->mem_idx);
|
|
| 1138 |
gen_store_gpr(t1, rt);
|
|
| 1137 | 1139 |
opn = "ldl"; |
| 1138 | 1140 |
break; |
| 1139 | 1141 |
case OPC_SDL: |
| 1140 | 1142 |
save_cpu_state(ctx, 1); |
| 1141 |
gen_load_gpr(cpu_T[1], rt);
|
|
| 1142 |
tcg_gen_helper_0_2i(do_sdl, cpu_T[0], cpu_T[1], ctx->mem_idx);
|
|
| 1143 |
gen_load_gpr(t1, rt);
|
|
| 1144 |
tcg_gen_helper_0_2i(do_sdl, t0, t1, ctx->mem_idx);
|
|
| 1143 | 1145 |
opn = "sdl"; |
| 1144 | 1146 |
break; |
| 1145 | 1147 |
case OPC_LDR: |
| 1146 | 1148 |
save_cpu_state(ctx, 1); |
| 1147 |
gen_load_gpr(cpu_T[1], rt);
|
|
| 1148 |
tcg_gen_helper_1_2i(do_ldr, cpu_T[1], cpu_T[0], cpu_T[1], ctx->mem_idx);
|
|
| 1149 |
gen_store_gpr(cpu_T[1], rt);
|
|
| 1149 |
gen_load_gpr(t1, rt);
|
|
| 1150 |
tcg_gen_helper_1_2i(do_ldr, t1, t0, t1, ctx->mem_idx);
|
|
| 1151 |
gen_store_gpr(t1, rt);
|
|
| 1150 | 1152 |
opn = "ldr"; |
| 1151 | 1153 |
break; |
| 1152 | 1154 |
case OPC_SDR: |
| 1153 | 1155 |
save_cpu_state(ctx, 1); |
| 1154 |
gen_load_gpr(cpu_T[1], rt);
|
|
| 1155 |
tcg_gen_helper_0_2i(do_sdr, cpu_T[0], cpu_T[1], ctx->mem_idx);
|
|
| 1156 |
gen_load_gpr(t1, rt);
|
|
| 1157 |
tcg_gen_helper_0_2i(do_sdr, t0, t1, ctx->mem_idx);
|
|
| 1156 | 1158 |
opn = "sdr"; |
| 1157 | 1159 |
break; |
| 1158 | 1160 |
#endif |
| 1159 | 1161 |
case OPC_LW: |
| 1160 |
op_ldst_lw(cpu_T[0], ctx);
|
|
| 1161 |
gen_store_gpr(cpu_T[0], rt);
|
|
| 1162 |
op_ldst_lw(t0, ctx);
|
|
| 1163 |
gen_store_gpr(t0, rt);
|
|
| 1162 | 1164 |
opn = "lw"; |
| 1163 | 1165 |
break; |
| 1164 | 1166 |
case OPC_SW: |
| 1165 |
gen_load_gpr(cpu_T[1], rt);
|
|
| 1166 |
op_ldst_sw(cpu_T[0], cpu_T[1], ctx);
|
|
| 1167 |
gen_load_gpr(t1, rt);
|
|
| 1168 |
op_ldst_sw(t0, t1, ctx);
|
|
| 1167 | 1169 |
opn = "sw"; |
| 1168 | 1170 |
break; |
| 1169 | 1171 |
case OPC_LH: |
| 1170 |
op_ldst_lh(cpu_T[0], ctx);
|
|
| 1171 |
gen_store_gpr(cpu_T[0], rt);
|
|
| 1172 |
op_ldst_lh(t0, ctx);
|
|
| 1173 |
gen_store_gpr(t0, rt);
|
|
| 1172 | 1174 |
opn = "lh"; |
| 1173 | 1175 |
break; |
| 1174 | 1176 |
case OPC_SH: |
| 1175 |
gen_load_gpr(cpu_T[1], rt);
|
|
| 1176 |
op_ldst_sh(cpu_T[0], cpu_T[1], ctx);
|
|
| 1177 |
gen_load_gpr(t1, rt);
|
|
| 1178 |
op_ldst_sh(t0, t1, ctx);
|
|
| 1177 | 1179 |
opn = "sh"; |
| 1178 | 1180 |
break; |
| 1179 | 1181 |
case OPC_LHU: |
| 1180 |
op_ldst_lhu(cpu_T[0], ctx);
|
|
| 1181 |
gen_store_gpr(cpu_T[0], rt);
|
|
| 1182 |
op_ldst_lhu(t0, ctx);
|
|
| 1183 |
gen_store_gpr(t0, rt);
|
|
| 1182 | 1184 |
opn = "lhu"; |
| 1183 | 1185 |
break; |
| 1184 | 1186 |
case OPC_LB: |
| 1185 |
op_ldst_lb(cpu_T[0], ctx);
|
|
| 1186 |
gen_store_gpr(cpu_T[0], rt);
|
|
| 1187 |
op_ldst_lb(t0, ctx);
|
|
| 1188 |
gen_store_gpr(t0, rt);
|
|
| 1187 | 1189 |
opn = "lb"; |
| 1188 | 1190 |
break; |
| 1189 | 1191 |
case OPC_SB: |
| 1190 |
gen_load_gpr(cpu_T[1], rt);
|
|
| 1191 |
op_ldst_sb(cpu_T[0], cpu_T[1], ctx);
|
|
| 1192 |
gen_load_gpr(t1, rt);
|
|
| 1193 |
op_ldst_sb(t0, t1, ctx);
|
|
| 1192 | 1194 |
opn = "sb"; |
| 1193 | 1195 |
break; |
| 1194 | 1196 |
case OPC_LBU: |
| 1195 |
op_ldst_lbu(cpu_T[0], ctx);
|
|
| 1196 |
gen_store_gpr(cpu_T[0], rt);
|
|
| 1197 |
op_ldst_lbu(t0, ctx);
|
|
| 1198 |
gen_store_gpr(t0, rt);
|
|
| 1197 | 1199 |
opn = "lbu"; |
| 1198 | 1200 |
break; |
| 1199 | 1201 |
case OPC_LWL: |
| 1200 | 1202 |
save_cpu_state(ctx, 1); |
| 1201 |
gen_load_gpr(cpu_T[1], rt);
|
|
| 1202 |
tcg_gen_helper_1_2i(do_lwl, cpu_T[1], cpu_T[0], cpu_T[1], ctx->mem_idx);
|
|
| 1203 |
gen_store_gpr(cpu_T[1], rt);
|
|
| 1203 |
gen_load_gpr(t1, rt);
|
|
| 1204 |
tcg_gen_helper_1_2i(do_lwl, t1, t0, t1, ctx->mem_idx);
|
|
| 1205 |
gen_store_gpr(t1, rt);
|
|
| 1204 | 1206 |
opn = "lwl"; |
| 1205 | 1207 |
break; |
| 1206 | 1208 |
case OPC_SWL: |
| 1207 | 1209 |
save_cpu_state(ctx, 1); |
| 1208 |
gen_load_gpr(cpu_T[1], rt);
|
|
| 1209 |
tcg_gen_helper_0_2i(do_swl, cpu_T[0], cpu_T[1], ctx->mem_idx);
|
|
| 1210 |
gen_load_gpr(t1, rt);
|
|
| 1211 |
tcg_gen_helper_0_2i(do_swl, t0, t1, ctx->mem_idx);
|
|
| 1210 | 1212 |
opn = "swr"; |
| 1211 | 1213 |
break; |
| 1212 | 1214 |
case OPC_LWR: |
| 1213 | 1215 |
save_cpu_state(ctx, 1); |
| 1214 |
gen_load_gpr(cpu_T[1], rt);
|
|
| 1215 |
tcg_gen_helper_1_2i(do_lwr, cpu_T[1], cpu_T[0], cpu_T[1], ctx->mem_idx);
|
|
| 1216 |
gen_store_gpr(cpu_T[1], rt);
|
|
| 1216 |
gen_load_gpr(t1, rt);
|
|
| 1217 |
tcg_gen_helper_1_2i(do_lwr, t1, t0, t1, ctx->mem_idx);
|
|
| 1218 |
gen_store_gpr(t1, rt);
|
|
| 1217 | 1219 |
opn = "lwr"; |
| 1218 | 1220 |
break; |
| 1219 | 1221 |
case OPC_SWR: |
| 1220 | 1222 |
save_cpu_state(ctx, 1); |
| 1221 |
gen_load_gpr(cpu_T[1], rt);
|
|
| 1222 |
tcg_gen_helper_0_2i(do_swr, cpu_T[0], cpu_T[1], ctx->mem_idx);
|
|
| 1223 |
gen_load_gpr(t1, rt);
|
|
| 1224 |
tcg_gen_helper_0_2i(do_swr, t0, t1, ctx->mem_idx);
|
|
| 1223 | 1225 |
opn = "swr"; |
| 1224 | 1226 |
break; |
| 1225 | 1227 |
case OPC_LL: |
| 1226 |
op_ldst_ll(cpu_T[0], cpu_T[1], ctx);
|
|
| 1227 |
gen_store_gpr(cpu_T[0], rt);
|
|
| 1228 |
op_ldst_ll(t0, t1, ctx);
|
|
| 1229 |
gen_store_gpr(t0, rt);
|
|
| 1228 | 1230 |
opn = "ll"; |
| 1229 | 1231 |
break; |
| 1230 | 1232 |
case OPC_SC: |
| 1231 | 1233 |
save_cpu_state(ctx, 1); |
| 1232 |
gen_load_gpr(cpu_T[1], rt);
|
|
| 1233 |
op_ldst_sc(cpu_T[0], cpu_T[1], ctx);
|
|
| 1234 |
gen_store_gpr(cpu_T[0], rt);
|
|
| 1234 |
gen_load_gpr(t1, rt);
|
|
| 1235 |
op_ldst_sc(t0, t1, ctx);
|
|
| 1236 |
gen_store_gpr(t0, rt);
|
|
| 1235 | 1237 |
opn = "sc"; |
| 1236 | 1238 |
break; |
| 1237 | 1239 |
default: |
| 1238 | 1240 |
MIPS_INVAL(opn); |
| 1239 | 1241 |
generate_exception(ctx, EXCP_RI); |
| 1240 |
return;
|
|
| 1242 |
goto out;
|
|
| 1241 | 1243 |
} |
| 1242 | 1244 |
MIPS_DEBUG("%s %s, %d(%s)", opn, regnames[rt], offset, regnames[base]);
|
| 1245 |
out: |
|
| 1246 |
tcg_temp_free(t0); |
|
| 1247 |
tcg_temp_free(t1); |
|
| 1243 | 1248 |
} |
| 1244 | 1249 |
|
| 1245 | 1250 |
/* Load and store */ |
| ... | ... | |
| 1247 | 1252 |
int base, int16_t offset) |
| 1248 | 1253 |
{
|
| 1249 | 1254 |
const char *opn = "flt_ldst"; |
| 1255 |
TCGv t0 = tcg_temp_local_new(TCG_TYPE_TL); |
|
| 1250 | 1256 |
|
| 1251 | 1257 |
if (base == 0) {
|
| 1252 |
tcg_gen_movi_tl(cpu_T[0], offset);
|
|
| 1258 |
tcg_gen_movi_tl(t0, offset);
|
|
| 1253 | 1259 |
} else if (offset == 0) {
|
| 1254 |
gen_load_gpr(cpu_T[0], base);
|
|
| 1260 |
gen_load_gpr(t0, base);
|
|
| 1255 | 1261 |
} else {
|
| 1256 |
gen_load_gpr(cpu_T[0], base); |
|
| 1257 |
tcg_gen_movi_tl(cpu_T[1], offset); |
|
| 1258 |
gen_op_addr_add(cpu_T[0], cpu_T[1]); |
|
| 1262 |
TCGv t1 = tcg_temp_local_new(TCG_TYPE_TL); |
|
| 1263 |
|
|
| 1264 |
gen_load_gpr(t0, base); |
|
| 1265 |
tcg_gen_movi_tl(t1, offset); |
|
| 1266 |
gen_op_addr_add(t0, t1); |
|
| 1267 |
tcg_temp_free(t1); |
|
| 1259 | 1268 |
} |
| 1260 | 1269 |
/* Don't do NOP if destination is zero: we must perform the actual |
| 1261 | 1270 |
memory access. */ |
| 1262 | 1271 |
switch (opc) {
|
| 1263 | 1272 |
case OPC_LWC1: |
| 1264 |
tcg_gen_qemu_ld32s(fpu32_T[0], cpu_T[0], ctx->mem_idx);
|
|
| 1273 |
tcg_gen_qemu_ld32s(fpu32_T[0], t0, ctx->mem_idx);
|
|
| 1265 | 1274 |
gen_store_fpr32(fpu32_T[0], ft); |
| 1266 | 1275 |
opn = "lwc1"; |
| 1267 | 1276 |
break; |
| 1268 | 1277 |
case OPC_SWC1: |
| 1269 | 1278 |
gen_load_fpr32(fpu32_T[0], ft); |
| 1270 |
tcg_gen_qemu_st32(fpu32_T[0], cpu_T[0], ctx->mem_idx);
|
|
| 1279 |
tcg_gen_qemu_st32(fpu32_T[0], t0, ctx->mem_idx);
|
|
| 1271 | 1280 |
opn = "swc1"; |
| 1272 | 1281 |
break; |
| 1273 | 1282 |
case OPC_LDC1: |
| 1274 |
tcg_gen_qemu_ld64(fpu64_T[0], cpu_T[0], ctx->mem_idx);
|
|
| 1283 |
tcg_gen_qemu_ld64(fpu64_T[0], t0, ctx->mem_idx);
|
|
| 1275 | 1284 |
gen_store_fpr64(ctx, fpu64_T[0], ft); |
| 1276 | 1285 |
opn = "ldc1"; |
| 1277 | 1286 |
break; |
| 1278 | 1287 |
case OPC_SDC1: |
| 1279 | 1288 |
gen_load_fpr64(ctx, fpu64_T[0], ft); |
| 1280 |
tcg_gen_qemu_st64(fpu64_T[0], cpu_T[0], ctx->mem_idx);
|
|
| 1289 |
tcg_gen_qemu_st64(fpu64_T[0], t0, ctx->mem_idx);
|
|
| 1281 | 1290 |
opn = "sdc1"; |
| 1282 | 1291 |
break; |
| 1283 | 1292 |
default: |
| 1284 | 1293 |
MIPS_INVAL(opn); |
| 1285 | 1294 |
generate_exception(ctx, EXCP_RI); |
| 1286 |
return;
|
|
| 1295 |
goto out;
|
|
| 1287 | 1296 |
} |
| 1288 | 1297 |
MIPS_DEBUG("%s %s, %d(%s)", opn, fregnames[ft], offset, regnames[base]);
|
| 1298 |
out: |
|
| 1299 |
tcg_temp_free(t0); |
|
| 1289 | 1300 |
} |
| 1290 | 1301 |
|
| 1291 | 1302 |
/* Arithmetic with immediate operand */ |
| ... | ... | |
| 1294 | 1305 |
{
|
| 1295 | 1306 |
target_ulong uimm; |
| 1296 | 1307 |
const char *opn = "imm arith"; |
| 1308 |
TCGv t0 = tcg_temp_local_new(TCG_TYPE_TL); |
|
| 1297 | 1309 |
|
| 1298 | 1310 |
if (rt == 0 && opc != OPC_ADDI && opc != OPC_DADDI) {
|
| 1299 | 1311 |
/* If no destination, treat it as a NOP. |
| 1300 | 1312 |
For addi, we must generate the overflow exception when needed. */ |
| 1301 | 1313 |
MIPS_DEBUG("NOP");
|
| 1302 |
return;
|
|
| 1314 |
goto out;
|
|
| 1303 | 1315 |
} |
| 1304 | 1316 |
uimm = (uint16_t)imm; |
| 1305 | 1317 |
switch (opc) {
|
| ... | ... | |
| 1316 | 1328 |
case OPC_ANDI: |
| 1317 | 1329 |
case OPC_ORI: |
| 1318 | 1330 |
case OPC_XORI: |
| 1319 |
gen_load_gpr(cpu_T[0], rs);
|
|
| 1331 |
gen_load_gpr(t0, rs);
|
|
| 1320 | 1332 |
break; |
| 1321 | 1333 |
case OPC_LUI: |
| 1322 |
tcg_gen_movi_tl(cpu_T[0], imm << 16);
|
|
| 1334 |
tcg_gen_movi_tl(t0, imm << 16);
|
|
| 1323 | 1335 |
break; |
| 1324 | 1336 |
case OPC_SLL: |
| 1325 | 1337 |
case OPC_SRA: |
| ... | ... | |
| 1333 | 1345 |
case OPC_DSRL32: |
| 1334 | 1346 |
#endif |
| 1335 | 1347 |
uimm &= 0x1f; |
| 1336 |
gen_load_gpr(cpu_T[0], rs);
|
|
| 1348 |
gen_load_gpr(t0, rs);
|
|
| 1337 | 1349 |
break; |
| 1338 | 1350 |
} |
| 1339 | 1351 |
switch (opc) {
|
| ... | ... | |
| 1344 | 1356 |
int l1 = gen_new_label(); |
| 1345 | 1357 |
|
| 1346 | 1358 |
save_cpu_state(ctx, 1); |
| 1347 |
tcg_gen_ext32s_tl(r_tmp1, cpu_T[0]);
|
|
| 1348 |
tcg_gen_addi_tl(cpu_T[0], r_tmp1, uimm);
|
|
| 1359 |
tcg_gen_ext32s_tl(r_tmp1, t0);
|
|
| 1360 |
tcg_gen_addi_tl(t0, r_tmp1, uimm);
|
|
| 1349 | 1361 |
|
| 1350 | 1362 |
tcg_gen_xori_tl(r_tmp1, r_tmp1, uimm); |
| 1351 | 1363 |
tcg_gen_xori_tl(r_tmp1, r_tmp1, -1); |
| 1352 |
tcg_gen_xori_tl(r_tmp2, cpu_T[0], uimm);
|
|
| 1364 |
tcg_gen_xori_tl(r_tmp2, t0, uimm);
|
|
| 1353 | 1365 |
tcg_gen_and_tl(r_tmp1, r_tmp1, r_tmp2); |
| 1354 | 1366 |
tcg_temp_free(r_tmp2); |
| 1355 | 1367 |
tcg_gen_shri_tl(r_tmp1, r_tmp1, 31); |
| ... | ... | |
| 1359 | 1371 |
generate_exception(ctx, EXCP_OVERFLOW); |
| 1360 | 1372 |
gen_set_label(l1); |
| 1361 | 1373 |
|
| 1362 |
tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
|
|
| 1374 |
tcg_gen_ext32s_tl(t0, t0);
|
|
| 1363 | 1375 |
} |
| 1364 | 1376 |
opn = "addi"; |
| 1365 | 1377 |
break; |
| 1366 | 1378 |
case OPC_ADDIU: |
| 1367 |
tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
|
|
| 1368 |
tcg_gen_addi_tl(cpu_T[0], cpu_T[0], uimm);
|
|
| 1369 |
tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
|
|
| 1379 |
tcg_gen_ext32s_tl(t0, t0);
|
|
| 1380 |
tcg_gen_addi_tl(t0, t0, uimm);
|
|
| 1381 |
tcg_gen_ext32s_tl(t0, t0);
|
|
| 1370 | 1382 |
opn = "addiu"; |
| 1371 | 1383 |
break; |
| 1372 | 1384 |
#if defined(TARGET_MIPS64) |
| ... | ... | |
| 1377 | 1389 |
int l1 = gen_new_label(); |
| 1378 | 1390 |
|
| 1379 | 1391 |
save_cpu_state(ctx, 1); |
| 1380 |
tcg_gen_mov_tl(r_tmp1, cpu_T[0]);
|
|
| 1381 |
tcg_gen_addi_tl(cpu_T[0], cpu_T[0], uimm);
|
|
| 1392 |
tcg_gen_mov_tl(r_tmp1, t0);
|
|
| 1393 |
tcg_gen_addi_tl(t0, t0, uimm);
|
|
| 1382 | 1394 |
|
| 1383 | 1395 |
tcg_gen_xori_tl(r_tmp1, r_tmp1, uimm); |
| 1384 | 1396 |
tcg_gen_xori_tl(r_tmp1, r_tmp1, -1); |
| 1385 |
tcg_gen_xori_tl(r_tmp2, cpu_T[0], uimm);
|
|
| 1397 |
tcg_gen_xori_tl(r_tmp2, t0, uimm);
|
|
| 1386 | 1398 |
tcg_gen_and_tl(r_tmp1, r_tmp1, r_tmp2); |
| 1387 | 1399 |
tcg_temp_free(r_tmp2); |
| 1388 | 1400 |
tcg_gen_shri_tl(r_tmp1, r_tmp1, 63); |
| ... | ... | |
| 1395 | 1407 |
opn = "daddi"; |
| 1396 | 1408 |
break; |
| 1397 | 1409 |
case OPC_DADDIU: |
| 1398 |
tcg_gen_addi_tl(cpu_T[0], cpu_T[0], uimm);
|
|
| 1410 |
tcg_gen_addi_tl(t0, t0, uimm);
|
|
| 1399 | 1411 |
opn = "daddiu"; |
| 1400 | 1412 |
break; |
| 1401 | 1413 |
#endif |
| 1402 | 1414 |
case OPC_SLTI: |
| 1403 |
gen_op_lti(cpu_T[0], uimm);
|
|
| 1415 |
gen_op_lti(t0, uimm);
|
|
| 1404 | 1416 |
opn = "slti"; |
| 1405 | 1417 |
break; |
| 1406 | 1418 |
case OPC_SLTIU: |
| 1407 |
gen_op_ltiu(cpu_T[0], uimm);
|
|
| 1419 |
gen_op_ltiu(t0, uimm);
|
|
| 1408 | 1420 |
opn = "sltiu"; |
| 1409 | 1421 |
break; |
| 1410 | 1422 |
case OPC_ANDI: |
| 1411 |
tcg_gen_andi_tl(cpu_T[0], cpu_T[0], uimm);
|
|
| 1423 |
tcg_gen_andi_tl(t0, t0, uimm);
|
|
| 1412 | 1424 |
opn = "andi"; |
| 1413 | 1425 |
break; |
| 1414 | 1426 |
case OPC_ORI: |
| 1415 |
tcg_gen_ori_tl(cpu_T[0], cpu_T[0], uimm);
|
|
| 1427 |
tcg_gen_ori_tl(t0, t0, uimm);
|
|
| 1416 | 1428 |
opn = "ori"; |
| 1417 | 1429 |
break; |
| 1418 | 1430 |
case OPC_XORI: |
| 1419 |
tcg_gen_xori_tl(cpu_T[0], cpu_T[0], uimm);
|
|
| 1431 |
tcg_gen_xori_tl(t0, t0, uimm);
|
|
| 1420 | 1432 |
opn = "xori"; |
| 1421 | 1433 |
break; |
| 1422 | 1434 |
case OPC_LUI: |
| 1423 | 1435 |
opn = "lui"; |
| 1424 | 1436 |
break; |
| 1425 | 1437 |
case OPC_SLL: |
| 1426 |
tcg_gen_ext32u_tl(cpu_T[0], cpu_T[0]);
|
|
| 1427 |
tcg_gen_shli_tl(cpu_T[0], cpu_T[0], uimm);
|
|
| 1428 |
tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
|
|
| 1438 |
tcg_gen_ext32u_tl(t0, t0);
|
|
| 1439 |
tcg_gen_shli_tl(t0, t0, uimm);
|
|
| 1440 |
tcg_gen_ext32s_tl(t0, t0);
|
|
| 1429 | 1441 |
opn = "sll"; |
| 1430 | 1442 |
break; |
| 1431 | 1443 |
case OPC_SRA: |
| 1432 |
tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
|
|
| 1433 |
tcg_gen_sari_tl(cpu_T[0], cpu_T[0], uimm);
|
|
| 1434 |
tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
|
|
| 1444 |
tcg_gen_ext32s_tl(t0, t0);
|
|
| 1445 |
tcg_gen_sari_tl(t0, t0, uimm);
|
|
| 1446 |
tcg_gen_ext32s_tl(t0, t0);
|
|
| 1435 | 1447 |
opn = "sra"; |
| 1436 | 1448 |
break; |
| 1437 | 1449 |
case OPC_SRL: |
| 1438 | 1450 |
switch ((ctx->opcode >> 21) & 0x1f) {
|
| 1439 | 1451 |
case 0: |
| 1440 |
tcg_gen_ext32u_tl(cpu_T[0], cpu_T[0]);
|
|
| 1441 |
tcg_gen_shri_tl(cpu_T[0], cpu_T[0], uimm);
|
|
| 1442 |
tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
|
|
| 1452 |
tcg_gen_ext32u_tl(t0, t0);
|
|
| 1453 |
tcg_gen_shri_tl(t0, t0, uimm);
|
|
| 1454 |
tcg_gen_ext32s_tl(t0, t0);
|
|
| 1443 | 1455 |
opn = "srl"; |
| 1444 | 1456 |
break; |
| 1445 | 1457 |
case 1: |
| ... | ... | |
| 1449 | 1461 |
TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_I32); |
| 1450 | 1462 |
TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_I32); |
| 1451 | 1463 |
|
| 1452 |
tcg_gen_trunc_tl_i32(r_tmp1, cpu_T[0]);
|
|
| 1464 |
tcg_gen_trunc_tl_i32(r_tmp1, t0);
|
|
| 1453 | 1465 |
tcg_gen_movi_i32(r_tmp2, 0x20); |
| 1454 | 1466 |
tcg_gen_subi_i32(r_tmp2, r_tmp2, uimm); |
| 1455 | 1467 |
tcg_gen_shl_i32(r_tmp2, r_tmp1, r_tmp2); |
| 1456 | 1468 |
tcg_gen_shri_i32(r_tmp1, r_tmp1, uimm); |
| 1457 | 1469 |
tcg_gen_or_i32(r_tmp1, r_tmp1, r_tmp2); |
| 1458 |
tcg_gen_ext_i32_tl(cpu_T[0], r_tmp1);
|
|
| 1470 |
tcg_gen_ext_i32_tl(t0, r_tmp1);
|
|
| 1459 | 1471 |
tcg_temp_free(r_tmp1); |
| 1460 | 1472 |
tcg_temp_free(r_tmp2); |
| 1461 | 1473 |
} |
| 1462 | 1474 |
opn = "rotr"; |
| 1463 | 1475 |
} else {
|
| 1464 |
tcg_gen_ext32u_tl(cpu_T[0], cpu_T[0]);
|
|
| 1465 |
tcg_gen_shri_tl(cpu_T[0], cpu_T[0], uimm);
|
|
| 1466 |
tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
|
|
| 1476 |
tcg_gen_ext32u_tl(t0, t0);
|
|
| 1477 |
tcg_gen_shri_tl(t0, t0, uimm);
|
|
| 1478 |
tcg_gen_ext32s_tl(t0, t0);
|
|
| 1467 | 1479 |
opn = "srl"; |
| 1468 | 1480 |
} |
| 1469 | 1481 |
break; |
| ... | ... | |
| 1475 | 1487 |
break; |
| 1476 | 1488 |
#if defined(TARGET_MIPS64) |
| 1477 | 1489 |
case OPC_DSLL: |
| 1478 |
tcg_gen_shli_tl(cpu_T[0], cpu_T[0], uimm);
|
|
| 1490 |
tcg_gen_shli_tl(t0, t0, uimm);
|
|
| 1479 | 1491 |
opn = "dsll"; |
| 1480 | 1492 |
break; |
| 1481 | 1493 |
case OPC_DSRA: |
| 1482 |
tcg_gen_sari_tl(cpu_T[0], cpu_T[0], uimm);
|
|
| 1494 |
tcg_gen_sari_tl(t0, t0, uimm);
|
|
| 1483 | 1495 |
opn = "dsra"; |
| 1484 | 1496 |
break; |
| 1485 | 1497 |
case OPC_DSRL: |
| 1486 | 1498 |
switch ((ctx->opcode >> 21) & 0x1f) {
|
| 1487 | 1499 |
case 0: |
| 1488 |
tcg_gen_shri_tl(cpu_T[0], cpu_T[0], uimm);
|
|
| 1500 |
tcg_gen_shri_tl(t0, t0, uimm);
|
|
| 1489 | 1501 |
opn = "dsrl"; |
| 1490 | 1502 |
break; |
| 1491 | 1503 |
case 1: |
| ... | ... | |
| 1496 | 1508 |
|
| 1497 | 1509 |
tcg_gen_movi_tl(r_tmp1, 0x40); |
| 1498 | 1510 |
tcg_gen_subi_tl(r_tmp1, r_tmp1, uimm); |
| 1499 |
tcg_gen_shl_tl(r_tmp1, cpu_T[0], r_tmp1);
|
|
| 1500 |
tcg_gen_shri_tl(cpu_T[0], cpu_T[0], uimm);
|
|
| 1501 |
tcg_gen_or_tl(cpu_T[0], cpu_T[0], r_tmp1);
|
|
| 1511 |
tcg_gen_shl_tl(r_tmp1, t0, r_tmp1);
|
|
| 1512 |
tcg_gen_shri_tl(t0, t0, uimm);
|
|
| 1513 |
tcg_gen_or_tl(t0, t0, r_tmp1);
|
|
| 1502 | 1514 |
tcg_temp_free(r_tmp1); |
| 1503 | 1515 |
} |
| 1504 | 1516 |
opn = "drotr"; |
| 1505 | 1517 |
} else {
|
| 1506 |
tcg_gen_shri_tl(cpu_T[0], cpu_T[0], uimm);
|
|
| 1518 |
tcg_gen_shri_tl(t0, t0, uimm);
|
|
| 1507 | 1519 |
opn = "dsrl"; |
| 1508 | 1520 |
} |
| 1509 | 1521 |
break; |
| ... | ... | |
| 1514 | 1526 |
} |
| 1515 | 1527 |
break; |
| 1516 | 1528 |
case OPC_DSLL32: |
| 1517 |
tcg_gen_shli_tl(cpu_T[0], cpu_T[0], uimm + 32);
|
|
| 1529 |
tcg_gen_shli_tl(t0, t0, uimm + 32);
|
|
| 1518 | 1530 |
opn = "dsll32"; |
| 1519 | 1531 |
break; |
| 1520 | 1532 |
case OPC_DSRA32: |
| 1521 |
tcg_gen_sari_tl(cpu_T[0], cpu_T[0], uimm + 32);
|
|
| 1533 |
tcg_gen_sari_tl(t0, t0, uimm + 32);
|
|
| 1522 | 1534 |
opn = "dsra32"; |
| 1523 | 1535 |
break; |
| 1524 | 1536 |
case OPC_DSRL32: |
| 1525 | 1537 |
switch ((ctx->opcode >> 21) & 0x1f) {
|
| 1526 | 1538 |
case 0: |
| 1527 |
tcg_gen_shri_tl(cpu_T[0], cpu_T[0], uimm + 32);
|
|
| 1539 |
tcg_gen_shri_tl(t0, t0, uimm + 32);
|
|
| 1528 | 1540 |
opn = "dsrl32"; |
| 1529 | 1541 |
break; |
| 1530 | 1542 |
case 1: |
| ... | ... | |
| 1537 | 1549 |
tcg_gen_movi_tl(r_tmp2, 32); |
| 1538 | 1550 |
tcg_gen_addi_tl(r_tmp2, r_tmp2, uimm); |
| 1539 | 1551 |
tcg_gen_sub_tl(r_tmp1, r_tmp1, r_tmp2); |
| 1540 |
tcg_gen_shl_tl(r_tmp1, cpu_T[0], r_tmp1);
|
|
| 1541 |
tcg_gen_shr_tl(cpu_T[0], cpu_T[0], r_tmp2);
|
|
| 1542 |
tcg_gen_or_tl(cpu_T[0], cpu_T[0], r_tmp1);
|
|
| 1552 |
tcg_gen_shl_tl(r_tmp1, t0, r_tmp1);
|
|
| 1553 |
tcg_gen_shr_tl(t0, t0, r_tmp2);
|
|
| 1554 |
tcg_gen_or_tl(t0, t0, r_tmp1);
|
|
| 1543 | 1555 |
tcg_temp_free(r_tmp1); |
| 1544 | 1556 |
tcg_temp_free(r_tmp2); |
| 1545 | 1557 |
opn = "drotr32"; |
| 1546 | 1558 |
} else {
|
| 1547 |
tcg_gen_shri_tl(cpu_T[0], cpu_T[0], uimm + 32);
|
|
| 1559 |
tcg_gen_shri_tl(t0, t0, uimm + 32);
|
|
| 1548 | 1560 |
opn = "dsrl32"; |
| 1549 | 1561 |
} |
| 1550 | 1562 |
break; |
| ... | ... | |
| 1558 | 1570 |
default: |
| 1559 | 1571 |
MIPS_INVAL(opn); |
| 1560 | 1572 |
generate_exception(ctx, EXCP_RI); |
| 1561 |
return;
|
|
| 1573 |
goto out;
|
|
| 1562 | 1574 |
} |
| 1563 |
gen_store_gpr(cpu_T[0], rt);
|
|
| 1575 |
gen_store_gpr(t0, rt);
|
|
| 1564 | 1576 |
MIPS_DEBUG("%s %s, %s, " TARGET_FMT_lx, opn, regnames[rt], regnames[rs], uimm);
|
| 1577 |
out: |
|
| 1578 |
tcg_temp_free(t0); |
|
| 1565 | 1579 |
} |
| 1566 | 1580 |
|
| 1567 | 1581 |
/* Arithmetic */ |
| ... | ... | |
| 1569 | 1583 |
int rd, int rs, int rt) |
| 1570 | 1584 |
{
|
| 1571 | 1585 |
const char *opn = "arith"; |
| 1586 |
TCGv t0 = tcg_temp_local_new(TCG_TYPE_TL); |
|
| 1587 |
TCGv t1 = tcg_temp_local_new(TCG_TYPE_TL); |
|
| 1572 | 1588 |
|
| 1573 | 1589 |
if (rd == 0 && opc != OPC_ADD && opc != OPC_SUB |
| 1574 | 1590 |
&& opc != OPC_DADD && opc != OPC_DSUB) {
|
| 1575 | 1591 |
/* If no destination, treat it as a NOP. |
| 1576 | 1592 |
For add & sub, we must generate the overflow exception when needed. */ |
| 1577 | 1593 |
MIPS_DEBUG("NOP");
|
| 1578 |
return;
|
|
| 1594 |
goto out;
|
|
| 1579 | 1595 |
} |
| 1580 |
gen_load_gpr(cpu_T[0], rs);
|
|
| 1596 |
gen_load_gpr(t0, rs);
|
|
| 1581 | 1597 |
/* Specialcase the conventional move operation. */ |
| 1582 | 1598 |
if (rt == 0 && (opc == OPC_ADDU || opc == OPC_DADDU |
| 1583 | 1599 |
|| opc == OPC_SUBU || opc == OPC_DSUBU)) {
|
| 1584 |
gen_store_gpr(cpu_T[0], rd);
|
|
| 1585 |
return;
|
|
| 1600 |
gen_store_gpr(t0, rd);
|
|
| 1601 |
goto out;
|
|
| 1586 | 1602 |
} |
| 1587 |
gen_load_gpr(cpu_T[1], rt);
|
|
| 1603 |
gen_load_gpr(t1, rt);
|
|
| 1588 | 1604 |
switch (opc) {
|
| 1589 | 1605 |
case OPC_ADD: |
| 1590 | 1606 |
{
|
| ... | ... | |
| 1593 | 1609 |
int l1 = gen_new_label(); |
| 1594 | 1610 |
|
| 1595 | 1611 |
save_cpu_state(ctx, 1); |
| 1596 |
tcg_gen_ext32s_tl(r_tmp1, cpu_T[0]);
|
|
| 1597 |
tcg_gen_ext32s_tl(r_tmp2, cpu_T[1]);
|
|
| 1598 |
tcg_gen_add_tl(cpu_T[0], r_tmp1, r_tmp2);
|
|
| 1612 |
tcg_gen_ext32s_tl(r_tmp1, t0);
|
|
| 1613 |
tcg_gen_ext32s_tl(r_tmp2, t1);
|
|
| 1614 |
tcg_gen_add_tl(t0, r_tmp1, r_tmp2);
|
|
| 1599 | 1615 |
|
| 1600 |
tcg_gen_xor_tl(r_tmp1, r_tmp1, cpu_T[1]);
|
|
| 1616 |
tcg_gen_xor_tl(r_tmp1, r_tmp1, t1);
|
|
| 1601 | 1617 |
tcg_gen_xori_tl(r_tmp1, r_tmp1, -1); |
| 1602 |
tcg_gen_xor_tl(r_tmp2, cpu_T[0], cpu_T[1]);
|
|
| 1618 |
tcg_gen_xor_tl(r_tmp2, t0, t1);
|
|
| 1603 | 1619 |
tcg_gen_and_tl(r_tmp1, r_tmp1, r_tmp2); |
| 1604 | 1620 |
tcg_temp_free(r_tmp2); |
| 1605 | 1621 |
tcg_gen_shri_tl(r_tmp1, r_tmp1, 31); |
| ... | ... | |
| 1609 | 1625 |
generate_exception(ctx, EXCP_OVERFLOW); |
| 1610 | 1626 |
gen_set_label(l1); |
| 1611 | 1627 |
|
| 1612 |
tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
|
|
| 1628 |
tcg_gen_ext32s_tl(t0, t0);
|
|
| 1613 | 1629 |
} |
| 1614 | 1630 |
opn = "add"; |
| 1615 | 1631 |
break; |
| 1616 | 1632 |
case OPC_ADDU: |
| 1617 |
tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
|
|
| 1618 |
tcg_gen_ext32s_tl(cpu_T[1], cpu_T[1]);
|
|
| 1619 |
tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
|
|
| 1620 |
tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
|
|
| 1633 |
tcg_gen_ext32s_tl(t0, t0);
|
|
| 1634 |
tcg_gen_ext32s_tl(t1, t1);
|
|
| 1635 |
tcg_gen_add_tl(t0, t0, t1);
|
|
| 1636 |
tcg_gen_ext32s_tl(t0, t0);
|
|
| 1621 | 1637 |
opn = "addu"; |
| 1622 | 1638 |
break; |
| 1623 | 1639 |
case OPC_SUB: |
| ... | ... | |
| 1627 | 1643 |
int l1 = gen_new_label(); |
| 1628 | 1644 |
|
| 1629 | 1645 |
save_cpu_state(ctx, 1); |
| 1630 |
tcg_gen_ext32s_tl(r_tmp1, cpu_T[0]);
|
|
| 1631 |
tcg_gen_ext32s_tl(r_tmp2, cpu_T[1]);
|
|
| 1632 |
tcg_gen_sub_tl(cpu_T[0], r_tmp1, r_tmp2);
|
|
| 1646 |
tcg_gen_ext32s_tl(r_tmp1, t0);
|
|
| 1647 |
tcg_gen_ext32s_tl(r_tmp2, t1);
|
|
| 1648 |
tcg_gen_sub_tl(t0, r_tmp1, r_tmp2);
|
|
| 1633 | 1649 |
|
| 1634 |
tcg_gen_xor_tl(r_tmp2, r_tmp1, cpu_T[1]);
|
|
| 1635 |
tcg_gen_xor_tl(r_tmp1, r_tmp1, cpu_T[0]);
|
|
| 1650 |
tcg_gen_xor_tl(r_tmp2, r_tmp1, t1);
|
|
| 1651 |
tcg_gen_xor_tl(r_tmp1, r_tmp1, t0);
|
|
| 1636 | 1652 |
tcg_gen_and_tl(r_tmp1, r_tmp1, r_tmp2); |
| 1637 | 1653 |
tcg_temp_free(r_tmp2); |
| 1638 | 1654 |
tcg_gen_shri_tl(r_tmp1, r_tmp1, 31); |
| ... | ... | |
| 1642 | 1658 |
generate_exception(ctx, EXCP_OVERFLOW); |
| 1643 | 1659 |
gen_set_label(l1); |
| 1644 | 1660 |
|
| 1645 |
tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
|
|
| 1661 |
tcg_gen_ext32s_tl(t0, t0);
|
|
| 1646 | 1662 |
} |
| 1647 | 1663 |
opn = "sub"; |
| 1648 | 1664 |
break; |
| 1649 | 1665 |
case OPC_SUBU: |
| 1650 |
tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
|
|
| 1651 |
tcg_gen_ext32s_tl(cpu_T[1], cpu_T[1]);
|
|
| 1652 |
tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
|
|
| 1653 |
tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
|
|
| 1666 |
tcg_gen_ext32s_tl(t0, t0);
|
|
| 1667 |
tcg_gen_ext32s_tl(t1, t1);
|
|
| 1668 |
tcg_gen_sub_tl(t0, t0, t1);
|
|
| 1669 |
tcg_gen_ext32s_tl(t0, t0);
|
|
| 1654 | 1670 |
opn = "subu"; |
| 1655 | 1671 |
break; |
| 1656 | 1672 |
#if defined(TARGET_MIPS64) |
| ... | ... | |
| 1661 | 1677 |
int l1 = gen_new_label(); |
| 1662 | 1678 |
|
| 1663 | 1679 |
save_cpu_state(ctx, 1); |
| 1664 |
tcg_gen_mov_tl(r_tmp1, cpu_T[0]);
|
|
| 1665 |
tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
|
|
| 1680 |
tcg_gen_mov_tl(r_tmp1, t0);
|
|
| 1681 |
tcg_gen_add_tl(t0, t0, t1);
|
|
| 1666 | 1682 |
|
| 1667 |
tcg_gen_xor_tl(r_tmp1, r_tmp1, cpu_T[1]);
|
|
| 1683 |
tcg_gen_xor_tl(r_tmp1, r_tmp1, t1);
|
|
| 1668 | 1684 |
tcg_gen_xori_tl(r_tmp1, r_tmp1, -1); |
| 1669 |
tcg_gen_xor_tl(r_tmp2, cpu_T[0], cpu_T[1]);
|
|
| 1685 |
tcg_gen_xor_tl(r_tmp2, t0, t1);
|
|
| 1670 | 1686 |
tcg_gen_and_tl(r_tmp1, r_tmp1, r_tmp2); |
| 1671 | 1687 |
tcg_temp_free(r_tmp2); |
| 1672 | 1688 |
tcg_gen_shri_tl(r_tmp1, r_tmp1, 63); |
| ... | ... | |
| 1679 | 1695 |
opn = "dadd"; |
| 1680 | 1696 |
break; |
| 1681 | 1697 |
case OPC_DADDU: |
| 1682 |
tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
|
|
| 1698 |
tcg_gen_add_tl(t0, t0, t1);
|
|
| 1683 | 1699 |
opn = "daddu"; |
| 1684 | 1700 |
break; |
| 1685 | 1701 |
case OPC_DSUB: |
| ... | ... | |
| 1689 | 1705 |
int l1 = gen_new_label(); |
| 1690 | 1706 |
|
| 1691 | 1707 |
save_cpu_state(ctx, 1); |
| 1692 |
tcg_gen_mov_tl(r_tmp1, cpu_T[0]);
|
|
| 1693 |
tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
|
|
| 1708 |
tcg_gen_mov_tl(r_tmp1, t0);
|
|
| 1709 |
tcg_gen_sub_tl(t0, t0, t1);
|
|
| 1694 | 1710 |
|
| 1695 |
tcg_gen_xor_tl(r_tmp2, r_tmp1, cpu_T[1]);
|
|
| 1696 |
tcg_gen_xor_tl(r_tmp1, r_tmp1, cpu_T[0]);
|
|
| 1711 |
tcg_gen_xor_tl(r_tmp2, r_tmp1, t1);
|
|
| 1712 |
tcg_gen_xor_tl(r_tmp1, r_tmp1, t0);
|
|
| 1697 | 1713 |
tcg_gen_and_tl(r_tmp1, r_tmp1, r_tmp2); |
| 1698 | 1714 |
tcg_temp_free(r_tmp2); |
| 1699 | 1715 |
tcg_gen_shri_tl(r_tmp1, r_tmp1, 63); |
| ... | ... | |
| 1706 | 1722 |
opn = "dsub"; |
| 1707 | 1723 |
break; |
| 1708 | 1724 |
case OPC_DSUBU: |
| 1709 |
tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
|
|
| 1725 |
tcg_gen_sub_tl(t0, t0, t1);
|
|
| 1710 | 1726 |
opn = "dsubu"; |
| 1711 | 1727 |
break; |
| 1712 | 1728 |
#endif |
| 1713 | 1729 |
case OPC_SLT: |
| 1714 |
gen_op_lt(cpu_T[0], cpu_T[1]);
|
|
| 1730 |
gen_op_lt(t0, t1);
|
|
| 1715 | 1731 |
opn = "slt"; |
| 1716 | 1732 |
break; |
| 1717 | 1733 |
case OPC_SLTU: |
| 1718 |
gen_op_ltu(cpu_T[0], cpu_T[1]);
|
|
| 1734 |
gen_op_ltu(t0, t1);
|
|
| 1719 | 1735 |
opn = "sltu"; |
| 1720 | 1736 |
break; |
| 1721 | 1737 |
case OPC_AND: |
| 1722 |
tcg_gen_and_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
|
|
| 1738 |
tcg_gen_and_tl(t0, t0, t1);
|
|
| 1723 | 1739 |
opn = "and"; |
| 1724 | 1740 |
break; |
| 1725 | 1741 |
case OPC_NOR: |
| 1726 |
tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
|
|
| 1727 |
tcg_gen_not_tl(cpu_T[0], cpu_T[0]);
|
|
| 1742 |
tcg_gen_or_tl(t0, t0, t1);
|
|
| 1743 |
tcg_gen_not_tl(t0, t0);
|
|
| 1728 | 1744 |
opn = "nor"; |
| 1729 | 1745 |
break; |
| 1730 | 1746 |
case OPC_OR: |
| 1731 |
tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
|
|
| 1747 |
tcg_gen_or_tl(t0, t0, t1);
|
|
| 1732 | 1748 |
opn = "or"; |
| 1733 | 1749 |
break; |
| 1734 | 1750 |
case OPC_XOR: |
| 1735 |
tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
|
|
| 1751 |
tcg_gen_xor_tl(t0, t0, t1);
|
|
| 1736 | 1752 |
opn = "xor"; |
| 1737 | 1753 |
break; |
| 1738 | 1754 |
case OPC_MUL: |
| 1739 |
tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
|
|
| 1740 |
tcg_gen_ext32s_tl(cpu_T[1], cpu_T[1]);
|
|
| 1741 |
tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
|
|
| 1742 |
tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
|
|
| 1755 |
tcg_gen_ext32s_tl(t0, t0);
|
|
| 1756 |
tcg_gen_ext32s_tl(t1, t1);
|
|
| 1757 |
tcg_gen_mul_tl(t0, t0, t1);
|
|
| 1758 |
tcg_gen_ext32s_tl(t0, t0);
|
|
| 1743 | 1759 |
opn = "mul"; |
| 1744 | 1760 |
break; |
| 1745 | 1761 |
case OPC_MOVN: |
| 1746 | 1762 |
{
|
| 1747 | 1763 |
int l1 = gen_new_label(); |
| 1748 | 1764 |
|
| 1749 |
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_T[1], 0, l1);
|
|
| 1750 |
gen_store_gpr(cpu_T[0], rd);
|
|
| 1765 |
tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
|
|
| 1766 |
gen_store_gpr(t0, rd);
|
|
| 1751 | 1767 |
gen_set_label(l1); |
| 1752 | 1768 |
} |
| 1753 | 1769 |
opn = "movn"; |
| ... | ... | |
| 1756 | 1772 |
{
|
| 1757 | 1773 |
int l1 = gen_new_label(); |
| 1758 | 1774 |
|
| 1759 |
tcg_gen_brcondi_tl(TCG_COND_NE, cpu_T[1], 0, l1);
|
|
| 1760 |
gen_store_gpr(cpu_T[0], rd);
|
|
| 1775 |
tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1);
|
|
| 1776 |
gen_store_gpr(t0, rd);
|
|
| 1761 | 1777 |
gen_set_label(l1); |
| 1762 | 1778 |
} |
| 1763 | 1779 |
opn = "movz"; |
| 1764 | 1780 |
goto print; |
| 1765 | 1781 |
case OPC_SLLV: |
| 1766 |
tcg_gen_ext32u_tl(cpu_T[0], cpu_T[0]);
|
|
| 1767 |
tcg_gen_ext32u_tl(cpu_T[1], cpu_T[1]);
|
|
| 1768 |
tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0x1f);
|
|
| 1769 |
tcg_gen_shl_tl(cpu_T[0], cpu_T[1], cpu_T[0]);
|
|
| 1770 |
tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
|
|
| 1782 |
tcg_gen_ext32u_tl(t0, t0);
|
|
| 1783 |
tcg_gen_ext32u_tl(t1, t1);
|
|
| 1784 |
tcg_gen_andi_tl(t0, t0, 0x1f);
|
|
| 1785 |
tcg_gen_shl_tl(t0, t1, t0);
|
|
| 1786 |
tcg_gen_ext32s_tl(t0, t0);
|
|
| 1771 | 1787 |
opn = "sllv"; |
| 1772 | 1788 |
break; |
| 1773 | 1789 |
case OPC_SRAV: |
| 1774 |
tcg_gen_ext32s_tl(cpu_T[1], cpu_T[1]);
|
|
| 1775 |
tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0x1f);
|
|
| 1776 |
tcg_gen_sar_tl(cpu_T[0], cpu_T[1], cpu_T[0]);
|
|
| 1777 |
tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
|
|
| 1790 |
tcg_gen_ext32s_tl(t1, t1);
|
|
| 1791 |
tcg_gen_andi_tl(t0, t0, 0x1f);
|
|
| 1792 |
tcg_gen_sar_tl(t0, t1, t0);
|
|
| 1793 |
tcg_gen_ext32s_tl(t0, t0);
|
|
| 1778 | 1794 |
opn = "srav"; |
| 1779 | 1795 |
break; |
| 1780 | 1796 |
case OPC_SRLV: |
| 1781 | 1797 |
switch ((ctx->opcode >> 6) & 0x1f) {
|
| 1782 | 1798 |
case 0: |
| 1783 |
tcg_gen_ext32u_tl(cpu_T[1], cpu_T[1]);
|
|
| 1784 |
tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0x1f);
|
|
| 1785 |
tcg_gen_shr_tl(cpu_T[0], cpu_T[1], cpu_T[0]);
|
|
| 1786 |
tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
|
|
| 1799 |
tcg_gen_ext32u_tl(t1, t1);
|
|
| 1800 |
tcg_gen_andi_tl(t0, t0, 0x1f);
|
|
| 1801 |
tcg_gen_shr_tl(t0, t1, t0);
|
|
| 1802 |
tcg_gen_ext32s_tl(t0, t0);
|
|
| 1787 | 1803 |
opn = "srlv"; |
| 1788 | 1804 |
break; |
| 1789 | 1805 |
case 1: |
| ... | ... | |
| 1792 | 1808 |
int l1 = gen_new_label(); |
| 1793 | 1809 |
int l2 = gen_new_label(); |
| 1794 | 1810 |
|
| 1795 |
tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0x1f);
|
|
| 1796 |
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_T[0], 0, l1);
|
|
| 1811 |
tcg_gen_andi_tl(t0, t0, 0x1f);
|
|
| 1812 |
tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
|
|
| 1797 | 1813 |
{
|
| 1798 | 1814 |
TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_I32); |
| 1799 | 1815 |
TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_I32); |
| 1800 | 1816 |
TCGv r_tmp3 = tcg_temp_new(TCG_TYPE_I32); |
| 1801 | 1817 |
|
| 1802 |
tcg_gen_trunc_tl_i32(r_tmp1, cpu_T[0]);
|
|
| 1803 |
tcg_gen_trunc_tl_i32(r_tmp2, cpu_T[1]);
|
|
| 1818 |
tcg_gen_trunc_tl_i32(r_tmp1, t0);
|
|
| 1819 |
tcg_gen_trunc_tl_i32(r_tmp2, t1);
|
|
| 1804 | 1820 |
tcg_gen_movi_i32(r_tmp3, 0x20); |
| 1805 | 1821 |
tcg_gen_sub_i32(r_tmp3, r_tmp3, r_tmp1); |
| 1806 | 1822 |
tcg_gen_shl_i32(r_tmp3, r_tmp2, r_tmp3); |
| 1807 | 1823 |
tcg_gen_shr_i32(r_tmp1, r_tmp2, r_tmp1); |
| 1808 | 1824 |
tcg_gen_or_i32(r_tmp1, r_tmp1, r_tmp3); |
| 1809 |
tcg_gen_ext_i32_tl(cpu_T[0], r_tmp1);
|
|
| 1825 |
tcg_gen_ext_i32_tl(t0, r_tmp1);
|
|
| 1810 | 1826 |
tcg_temp_free(r_tmp1); |
| 1811 | 1827 |
tcg_temp_free(r_tmp2); |
| 1812 | 1828 |
tcg_temp_free(r_tmp3); |
| 1813 | 1829 |
tcg_gen_br(l2); |
| 1814 | 1830 |
} |
| 1815 | 1831 |
gen_set_label(l1); |
| 1816 |
tcg_gen_mov_tl(cpu_T[0], cpu_T[1]);
|
|
| 1832 |
tcg_gen_mov_tl(t0, t1);
|
|
| 1817 | 1833 |
gen_set_label(l2); |
| 1818 | 1834 |
opn = "rotrv"; |
| 1819 | 1835 |
} else {
|
| 1820 |
tcg_gen_ext32u_tl(cpu_T[1], cpu_T[1]);
|
|
| 1821 |
tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0x1f);
|
|
| 1822 |
tcg_gen_shr_tl(cpu_T[0], cpu_T[1], cpu_T[0]);
|
|
| 1823 |
tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
|
|
| 1836 |
tcg_gen_ext32u_tl(t1, t1);
|
|
| 1837 |
tcg_gen_andi_tl(t0, t0, 0x1f);
|
|
| 1838 |
tcg_gen_shr_tl(t0, t1, t0);
|
|
| 1839 |
tcg_gen_ext32s_tl(t0, t0);
|
|
| 1824 | 1840 |
opn = "srlv"; |
| 1825 | 1841 |
} |
| 1826 | 1842 |
break; |
| ... | ... | |
| 1832 | 1848 |
break; |
| 1833 | 1849 |
#if defined(TARGET_MIPS64) |
| 1834 | 1850 |
case OPC_DSLLV: |
| 1835 |
tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0x3f);
|
|
| 1836 |
tcg_gen_shl_tl(cpu_T[0], cpu_T[1], cpu_T[0]);
|
|
| 1851 |
tcg_gen_andi_tl(t0, t0, 0x3f);
|
|
| 1852 |
tcg_gen_shl_tl(t0, t1, t0);
|
|
| 1837 | 1853 |
opn = "dsllv"; |
| 1838 | 1854 |
break; |
| 1839 | 1855 |
case OPC_DSRAV: |
| 1840 |
tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0x3f);
|
|
| 1841 |
tcg_gen_sar_tl(cpu_T[0], cpu_T[1], cpu_T[0]);
|
|
| 1856 |
tcg_gen_andi_tl(t0, t0, 0x3f);
|
|
| 1857 |
tcg_gen_sar_tl(t0, t1, t0);
|
|
| 1842 | 1858 |
opn = "dsrav"; |
| 1843 | 1859 |
break; |
| 1844 | 1860 |
case OPC_DSRLV: |
| 1845 | 1861 |
switch ((ctx->opcode >> 6) & 0x1f) {
|
| 1846 | 1862 |
case 0: |
| 1847 |
tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0x3f);
|
|
| 1848 |
tcg_gen_shr_tl(cpu_T[0], cpu_T[1], cpu_T[0]);
|
|
| 1863 |
tcg_gen_andi_tl(t0, t0, 0x3f);
|
|
| 1864 |
tcg_gen_shr_tl(t0, t1, t0);
|
|
| 1849 | 1865 |
opn = "dsrlv"; |
| 1850 | 1866 |
break; |
| 1851 | 1867 |
case 1: |
| ... | ... | |
| 1854 | 1870 |
int l1 = gen_new_label(); |
| 1855 | 1871 |
int l2 = gen_new_label(); |
| 1856 | 1872 |
|
| 1857 |
tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0x3f);
|
|
| 1858 |
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_T[0], 0, l1);
|
|
| 1873 |
tcg_gen_andi_tl(t0, t0, 0x3f);
|
|
| 1874 |
tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
|
|
| 1859 | 1875 |
{
|
| 1860 | 1876 |
TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_TL); |
| 1861 | 1877 |
|
| 1862 | 1878 |
tcg_gen_movi_tl(r_tmp1, 0x40); |
| 1863 |
tcg_gen_sub_tl(r_tmp1, r_tmp1, cpu_T[0]);
|
|
| 1864 |
tcg_gen_shl_tl(r_tmp1, cpu_T[1], r_tmp1);
|
|
| 1865 |
tcg_gen_shr_tl(cpu_T[0], cpu_T[1], cpu_T[0]);
|
|
| 1866 |
tcg_gen_or_tl(cpu_T[0], cpu_T[0], r_tmp1);
|
|
| 1879 |
tcg_gen_sub_tl(r_tmp1, r_tmp1, t0);
|
|
| 1880 |
tcg_gen_shl_tl(r_tmp1, t1, r_tmp1);
|
|
| 1881 |
tcg_gen_shr_tl(t0, t1, t0);
|
|
| 1882 |
tcg_gen_or_tl(t0, t0, r_tmp1);
|
|
| 1867 | 1883 |
tcg_temp_free(r_tmp1); |
| 1868 | 1884 |
tcg_gen_br(l2); |
| 1869 | 1885 |
} |
| 1870 | 1886 |
gen_set_label(l1); |
| 1871 |
tcg_gen_mov_tl(cpu_T[0], cpu_T[1]);
|
|
| 1887 |
tcg_gen_mov_tl(t0, t1);
|
|
| 1872 | 1888 |
gen_set_label(l2); |
| 1873 | 1889 |
opn = "drotrv"; |
| 1874 | 1890 |
} else {
|
| 1875 |
tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0x3f);
|
|
| 1876 |
tcg_gen_shr_tl(cpu_T[0], cpu_T[1], cpu_T[0]);
|
|
| 1891 |
tcg_gen_andi_tl(t0, t0, 0x3f);
|
|
| 1892 |
tcg_gen_shr_tl(t0, t1, t0);
|
|
| 1877 | 1893 |
opn = "dsrlv"; |
| 1878 | 1894 |
} |
| 1879 | 1895 |
break; |
| ... | ... | |
| 1887 | 1903 |
default: |
| 1888 | 1904 |
MIPS_INVAL(opn); |
| 1889 | 1905 |
generate_exception(ctx, EXCP_RI); |
| 1890 |
return;
|
|
| 1906 |
goto out;
|
|
| 1891 | 1907 |
} |
| 1892 |
gen_store_gpr(cpu_T[0], rd);
|
|
| 1908 |
gen_store_gpr(t0, rd);
|
|
| 1893 | 1909 |
print: |
| 1894 | 1910 |
MIPS_DEBUG("%s %s, %s, %s", opn, regnames[rd], regnames[rs], regnames[rt]);
|
| 1911 |
out: |
|
| 1912 |
tcg_temp_free(t0); |
|
| 1913 |
tcg_temp_free(t1); |
|
| 1895 | 1914 |
} |
| 1896 | 1915 |
|
| 1897 | 1916 |
/* Arithmetic on HI/LO registers */ |
| 1898 | 1917 |
static void gen_HILO (DisasContext *ctx, uint32_t opc, int reg) |
| 1899 | 1918 |
{
|
| 1900 | 1919 |
const char *opn = "hilo"; |
| 1920 |
TCGv t0 = tcg_temp_local_new(TCG_TYPE_TL); |
|
| 1901 | 1921 |
|
| 1902 | 1922 |
if (reg == 0 && (opc == OPC_MFHI || opc == OPC_MFLO)) {
|
| 1903 | 1923 |
/* Treat as NOP. */ |
| 1904 | 1924 |
MIPS_DEBUG("NOP");
|
| 1905 |
return;
|
|
| 1925 |
goto out;
|
|
| 1906 | 1926 |
} |
| 1907 | 1927 |
switch (opc) {
|
| 1908 | 1928 |
case OPC_MFHI: |
| 1909 |
gen_load_HI(cpu_T[0], 0);
|
|
| 1910 |
gen_store_gpr(cpu_T[0], reg);
|
|
| 1929 |
gen_load_HI(t0, 0);
|
|
| 1930 |
gen_store_gpr(t0, reg);
|
|
| 1911 | 1931 |
opn = "mfhi"; |
| 1912 | 1932 |
break; |
| 1913 | 1933 |
case OPC_MFLO: |
| 1914 |
gen_load_LO(cpu_T[0], 0);
|
|
| 1915 |
gen_store_gpr(cpu_T[0], reg);
|
|
| 1934 |
gen_load_LO(t0, 0);
|
|
| 1935 |
gen_store_gpr(t0, reg);
|
|
| 1916 | 1936 |
opn = "mflo"; |
| 1917 | 1937 |
break; |
| 1918 | 1938 |
case OPC_MTHI: |
| 1919 |
gen_load_gpr(cpu_T[0], reg);
|
|
| 1920 |
gen_store_HI(cpu_T[0], 0);
|
|
| 1939 |
gen_load_gpr(t0, reg);
|
|
| 1940 |
gen_store_HI(t0, 0);
|
|
| 1921 | 1941 |
opn = "mthi"; |
| 1922 | 1942 |
break; |
| 1923 | 1943 |
case OPC_MTLO: |
| 1924 |
gen_load_gpr(cpu_T[0], reg);
|
|
| 1925 |
gen_store_LO(cpu_T[0], 0);
|
|
| 1944 |
gen_load_gpr(t0, reg);
|
|
| 1945 |
gen_store_LO(t0, 0);
|
|
| 1926 | 1946 |
opn = "mtlo"; |
| 1927 | 1947 |
break; |
| 1928 | 1948 |
default: |
| 1929 | 1949 |
MIPS_INVAL(opn); |
| 1930 | 1950 |
generate_exception(ctx, EXCP_RI); |
| 1931 |
return;
|
|
| 1951 |
goto out;
|
|
| 1932 | 1952 |
} |
| 1933 | 1953 |
MIPS_DEBUG("%s %s", opn, regnames[reg]);
|
| 1954 |
out: |
|
| 1955 |
tcg_temp_free(t0); |
|
| 1934 | 1956 |
} |
| 1935 | 1957 |
|
| 1936 | 1958 |
static void gen_muldiv (DisasContext *ctx, uint32_t opc, |
| 1937 | 1959 |
int rs, int rt) |
| 1938 | 1960 |
{
|
| 1939 | 1961 |
const char *opn = "mul/div"; |
| 1962 |
TCGv t0 = tcg_temp_local_new(TCG_TYPE_TL); |
|
| 1963 |
TCGv t1 = tcg_temp_local_new(TCG_TYPE_TL); |
|
| 1940 | 1964 |
|
| 1941 |
gen_load_gpr(cpu_T[0], rs);
|
|
| 1942 |
gen_load_gpr(cpu_T[1], rt);
|
|
| 1965 |
gen_load_gpr(t0, rs);
|
|
| 1966 |
gen_load_gpr(t1, rt);
|
|
| 1943 | 1967 |
switch (opc) {
|
| 1944 | 1968 |
case OPC_DIV: |
| 1945 | 1969 |
{
|
| 1946 | 1970 |
int l1 = gen_new_label(); |
| 1947 | 1971 |
|
| 1948 |
tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
|
|
| 1949 |
tcg_gen_ext32s_tl(cpu_T[1], cpu_T[1]);
|
|
| 1950 |
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_T[1], 0, l1);
|
|
| 1972 |
tcg_gen_ext32s_tl(t0, t0);
|
|
| 1973 |
tcg_gen_ext32s_tl(t1, t1);
|
|
| 1974 |
tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
|
|
| 1951 | 1975 |
{
|
| 1952 | 1976 |
TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_I64); |
| 1953 | 1977 |
TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_I64); |
| 1954 | 1978 |
TCGv r_tmp3 = tcg_temp_new(TCG_TYPE_I64); |
| 1955 | 1979 |
|
| 1956 |
tcg_gen_ext_tl_i64(r_tmp1, cpu_T[0]);
|
|
| 1957 |
tcg_gen_ext_tl_i64(r_tmp2, cpu_T[1]);
|
|
| 1980 |
tcg_gen_ext_tl_i64(r_tmp1, t0);
|
|
| 1981 |
tcg_gen_ext_tl_i64(r_tmp2, t1);
|
|
| 1958 | 1982 |
tcg_gen_div_i64(r_tmp3, r_tmp1, r_tmp2); |
| 1959 | 1983 |
tcg_gen_rem_i64(r_tmp2, r_tmp1, r_tmp2); |
| 1960 |
tcg_gen_trunc_i64_tl(cpu_T[0], r_tmp3);
|
|
| 1961 |
tcg_gen_trunc_i64_tl(cpu_T[1], r_tmp2);
|
|
| 1984 |
tcg_gen_trunc_i64_tl(t0, r_tmp3);
|
|
| 1985 |
tcg_gen_trunc_i64_tl(t1, r_tmp2);
|
|
| 1962 | 1986 |
tcg_temp_free(r_tmp1); |
| 1963 | 1987 |
tcg_temp_free(r_tmp2); |
| 1964 | 1988 |
tcg_temp_free(r_tmp3); |
| 1965 |
tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
|
|
| 1966 |
tcg_gen_ext32s_tl(cpu_T[1], cpu_T[1]);
|
|
| 1967 |
gen_store_LO(cpu_T[0], 0);
|
|
| 1968 |
gen_store_HI(cpu_T[1], 0);
|
|
| 1989 |
tcg_gen_ext32s_tl(t0, t0);
|
|
| 1990 |
tcg_gen_ext32s_tl(t1, t1);
|
|
| 1991 |
gen_store_LO(t0, 0);
|
|
| 1992 |
gen_store_HI(t1, 0);
|
|
| 1969 | 1993 |
} |
| 1970 | 1994 |
gen_set_label(l1); |
| 1971 | 1995 |
} |
| ... | ... | |
| 1975 | 1999 |
{
|
| 1976 | 2000 |
int l1 = gen_new_label(); |
| 1977 | 2001 |
|
| 1978 |
tcg_gen_ext32s_tl(cpu_T[1], cpu_T[1]);
|
|
| 1979 |
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_T[1], 0, l1);
|
|
| 2002 |
tcg_gen_ext32s_tl(t1, t1);
|
|
| 2003 |
tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
|
|
| 1980 | 2004 |
{
|
| 1981 | 2005 |
TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_I32); |
| 1982 | 2006 |
TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_I32); |
| 1983 | 2007 |
TCGv r_tmp3 = tcg_temp_new(TCG_TYPE_I32); |
| 1984 | 2008 |
|
| 1985 |
tcg_gen_trunc_tl_i32(r_tmp1, cpu_T[0]);
|
|
| 1986 |
tcg_gen_trunc_tl_i32(r_tmp2, cpu_T[1]);
|
|
| 2009 |
tcg_gen_trunc_tl_i32(r_tmp1, t0);
|
|
| 2010 |
tcg_gen_trunc_tl_i32(r_tmp2, t1);
|
|
| 1987 | 2011 |
tcg_gen_divu_i32(r_tmp3, r_tmp1, r_tmp2); |
| 1988 | 2012 |
tcg_gen_remu_i32(r_tmp1, r_tmp1, r_tmp2); |
| 1989 |
tcg_gen_ext_i32_tl(cpu_T[0], r_tmp3);
|
|
| 1990 |
tcg_gen_ext_i32_tl(cpu_T[1], r_tmp1);
|
|
| 2013 |
tcg_gen_ext_i32_tl(t0, r_tmp3);
|
|
| 2014 |
tcg_gen_ext_i32_tl(t1, r_tmp1);
|
|
| 1991 | 2015 |
tcg_temp_free(r_tmp1); |
| 1992 | 2016 |
tcg_temp_free(r_tmp2); |
| 1993 | 2017 |
tcg_temp_free(r_tmp3); |
| 1994 |
gen_store_LO(cpu_T[0], 0);
|
|
| 1995 |
gen_store_HI(cpu_T[1], 0);
|
|
| 2018 |
gen_store_LO(t0, 0);
|
|
| 2019 |
gen_store_HI(t1, 0);
|
|
| 1996 | 2020 |
} |
| 1997 | 2021 |
gen_set_label(l1); |
| 1998 | 2022 |
} |
| ... | ... | |
| 2003 | 2027 |
TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_I64); |
| 2004 | 2028 |
TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_I64); |
| 2005 | 2029 |
|
| 2006 |
tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
|
|
| 2007 |
tcg_gen_ext32s_tl(cpu_T[1], cpu_T[1]);
|
|
| 2008 |
tcg_gen_ext_tl_i64(r_tmp1, cpu_T[0]);
|
|
| 2009 |
tcg_gen_ext_tl_i64(r_tmp2, cpu_T[1]);
|
|
| 2030 |
tcg_gen_ext32s_tl(t0, t0);
|
|
| 2031 |
tcg_gen_ext32s_tl(t1, t1);
|
|
| 2032 |
tcg_gen_ext_tl_i64(r_tmp1, t0);
|
|
| 2033 |
tcg_gen_ext_tl_i64(r_tmp2, t1);
|
|
| 2010 | 2034 |
tcg_gen_mul_i64(r_tmp1, r_tmp1, r_tmp2); |
| 2011 | 2035 |
tcg_temp_free(r_tmp2); |
| 2012 |
tcg_gen_trunc_i64_tl(cpu_T[0], r_tmp1);
|
|
| 2036 |
tcg_gen_trunc_i64_tl(t0, r_tmp1);
|
|
| 2013 | 2037 |
tcg_gen_shri_i64(r_tmp1, r_tmp1, 32); |
| 2014 |
tcg_gen_trunc_i64_tl(cpu_T[1], r_tmp1);
|
|
| 2038 |
tcg_gen_trunc_i64_tl(t1, r_tmp1);
|
|
| 2015 | 2039 |
tcg_temp_free(r_tmp1); |
| 2016 |
tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
|
|
| 2017 |
tcg_gen_ext32s_tl(cpu_T[1], cpu_T[1]);
|
|
| 2018 |
gen_store_LO(cpu_T[0], 0);
|
|
| 2019 |
gen_store_HI(cpu_T[1], 0);
|
|
| 2040 |
tcg_gen_ext32s_tl(t0, t0);
|
|
| 2041 |
tcg_gen_ext32s_tl(t1, t1);
|
|
| 2042 |
gen_store_LO(t0, 0);
|
|
| 2043 |
gen_store_HI(t1, 0);
|
|
| 2020 | 2044 |
} |
| 2021 | 2045 |
opn = "mult"; |
| 2022 | 2046 |
break; |
| ... | ... | |
| 2025 | 2049 |
TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_I64); |
| 2026 | 2050 |
TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_I64); |
| 2027 | 2051 |
|
| 2028 |
tcg_gen_ext32u_tl(cpu_T[0], cpu_T[0]);
|
|
| 2029 |
tcg_gen_ext32u_tl(cpu_T[1], cpu_T[1]);
|
|
| 2030 |
tcg_gen_extu_tl_i64(r_tmp1, cpu_T[0]);
|
|
| 2031 |
tcg_gen_extu_tl_i64(r_tmp2, cpu_T[1]);
|
|
| 2052 |
tcg_gen_ext32u_tl(t0, t0);
|
|
| 2053 |
tcg_gen_ext32u_tl(t1, t1);
|
|
| 2054 |
tcg_gen_extu_tl_i64(r_tmp1, t0);
|
|
| 2055 |
tcg_gen_extu_tl_i64(r_tmp2, t1);
|
|
| 2032 | 2056 |
tcg_gen_mul_i64(r_tmp1, r_tmp1, r_tmp2); |
| 2033 | 2057 |
tcg_temp_free(r_tmp2); |
| 2034 |
tcg_gen_trunc_i64_tl(cpu_T[0], r_tmp1);
|
|
| 2058 |
tcg_gen_trunc_i64_tl(t0, r_tmp1);
|
|
| 2035 | 2059 |
tcg_gen_shri_i64(r_tmp1, r_tmp1, 32); |
| 2036 |
tcg_gen_trunc_i64_tl(cpu_T[1], r_tmp1);
|
|
| 2060 |
tcg_gen_trunc_i64_tl(t1, r_tmp1);
|
|
| 2037 | 2061 |
tcg_temp_free(r_tmp1); |
| 2038 |
tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
|
|
| 2039 |
tcg_gen_ext32s_tl(cpu_T[1], cpu_T[1]);
|
|
| 2040 |
gen_store_LO(cpu_T[0], 0);
|
|
| 2041 |
gen_store_HI(cpu_T[1], 0);
|
|
| 2062 |
tcg_gen_ext32s_tl(t0, t0);
|
|
| 2063 |
tcg_gen_ext32s_tl(t1, t1);
|
|
| 2064 |
gen_store_LO(t0, 0);
|
|
| 2065 |
gen_store_HI(t1, 0);
|
|
| 2042 | 2066 |
} |
| 2043 | 2067 |
opn = "multu"; |
| 2044 | 2068 |
break; |
| ... | ... | |
| 2047 | 2071 |
{
|
| 2048 | 2072 |
int l1 = gen_new_label(); |
| 2049 | 2073 |
|
| 2050 |
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_T[1], 0, l1);
|
|
| 2074 |
tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
|
|
| 2051 | 2075 |
{
|
| 2052 | 2076 |
int l2 = gen_new_label(); |
| 2053 | 2077 |
|
| 2054 |
tcg_gen_brcondi_tl(TCG_COND_NE, cpu_T[0], -1LL << 63, l2);
|
|
| 2055 |
tcg_gen_brcondi_tl(TCG_COND_NE, cpu_T[1], -1LL, l2);
|
|
| 2078 |
tcg_gen_brcondi_tl(TCG_COND_NE, t0, -1LL << 63, l2);
|
|
| 2079 |
tcg_gen_brcondi_tl(TCG_COND_NE, t1, -1LL, l2);
|
|
| 2056 | 2080 |
{
|
| 2057 |
tcg_gen_movi_tl(cpu_T[1], 0);
|
|
| 2058 |
gen_store_LO(cpu_T[0], 0);
|
|
| 2059 |
gen_store_HI(cpu_T[1], 0);
|
|
| 2081 |
tcg_gen_movi_tl(t1, 0);
|
|
| 2082 |
gen_store_LO(t0, 0);
|
|
| 2083 |
gen_store_HI(t1, 0);
|
|
| 2060 | 2084 |
tcg_gen_br(l1); |
| 2061 | 2085 |
} |
| 2062 | 2086 |
gen_set_label(l2); |
| ... | ... | |
| 2064 | 2088 |
TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_I64); |
| 2065 | 2089 |
TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_I64); |
| 2066 | 2090 |
|
| 2067 |
tcg_gen_div_i64(r_tmp1, cpu_T[0], cpu_T[1]);
|
|
| 2068 |
tcg_gen_rem_i64(r_tmp2, cpu_T[0], cpu_T[1]);
|
|
| 2091 |
tcg_gen_div_i64(r_tmp1, t0, t1);
|
|
| 2092 |
tcg_gen_rem_i64(r_tmp2, t0, t1);
|
|
| 2069 | 2093 |
gen_store_LO(r_tmp1, 0); |
| 2070 | 2094 |
gen_store_HI(r_tmp2, 0); |
| 2071 | 2095 |
tcg_temp_free(r_tmp1); |
| ... | ... | |
| 2080 | 2104 |
{
|
| 2081 | 2105 |
int l1 = gen_new_label(); |
| 2082 | 2106 |
|
| 2083 |
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_T[1], 0, l1);
|
|
| 2107 |
tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
|
|
| 2084 | 2108 |
{
|
| 2085 | 2109 |
TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_I64); |
| 2086 | 2110 |
TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_I64); |
| 2087 | 2111 |
|
| 2088 |
tcg_gen_divu_i64(r_tmp1, cpu_T[0], cpu_T[1]);
|
|
| 2089 |
tcg_gen_remu_i64(r_tmp2, cpu_T[0], cpu_T[1]);
|
|
| 2112 |
tcg_gen_divu_i64(r_tmp1, t0, t1);
|
|
| 2113 |
tcg_gen_remu_i64(r_tmp2, t0, t1);
|
|
| 2090 | 2114 |
tcg_temp_free(r_tmp1); |
| 2091 | 2115 |
tcg_temp_free(r_tmp2); |
| 2092 | 2116 |
gen_store_LO(r_tmp1, 0); |
| ... | ... | |
| 2097 | 2121 |
opn = "ddivu"; |
| 2098 | 2122 |
break; |
| 2099 | 2123 |
case OPC_DMULT: |
| 2100 |
tcg_gen_helper_0_2(do_dmult, cpu_T[0], cpu_T[1]);
|
|
| 2124 |
tcg_gen_helper_0_2(do_dmult, t0, t1);
|
|
| 2101 | 2125 |
opn = "dmult"; |
| 2102 | 2126 |
break; |
| 2103 | 2127 |
case OPC_DMULTU: |
| 2104 |
tcg_gen_helper_0_2(do_dmultu, cpu_T[0], cpu_T[1]);
|
|
| 2128 |
tcg_gen_helper_0_2(do_dmultu, t0, t1);
|
|
| 2105 | 2129 |
opn = "dmultu"; |
| 2106 | 2130 |
break; |
| 2107 | 2131 |
#endif |
| ... | ... | |
| 2111 | 2135 |
TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_I64); |
| 2112 | 2136 |
TCGv r_tmp3 = tcg_temp_new(TCG_TYPE_I64); |
| 2113 | 2137 |
|
| 2114 |
tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
|
|
| 2115 |
tcg_gen_ext32s_tl(cpu_T[1], cpu_T[1]);
|
|
| 2116 |
tcg_gen_ext_tl_i64(r_tmp1, cpu_T[0]);
|
|
| 2117 |
tcg_gen_ext_tl_i64(r_tmp2, cpu_T[1]);
|
|
| 2138 |
tcg_gen_ext32s_tl(t0, t0);
|
|
| 2139 |
tcg_gen_ext32s_tl(t1, t1);
|
|
| 2140 |
tcg_gen_ext_tl_i64(r_tmp1, t0);
|
|
| 2141 |
tcg_gen_ext_tl_i64(r_tmp2, t1);
|
|
| 2118 | 2142 |
tcg_gen_mul_i64(r_tmp1, r_tmp1, r_tmp2); |
| 2119 |
gen_load_LO(cpu_T[0], 0);
|
|
| 2120 |
gen_load_HI(cpu_T[1], 0);
|
|
| 2121 |
tcg_gen_extu_tl_i64(r_tmp2, cpu_T[0]);
|
|
| 2122 |
tcg_gen_extu_tl_i64(r_tmp3, cpu_T[1]);
|
|
| 2143 |
gen_load_LO(t0, 0);
|
|
| 2144 |
gen_load_HI(t1, 0);
|
|
| 2145 |
tcg_gen_extu_tl_i64(r_tmp2, t0);
|
|
| 2146 |
tcg_gen_extu_tl_i64(r_tmp3, t1);
|
|
| 2123 | 2147 |
tcg_gen_shli_i64(r_tmp3, r_tmp3, 32); |
| 2124 | 2148 |
tcg_gen_or_i64(r_tmp2, r_tmp2, r_tmp3); |
| 2125 | 2149 |
tcg_temp_free(r_tmp3); |
| 2126 | 2150 |
tcg_gen_add_i64(r_tmp1, r_tmp1, r_tmp2); |
| 2127 | 2151 |
tcg_temp_free(r_tmp2); |
| 2128 |
tcg_gen_trunc_i64_tl(cpu_T[0], r_tmp1);
|
|
| 2152 |
tcg_gen_trunc_i64_tl(t0, r_tmp1);
|
|
| 2129 | 2153 |
tcg_gen_shri_i64(r_tmp1, r_tmp1, 32); |
| 2130 |
tcg_gen_trunc_i64_tl(cpu_T[1], r_tmp1);
|
|
| 2154 |
tcg_gen_trunc_i64_tl(t1, r_tmp1);
|
|
| 2131 | 2155 |
tcg_temp_free(r_tmp1); |
| 2132 |
tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
|
|
| 2133 |
tcg_gen_ext32s_tl(cpu_T[1], cpu_T[1]);
|
|
| 2134 |
gen_store_LO(cpu_T[0], 0);
|
|
| 2135 |
gen_store_HI(cpu_T[1], 0);
|
|
| 2156 |
tcg_gen_ext32s_tl(t0, t0);
|
|
| 2157 |
tcg_gen_ext32s_tl(t1, t1);
|
|
| 2158 |
gen_store_LO(t0, 0);
|
|
| 2159 |
gen_store_HI(t1, 0);
|
|
| 2136 | 2160 |
} |
| 2137 | 2161 |
opn = "madd"; |
| 2138 | 2162 |
break; |
| ... | ... | |
| 2142 | 2166 |
TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_I64); |
| 2143 | 2167 |
TCGv r_tmp3 = tcg_temp_new(TCG_TYPE_I64); |
| 2144 | 2168 |
|
| 2145 |
tcg_gen_ext32u_tl(cpu_T[0], cpu_T[0]);
|
|
| 2146 |
tcg_gen_ext32u_tl(cpu_T[1], cpu_T[1]);
|
|
| 2147 |
tcg_gen_extu_tl_i64(r_tmp1, cpu_T[0]);
|
|
| 2148 |
tcg_gen_extu_tl_i64(r_tmp2, cpu_T[1]);
|
|
| 2169 |
tcg_gen_ext32u_tl(t0, t0);
|
|
| 2170 |
tcg_gen_ext32u_tl(t1, t1);
|
|
| 2171 |
tcg_gen_extu_tl_i64(r_tmp1, t0);
|
|
| 2172 |
tcg_gen_extu_tl_i64(r_tmp2, t1);
|
|
| 2149 | 2173 |
tcg_gen_mul_i64(r_tmp1, r_tmp1, r_tmp2); |
| 2150 |
gen_load_LO(cpu_T[0], 0);
|
|
| 2151 |
gen_load_HI(cpu_T[1], 0);
|
|
| 2152 |
tcg_gen_extu_tl_i64(r_tmp2, cpu_T[0]);
|
|
| 2153 |
tcg_gen_extu_tl_i64(r_tmp3, cpu_T[1]);
|
|
| 2174 |
gen_load_LO(t0, 0);
|
|
| 2175 |
gen_load_HI(t1, 0);
|
|
| 2176 |
tcg_gen_extu_tl_i64(r_tmp2, t0);
|
|
| 2177 |
tcg_gen_extu_tl_i64(r_tmp3, t1);
|
|
| 2154 | 2178 |
tcg_gen_shli_i64(r_tmp3, r_tmp3, 32); |
| 2155 | 2179 |
tcg_gen_or_i64(r_tmp2, r_tmp2, r_tmp3); |
| 2156 | 2180 |
tcg_temp_free(r_tmp3); |
| 2157 | 2181 |
tcg_gen_add_i64(r_tmp1, r_tmp1, r_tmp2); |
| 2158 | 2182 |
tcg_temp_free(r_tmp2); |
| 2159 |
tcg_gen_trunc_i64_tl(cpu_T[0], r_tmp1);
|
|
| 2183 |
tcg_gen_trunc_i64_tl(t0, r_tmp1);
|
|
| 2160 | 2184 |
tcg_gen_shri_i64(r_tmp1, r_tmp1, 32); |
| 2161 |
tcg_gen_trunc_i64_tl(cpu_T[1], r_tmp1);
|
|
| 2185 |
tcg_gen_trunc_i64_tl(t1, r_tmp1);
|
|
| 2162 | 2186 |
tcg_temp_free(r_tmp1); |
| 2163 |
tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
|
|
| 2164 |
tcg_gen_ext32s_tl(cpu_T[1], cpu_T[1]);
|
|
| 2165 |
gen_store_LO(cpu_T[0], 0);
|
|
| 2166 |
gen_store_HI(cpu_T[1], 0);
|
|
| 2187 |
tcg_gen_ext32s_tl(t0, t0);
|
|
| 2188 |
tcg_gen_ext32s_tl(t1, t1);
|
|
| 2189 |
gen_store_LO(t0, 0);
|
|
| 2190 |
gen_store_HI(t1, 0);
|
|
| 2167 | 2191 |
} |
| 2168 | 2192 |
opn = "maddu"; |
| 2169 | 2193 |
break; |
| ... | ... | |
| 2173 | 2197 |
TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_I64); |
| 2174 | 2198 |
TCGv r_tmp3 = tcg_temp_new(TCG_TYPE_I64); |
| 2175 | 2199 |
|
| 2176 |
tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
|
|
| 2177 |
tcg_gen_ext32s_tl(cpu_T[1], cpu_T[1]);
|
|
| 2178 |
tcg_gen_ext_tl_i64(r_tmp1, cpu_T[0]);
|
|
| 2179 |
tcg_gen_ext_tl_i64(r_tmp2, cpu_T[1]);
|
|
| 2200 |
tcg_gen_ext32s_tl(t0, t0);
|
|
| 2201 |
tcg_gen_ext32s_tl(t1, t1);
|
|
| 2202 |
tcg_gen_ext_tl_i64(r_tmp1, t0);
|
|
| 2203 |
tcg_gen_ext_tl_i64(r_tmp2, t1);
|
|
| 2180 | 2204 |
tcg_gen_mul_i64(r_tmp1, r_tmp1, r_tmp2); |
| 2181 |
gen_load_LO(cpu_T[0], 0);
|
|
| 2182 |
gen_load_HI(cpu_T[1], 0);
|
|
| 2183 |
tcg_gen_extu_tl_i64(r_tmp2, cpu_T[0]);
|
|
| 2184 |
tcg_gen_extu_tl_i64(r_tmp3, cpu_T[1]);
|
|
| 2205 |
gen_load_LO(t0, 0);
|
|
| 2206 |
gen_load_HI(t1, 0);
|
|
| 2207 |
tcg_gen_extu_tl_i64(r_tmp2, t0);
|
|
| 2208 |
tcg_gen_extu_tl_i64(r_tmp3, t1);
|
|
| 2185 | 2209 |
tcg_gen_shli_i64(r_tmp3, r_tmp3, 32); |
| 2186 | 2210 |
tcg_gen_or_i64(r_tmp2, r_tmp2, r_tmp3); |
| 2187 | 2211 |
tcg_temp_free(r_tmp3); |
| 2188 | 2212 |
tcg_gen_sub_i64(r_tmp1, r_tmp1, r_tmp2); |
| 2189 | 2213 |
tcg_temp_free(r_tmp2); |
| 2190 |
tcg_gen_trunc_i64_tl(cpu_T[0], r_tmp1);
|
|
| 2214 |
tcg_gen_trunc_i64_tl(t0, r_tmp1);
|
|
| 2191 | 2215 |
tcg_gen_shri_i64(r_tmp1, r_tmp1, 32); |
| 2192 |
tcg_gen_trunc_i64_tl(cpu_T[1], r_tmp1);
|
|
| 2216 |
tcg_gen_trunc_i64_tl(t1, r_tmp1);
|
|
| 2193 | 2217 |
tcg_temp_free(r_tmp1); |
| 2194 |
tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
|
|
| 2195 |
tcg_gen_ext32s_tl(cpu_T[1], cpu_T[1]);
|
|
| 2196 |
gen_store_LO(cpu_T[0], 0);
|
|
| 2197 |
gen_store_HI(cpu_T[1], 0);
|
|
| 2218 |
tcg_gen_ext32s_tl(t0, t0);
|
|
| 2219 |
tcg_gen_ext32s_tl(t1, t1);
|
|
| 2220 |
gen_store_LO(t0, 0);
|
|
| 2221 |
gen_store_HI(t1, 0);
|
|
| 2198 | 2222 |
} |
| 2199 | 2223 |
opn = "msub"; |
| 2200 | 2224 |
break; |
| ... | ... | |
| 2204 | 2228 |
TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_I64); |
| 2205 | 2229 |
TCGv r_tmp3 = tcg_temp_new(TCG_TYPE_I64); |
| 2206 | 2230 |
|
| 2207 |
tcg_gen_ext32u_tl(cpu_T[0], cpu_T[0]);
|
|
| 2208 |
tcg_gen_ext32u_tl(cpu_T[1], cpu_T[1]);
|
|
| 2209 |
tcg_gen_extu_tl_i64(r_tmp1, cpu_T[0]);
|
|
| 2210 |
tcg_gen_extu_tl_i64(r_tmp2, cpu_T[1]);
|
|
| 2231 |
tcg_gen_ext32u_tl(t0, t0);
|
|
| 2232 |
tcg_gen_ext32u_tl(t1, t1);
|
|
| 2233 |
tcg_gen_extu_tl_i64(r_tmp1, t0);
|
|
| 2234 |
tcg_gen_extu_tl_i64(r_tmp2, t1);
|
|
| 2211 | 2235 |
tcg_gen_mul_i64(r_tmp1, r_tmp1, r_tmp2); |
| 2212 |
gen_load_LO(cpu_T[0], 0);
|
|
| 2213 |
gen_load_HI(cpu_T[1], 0);
|
|
| 2214 |
tcg_gen_extu_tl_i64(r_tmp2, cpu_T[0]);
|
|
| 2215 |
tcg_gen_extu_tl_i64(r_tmp3, cpu_T[1]);
|
|
| 2236 |
gen_load_LO(t0, 0);
|
|
| 2237 |
gen_load_HI(t1, 0);
|
|
| 2238 |
tcg_gen_extu_tl_i64(r_tmp2, t0);
|
|
| 2239 |
tcg_gen_extu_tl_i64(r_tmp3, t1);
|
|
| 2216 | 2240 |
tcg_gen_shli_i64(r_tmp3, r_tmp3, 32); |
| 2217 | 2241 |
tcg_gen_or_i64(r_tmp2, r_tmp2, r_tmp3); |
| 2218 | 2242 |
tcg_temp_free(r_tmp3); |
| 2219 | 2243 |
tcg_gen_sub_i64(r_tmp1, r_tmp1, r_tmp2); |
| 2220 | 2244 |
tcg_temp_free(r_tmp2); |
| 2221 |
tcg_gen_trunc_i64_tl(cpu_T[0], r_tmp1);
|
|
| 2245 |
tcg_gen_trunc_i64_tl(t0, r_tmp1);
|
|
| 2222 | 2246 |
tcg_gen_shri_i64(r_tmp1, r_tmp1, 32); |
| 2223 |
tcg_gen_trunc_i64_tl(cpu_T[1], r_tmp1);
|
|
| 2247 |
tcg_gen_trunc_i64_tl(t1, r_tmp1);
|
|
| 2224 | 2248 |
tcg_temp_free(r_tmp1); |
| 2225 |
tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
|
|
| 2226 |
tcg_gen_ext32s_tl(cpu_T[1], cpu_T[1]);
|
|
| 2227 |
gen_store_LO(cpu_T[0], 0);
|
|
| 2228 |
gen_store_HI(cpu_T[1], 0);
|
|
| 2249 |
tcg_gen_ext32s_tl(t0, t0);
|
|
| 2250 |
tcg_gen_ext32s_tl(t1, t1);
|
|
| 2251 |
gen_store_LO(t0, 0);
|
|
| 2252 |
gen_store_HI(t1, 0);
|
|
| 2229 | 2253 |
} |
| 2230 | 2254 |
opn = "msubu"; |
| 2231 | 2255 |
break; |
| 2232 | 2256 |
default: |
| 2233 | 2257 |
MIPS_INVAL(opn); |
| 2234 | 2258 |
generate_exception(ctx, EXCP_RI); |
| 2235 |
return;
|
|
| 2259 |
goto out;
|
|
| 2236 | 2260 |
} |
| 2237 | 2261 |
MIPS_DEBUG("%s %s %s", opn, regnames[rs], regnames[rt]);
|
| 2262 |
out: |
|
| 2263 |
tcg_temp_free(t0); |
|
| 2264 |
tcg_temp_free(t1); |
|
| 2238 | 2265 |
} |
| 2239 | 2266 |
|
| 2240 | 2267 |
static void gen_mul_vr54xx (DisasContext *ctx, uint32_t opc, |
Also available in: Unified diff