Revision 787aaf57 target-i386/cpu.c
| b/target-i386/cpu.c | ||
|---|---|---|
| 486 | 486 |
int stepping; |
| 487 | 487 |
FeatureWordArray features; |
| 488 | 488 |
char model_id[48]; |
| 489 |
bool cache_info_passthrough; |
|
| 489 | 490 |
} x86_def_t; |
| 490 | 491 |
|
| 491 | 492 |
#define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE) |
| ... | ... | |
| 1139 | 1140 |
assert(kvm_enabled()); |
| 1140 | 1141 |
|
| 1141 | 1142 |
x86_cpu_def->name = "host"; |
| 1143 |
x86_cpu_def->cache_info_passthrough = true; |
|
| 1142 | 1144 |
host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx); |
| 1143 | 1145 |
x86_cpu_vendor_words2str(x86_cpu_def->vendor, ebx, edx, ecx); |
| 1144 | 1146 |
|
| ... | ... | |
| 1888 | 1890 |
env->features[FEAT_C000_0001_EDX] = def->features[FEAT_C000_0001_EDX]; |
| 1889 | 1891 |
env->features[FEAT_7_0_EBX] = def->features[FEAT_7_0_EBX]; |
| 1890 | 1892 |
env->cpuid_xlevel2 = def->xlevel2; |
| 1893 |
cpu->cache_info_passthrough = def->cache_info_passthrough; |
|
| 1891 | 1894 |
|
| 1892 | 1895 |
object_property_set_str(OBJECT(cpu), def->model_id, "model-id", errp); |
| 1893 | 1896 |
} |
| ... | ... | |
| 2062 | 2065 |
break; |
| 2063 | 2066 |
case 2: |
| 2064 | 2067 |
/* cache info: needed for Pentium Pro compatibility */ |
| 2068 |
if (cpu->cache_info_passthrough) {
|
|
| 2069 |
host_cpuid(index, 0, eax, ebx, ecx, edx); |
|
| 2070 |
break; |
|
| 2071 |
} |
|
| 2065 | 2072 |
*eax = 1; /* Number of CPUID[EAX=2] calls required */ |
| 2066 | 2073 |
*ebx = 0; |
| 2067 | 2074 |
*ecx = 0; |
| ... | ... | |
| 2071 | 2078 |
break; |
| 2072 | 2079 |
case 4: |
| 2073 | 2080 |
/* cache info: needed for Core compatibility */ |
| 2081 |
if (cpu->cache_info_passthrough) {
|
|
| 2082 |
host_cpuid(index, count, eax, ebx, ecx, edx); |
|
| 2083 |
break; |
|
| 2084 |
} |
|
| 2074 | 2085 |
if (cs->nr_cores > 1) {
|
| 2075 | 2086 |
*eax = (cs->nr_cores - 1) << 26; |
| 2076 | 2087 |
} else {
|
| ... | ... | |
| 2228 | 2239 |
break; |
| 2229 | 2240 |
case 0x80000005: |
| 2230 | 2241 |
/* cache info (L1 cache) */ |
| 2242 |
if (cpu->cache_info_passthrough) {
|
|
| 2243 |
host_cpuid(index, 0, eax, ebx, ecx, edx); |
|
| 2244 |
break; |
|
| 2245 |
} |
|
| 2231 | 2246 |
*eax = (L1_DTLB_2M_ASSOC << 24) | (L1_DTLB_2M_ENTRIES << 16) | \ |
| 2232 | 2247 |
(L1_ITLB_2M_ASSOC << 8) | (L1_ITLB_2M_ENTRIES); |
| 2233 | 2248 |
*ebx = (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) | \ |
| ... | ... | |
| 2239 | 2254 |
break; |
| 2240 | 2255 |
case 0x80000006: |
| 2241 | 2256 |
/* cache info (L2 cache) */ |
| 2257 |
if (cpu->cache_info_passthrough) {
|
|
| 2258 |
host_cpuid(index, 0, eax, ebx, ecx, edx); |
|
| 2259 |
break; |
|
| 2260 |
} |
|
| 2242 | 2261 |
*eax = (AMD_ENC_ASSOC(L2_DTLB_2M_ASSOC) << 28) | \ |
| 2243 | 2262 |
(L2_DTLB_2M_ENTRIES << 16) | \ |
| 2244 | 2263 |
(AMD_ENC_ASSOC(L2_ITLB_2M_ASSOC) << 12) | \ |
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