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/*
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* OMAP on-chip MMC/SD host emulation.
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*
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* Copyright (C) 2006-2007 Andrzej Zaborowski <balrog@zabor.org>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 or
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* (at your option) version 3 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include "hw.h" |
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#include "omap.h" |
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#include "sd.h" |
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struct omap_mmc_s {
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target_phys_addr_t base; |
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qemu_irq irq; |
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qemu_irq *dma; |
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qemu_irq coverswitch; |
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omap_clk clk; |
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SDState *card; |
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uint16_t last_cmd; |
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uint16_t sdio; |
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uint16_t rsp[8];
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uint32_t arg; |
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int lines;
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int dw;
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int mode;
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int enable;
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int be;
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int rev;
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uint16_t status; |
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uint16_t mask; |
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uint8_t cto; |
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uint16_t dto; |
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int clkdiv;
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uint16_t fifo[32];
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int fifo_start;
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int fifo_len;
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uint16_t blen; |
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uint16_t blen_counter; |
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uint16_t nblk; |
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uint16_t nblk_counter; |
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int tx_dma;
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int rx_dma;
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int af_level;
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int ae_level;
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int ddir;
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int transfer;
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int cdet_wakeup;
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int cdet_enable;
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int cdet_state;
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qemu_irq cdet; |
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}; |
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static void omap_mmc_interrupts_update(struct omap_mmc_s *s) |
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{ |
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qemu_set_irq(s->irq, !!(s->status & s->mask)); |
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} |
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static void omap_mmc_fifolevel_update(struct omap_mmc_s *host) |
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{ |
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if (!host->transfer && !host->fifo_len) {
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host->status &= 0xf3ff;
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return;
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} |
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if (host->fifo_len > host->af_level && host->ddir) {
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if (host->rx_dma) {
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host->status &= 0xfbff;
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qemu_irq_raise(host->dma[1]);
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} else
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host->status |= 0x0400;
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} else {
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host->status &= 0xfbff;
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qemu_irq_lower(host->dma[1]);
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} |
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if (host->fifo_len < host->ae_level && !host->ddir) {
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if (host->tx_dma) {
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host->status &= 0xf7ff;
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qemu_irq_raise(host->dma[0]);
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} else
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host->status |= 0x0800;
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} else {
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qemu_irq_lower(host->dma[0]);
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host->status &= 0xf7ff;
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} |
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} |
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typedef enum { |
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sd_nore = 0, /* no response */ |
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sd_r1, /* normal response command */
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sd_r2, /* CID, CSD registers */
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sd_r3, /* OCR register */
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sd_r6 = 6, /* Published RCA response */ |
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sd_r1b = -1,
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} sd_rsp_type_t; |
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static void omap_mmc_command(struct omap_mmc_s *host, int cmd, int dir, |
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sd_cmd_type_t type, int busy, sd_rsp_type_t resptype, int init) |
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{ |
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uint32_t rspstatus, mask; |
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int rsplen, timeout;
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struct sd_request_s request;
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uint8_t response[16];
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if (init && cmd == 0) { |
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host->status |= 0x0001;
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return;
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} |
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if (resptype == sd_r1 && busy)
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resptype = sd_r1b; |
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if (type == sd_adtc) {
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host->fifo_start = 0;
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host->fifo_len = 0;
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host->transfer = 1;
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host->ddir = dir; |
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} else
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host->transfer = 0;
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timeout = 0;
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mask = 0;
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rspstatus = 0;
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request.cmd = cmd; |
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request.arg = host->arg; |
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request.crc = 0; /* FIXME */ |
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rsplen = sd_do_command(host->card, &request, response); |
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/* TODO: validate CRCs */
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switch (resptype) {
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case sd_nore:
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rsplen = 0;
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break;
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case sd_r1:
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case sd_r1b:
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if (rsplen < 4) { |
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timeout = 1;
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break;
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} |
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rsplen = 4;
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mask = OUT_OF_RANGE | ADDRESS_ERROR | BLOCK_LEN_ERROR | |
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ERASE_SEQ_ERROR | ERASE_PARAM | WP_VIOLATION | |
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LOCK_UNLOCK_FAILED | COM_CRC_ERROR | ILLEGAL_COMMAND | |
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CARD_ECC_FAILED | CC_ERROR | SD_ERROR | |
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CID_CSD_OVERWRITE; |
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if (host->sdio & (1 << 13)) |
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mask |= AKE_SEQ_ERROR; |
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rspstatus = (response[0] << 24) | (response[1] << 16) | |
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(response[2] << 8) | (response[3] << 0); |
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break;
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case sd_r2:
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if (rsplen < 16) { |
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timeout = 1;
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break;
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} |
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rsplen = 16;
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break;
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case sd_r3:
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if (rsplen < 4) { |
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timeout = 1;
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break;
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} |
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rsplen = 4;
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rspstatus = (response[0] << 24) | (response[1] << 16) | |
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(response[2] << 8) | (response[3] << 0); |
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if (rspstatus & 0x80000000) |
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host->status &= 0xe000;
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else
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host->status |= 0x1000;
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break;
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case sd_r6:
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if (rsplen < 4) { |
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timeout = 1;
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break;
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} |
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rsplen = 4;
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mask = 0xe000 | AKE_SEQ_ERROR;
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rspstatus = (response[2] << 8) | (response[3] << 0); |
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} |
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if (rspstatus & mask)
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host->status |= 0x4000;
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else
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host->status &= 0xb000;
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if (rsplen)
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for (rsplen = 0; rsplen < 8; rsplen ++) |
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host->rsp[~rsplen & 7] = response[(rsplen << 1) | 1] | |
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(response[(rsplen << 1) | 0] << 8); |
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if (timeout)
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host->status |= 0x0080;
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else if (cmd == 12) |
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host->status |= 0x0005; /* Makes it more real */ |
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else
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host->status |= 0x0001;
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} |
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static void omap_mmc_transfer(struct omap_mmc_s *host) |
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{ |
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uint8_t value; |
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if (!host->transfer)
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return;
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while (1) { |
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if (host->ddir) {
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if (host->fifo_len > host->af_level)
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break;
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value = sd_read_data(host->card); |
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host->fifo[(host->fifo_start + host->fifo_len) & 31] = value;
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if (-- host->blen_counter) {
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value = sd_read_data(host->card); |
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host->fifo[(host->fifo_start + host->fifo_len) & 31] |=
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value << 8;
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host->blen_counter --; |
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} |
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host->fifo_len ++; |
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} else {
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if (!host->fifo_len)
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break;
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value = host->fifo[host->fifo_start] & 0xff;
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sd_write_data(host->card, value); |
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if (-- host->blen_counter) {
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value = host->fifo[host->fifo_start] >> 8;
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sd_write_data(host->card, value); |
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host->blen_counter --; |
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} |
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host->fifo_start ++; |
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host->fifo_len --; |
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host->fifo_start &= 31;
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} |
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if (host->blen_counter == 0) { |
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host->nblk_counter --; |
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host->blen_counter = host->blen; |
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if (host->nblk_counter == 0) { |
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host->nblk_counter = host->nblk; |
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host->transfer = 0;
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host->status |= 0x0008;
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break;
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} |
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} |
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} |
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} |
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static void omap_mmc_update(void *opaque) |
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{ |
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struct omap_mmc_s *s = opaque;
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omap_mmc_transfer(s); |
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omap_mmc_fifolevel_update(s); |
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omap_mmc_interrupts_update(s); |
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} |
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void omap_mmc_reset(struct omap_mmc_s *host) |
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{ |
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host->last_cmd = 0;
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memset(host->rsp, 0, sizeof(host->rsp)); |
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host->arg = 0;
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host->dw = 0;
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host->mode = 0;
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host->enable = 0;
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host->status = 0;
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host->mask = 0;
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host->cto = 0;
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host->dto = 0;
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host->fifo_len = 0;
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host->blen = 0;
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host->blen_counter = 0;
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host->nblk = 0;
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host->nblk_counter = 0;
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host->tx_dma = 0;
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host->rx_dma = 0;
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host->ae_level = 0x00;
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host->af_level = 0x1f;
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host->transfer = 0;
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host->cdet_wakeup = 0;
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host->cdet_enable = 0;
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qemu_set_irq(host->coverswitch, host->cdet_state); |
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host->clkdiv = 0;
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} |
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static uint32_t omap_mmc_read(void *opaque, target_phys_addr_t offset) |
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{ |
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uint16_t i; |
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struct omap_mmc_s *s = (struct omap_mmc_s *) opaque; |
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offset &= OMAP_MPUI_REG_MASK; |
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switch (offset) {
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case 0x00: /* MMC_CMD */ |
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return s->last_cmd;
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case 0x04: /* MMC_ARGL */ |
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return s->arg & 0x0000ffff; |
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case 0x08: /* MMC_ARGH */ |
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return s->arg >> 16; |
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case 0x0c: /* MMC_CON */ |
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return (s->dw << 15) | (s->mode << 12) | (s->enable << 11) | |
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(s->be << 10) | s->clkdiv;
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case 0x10: /* MMC_STAT */ |
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return s->status;
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|
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case 0x14: /* MMC_IE */ |
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return s->mask;
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|
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case 0x18: /* MMC_CTO */ |
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return s->cto;
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case 0x1c: /* MMC_DTO */ |
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return s->dto;
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case 0x20: /* MMC_DATA */ |
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/* TODO: support 8-bit access */
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i = s->fifo[s->fifo_start]; |
346 |
if (s->fifo_len == 0) { |
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printf("MMC: FIFO underrun\n");
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return i;
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} |
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s->fifo_start ++; |
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s->fifo_len --; |
352 |
s->fifo_start &= 31;
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omap_mmc_transfer(s); |
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omap_mmc_fifolevel_update(s); |
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omap_mmc_interrupts_update(s); |
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return i;
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|
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case 0x24: /* MMC_BLEN */ |
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return s->blen_counter;
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|
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case 0x28: /* MMC_NBLK */ |
362 |
return s->nblk_counter;
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363 |
|
364 |
case 0x2c: /* MMC_BUF */ |
365 |
return (s->rx_dma << 15) | (s->af_level << 8) | |
366 |
(s->tx_dma << 7) | s->ae_level;
|
367 |
|
368 |
case 0x30: /* MMC_SPI */ |
369 |
return 0x0000; |
370 |
case 0x34: /* MMC_SDIO */ |
371 |
return (s->cdet_wakeup << 2) | (s->cdet_enable) | s->sdio; |
372 |
case 0x38: /* MMC_SYST */ |
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return 0x0000; |
374 |
|
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case 0x3c: /* MMC_REV */ |
376 |
return s->rev;
|
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|
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case 0x40: /* MMC_RSP0 */ |
379 |
case 0x44: /* MMC_RSP1 */ |
380 |
case 0x48: /* MMC_RSP2 */ |
381 |
case 0x4c: /* MMC_RSP3 */ |
382 |
case 0x50: /* MMC_RSP4 */ |
383 |
case 0x54: /* MMC_RSP5 */ |
384 |
case 0x58: /* MMC_RSP6 */ |
385 |
case 0x5c: /* MMC_RSP7 */ |
386 |
return s->rsp[(offset - 0x40) >> 2]; |
387 |
|
388 |
/* OMAP2-specific */
|
389 |
case 0x60: /* MMC_IOSR */ |
390 |
case 0x64: /* MMC_SYSC */ |
391 |
return 0; |
392 |
case 0x68: /* MMC_SYSS */ |
393 |
return 1; /* RSTD */ |
394 |
} |
395 |
|
396 |
OMAP_BAD_REG(offset); |
397 |
return 0; |
398 |
} |
399 |
|
400 |
static void omap_mmc_write(void *opaque, target_phys_addr_t offset, |
401 |
uint32_t value) |
402 |
{ |
403 |
int i;
|
404 |
struct omap_mmc_s *s = (struct omap_mmc_s *) opaque; |
405 |
offset &= OMAP_MPUI_REG_MASK; |
406 |
|
407 |
switch (offset) {
|
408 |
case 0x00: /* MMC_CMD */ |
409 |
if (!s->enable)
|
410 |
break;
|
411 |
|
412 |
s->last_cmd = value; |
413 |
for (i = 0; i < 8; i ++) |
414 |
s->rsp[i] = 0x0000;
|
415 |
omap_mmc_command(s, value & 63, (value >> 15) & 1, |
416 |
(sd_cmd_type_t) ((value >> 12) & 3), |
417 |
(value >> 11) & 1, |
418 |
(sd_rsp_type_t) ((value >> 8) & 7), |
419 |
(value >> 7) & 1); |
420 |
omap_mmc_update(s); |
421 |
break;
|
422 |
|
423 |
case 0x04: /* MMC_ARGL */ |
424 |
s->arg &= 0xffff0000;
|
425 |
s->arg |= 0x0000ffff & value;
|
426 |
break;
|
427 |
|
428 |
case 0x08: /* MMC_ARGH */ |
429 |
s->arg &= 0x0000ffff;
|
430 |
s->arg |= value << 16;
|
431 |
break;
|
432 |
|
433 |
case 0x0c: /* MMC_CON */ |
434 |
s->dw = (value >> 15) & 1; |
435 |
s->mode = (value >> 12) & 3; |
436 |
s->enable = (value >> 11) & 1; |
437 |
s->be = (value >> 10) & 1; |
438 |
s->clkdiv = (value >> 0) & (s->rev >= 2 ? 0x3ff : 0xff); |
439 |
if (s->mode != 0) |
440 |
printf("SD mode %i unimplemented!\n", s->mode);
|
441 |
if (s->be != 0) |
442 |
printf("SD FIFO byte sex unimplemented!\n");
|
443 |
if (s->dw != 0 && s->lines < 4) |
444 |
printf("4-bit SD bus enabled\n");
|
445 |
if (!s->enable)
|
446 |
omap_mmc_reset(s); |
447 |
break;
|
448 |
|
449 |
case 0x10: /* MMC_STAT */ |
450 |
s->status &= ~value; |
451 |
omap_mmc_interrupts_update(s); |
452 |
break;
|
453 |
|
454 |
case 0x14: /* MMC_IE */ |
455 |
s->mask = value & 0x7fff;
|
456 |
omap_mmc_interrupts_update(s); |
457 |
break;
|
458 |
|
459 |
case 0x18: /* MMC_CTO */ |
460 |
s->cto = value & 0xff;
|
461 |
if (s->cto > 0xfd && s->rev <= 1) |
462 |
printf("MMC: CTO of 0xff and 0xfe cannot be used!\n");
|
463 |
break;
|
464 |
|
465 |
case 0x1c: /* MMC_DTO */ |
466 |
s->dto = value & 0xffff;
|
467 |
break;
|
468 |
|
469 |
case 0x20: /* MMC_DATA */ |
470 |
/* TODO: support 8-bit access */
|
471 |
if (s->fifo_len == 32) |
472 |
break;
|
473 |
s->fifo[(s->fifo_start + s->fifo_len) & 31] = value;
|
474 |
s->fifo_len ++; |
475 |
omap_mmc_transfer(s); |
476 |
omap_mmc_fifolevel_update(s); |
477 |
omap_mmc_interrupts_update(s); |
478 |
break;
|
479 |
|
480 |
case 0x24: /* MMC_BLEN */ |
481 |
s->blen = (value & 0x07ff) + 1; |
482 |
s->blen_counter = s->blen; |
483 |
break;
|
484 |
|
485 |
case 0x28: /* MMC_NBLK */ |
486 |
s->nblk = (value & 0x07ff) + 1; |
487 |
s->nblk_counter = s->nblk; |
488 |
s->blen_counter = s->blen; |
489 |
break;
|
490 |
|
491 |
case 0x2c: /* MMC_BUF */ |
492 |
s->rx_dma = (value >> 15) & 1; |
493 |
s->af_level = (value >> 8) & 0x1f; |
494 |
s->tx_dma = (value >> 7) & 1; |
495 |
s->ae_level = value & 0x1f;
|
496 |
|
497 |
if (s->rx_dma)
|
498 |
s->status &= 0xfbff;
|
499 |
if (s->tx_dma)
|
500 |
s->status &= 0xf7ff;
|
501 |
omap_mmc_fifolevel_update(s); |
502 |
omap_mmc_interrupts_update(s); |
503 |
break;
|
504 |
|
505 |
/* SPI, SDIO and TEST modes unimplemented */
|
506 |
case 0x30: /* MMC_SPI (OMAP1 only) */ |
507 |
break;
|
508 |
case 0x34: /* MMC_SDIO */ |
509 |
s->sdio = value & (s->rev >= 2 ? 0xfbf3 : 0x2020); |
510 |
s->cdet_wakeup = (value >> 9) & 1; |
511 |
s->cdet_enable = (value >> 2) & 1; |
512 |
break;
|
513 |
case 0x38: /* MMC_SYST */ |
514 |
break;
|
515 |
|
516 |
case 0x3c: /* MMC_REV */ |
517 |
case 0x40: /* MMC_RSP0 */ |
518 |
case 0x44: /* MMC_RSP1 */ |
519 |
case 0x48: /* MMC_RSP2 */ |
520 |
case 0x4c: /* MMC_RSP3 */ |
521 |
case 0x50: /* MMC_RSP4 */ |
522 |
case 0x54: /* MMC_RSP5 */ |
523 |
case 0x58: /* MMC_RSP6 */ |
524 |
case 0x5c: /* MMC_RSP7 */ |
525 |
OMAP_RO_REG(offset); |
526 |
break;
|
527 |
|
528 |
/* OMAP2-specific */
|
529 |
case 0x60: /* MMC_IOSR */ |
530 |
if (value & 0xf) |
531 |
printf("MMC: SDIO bits used!\n");
|
532 |
break;
|
533 |
case 0x64: /* MMC_SYSC */ |
534 |
if (value & (1 << 2)) /* SRTS */ |
535 |
omap_mmc_reset(s); |
536 |
break;
|
537 |
case 0x68: /* MMC_SYSS */ |
538 |
OMAP_RO_REG(offset); |
539 |
break;
|
540 |
|
541 |
default:
|
542 |
OMAP_BAD_REG(offset); |
543 |
} |
544 |
} |
545 |
|
546 |
static CPUReadMemoryFunc *omap_mmc_readfn[] = {
|
547 |
omap_badwidth_read16, |
548 |
omap_mmc_read, |
549 |
omap_badwidth_read16, |
550 |
}; |
551 |
|
552 |
static CPUWriteMemoryFunc *omap_mmc_writefn[] = {
|
553 |
omap_badwidth_write16, |
554 |
omap_mmc_write, |
555 |
omap_badwidth_write16, |
556 |
}; |
557 |
|
558 |
static void omap_mmc_cover_cb(void *opaque, int line, int level) |
559 |
{ |
560 |
struct omap_mmc_s *host = (struct omap_mmc_s *) opaque; |
561 |
|
562 |
if (!host->cdet_state && level) {
|
563 |
host->status |= 0x0002;
|
564 |
omap_mmc_interrupts_update(host); |
565 |
if (host->cdet_wakeup)
|
566 |
/* TODO: Assert wake-up */;
|
567 |
} |
568 |
|
569 |
if (host->cdet_state != level) {
|
570 |
qemu_set_irq(host->coverswitch, level); |
571 |
host->cdet_state = level; |
572 |
} |
573 |
} |
574 |
|
575 |
struct omap_mmc_s *omap_mmc_init(target_phys_addr_t base,
|
576 |
BlockDriverState *bd, |
577 |
qemu_irq irq, qemu_irq dma[], omap_clk clk) |
578 |
{ |
579 |
int iomemtype;
|
580 |
struct omap_mmc_s *s = (struct omap_mmc_s *) |
581 |
qemu_mallocz(sizeof(struct omap_mmc_s)); |
582 |
|
583 |
s->irq = irq; |
584 |
s->base = base; |
585 |
s->dma = dma; |
586 |
s->clk = clk; |
587 |
s->lines = 1; /* TODO: needs to be settable per-board */ |
588 |
s->rev = 1;
|
589 |
|
590 |
omap_mmc_reset(s); |
591 |
|
592 |
iomemtype = cpu_register_io_memory(0, omap_mmc_readfn,
|
593 |
omap_mmc_writefn, s); |
594 |
cpu_register_physical_memory(s->base, 0x800, iomemtype);
|
595 |
|
596 |
/* Instantiate the storage */
|
597 |
s->card = sd_init(bd, 0);
|
598 |
|
599 |
return s;
|
600 |
} |
601 |
|
602 |
struct omap_mmc_s *omap2_mmc_init(struct omap_target_agent_s *ta, |
603 |
BlockDriverState *bd, qemu_irq irq, qemu_irq dma[], |
604 |
omap_clk fclk, omap_clk iclk) |
605 |
{ |
606 |
int iomemtype;
|
607 |
struct omap_mmc_s *s = (struct omap_mmc_s *) |
608 |
qemu_mallocz(sizeof(struct omap_mmc_s)); |
609 |
|
610 |
s->irq = irq; |
611 |
s->dma = dma; |
612 |
s->clk = fclk; |
613 |
s->lines = 4;
|
614 |
s->rev = 2;
|
615 |
|
616 |
omap_mmc_reset(s); |
617 |
|
618 |
iomemtype = cpu_register_io_memory(0, omap_mmc_readfn,
|
619 |
omap_mmc_writefn, s); |
620 |
s->base = omap_l4_attach(ta, 0, iomemtype);
|
621 |
|
622 |
/* Instantiate the storage */
|
623 |
s->card = sd_init(bd, 0);
|
624 |
|
625 |
s->cdet = qemu_allocate_irqs(omap_mmc_cover_cb, s, 1)[0]; |
626 |
sd_set_cb(s->card, 0, s->cdet);
|
627 |
|
628 |
return s;
|
629 |
} |
630 |
|
631 |
void omap_mmc_handlers(struct omap_mmc_s *s, qemu_irq ro, qemu_irq cover) |
632 |
{ |
633 |
if (s->cdet) {
|
634 |
sd_set_cb(s->card, ro, s->cdet); |
635 |
s->coverswitch = cover; |
636 |
qemu_set_irq(cover, s->cdet_state); |
637 |
} else
|
638 |
sd_set_cb(s->card, ro, cover); |
639 |
} |
640 |
|
641 |
void omap_mmc_enable(struct omap_mmc_s *s, int enable) |
642 |
{ |
643 |
sd_enable(s->card, enable); |
644 |
} |