root / hw / etraxfs_dma.c @ 79383c9c
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1 | 1ba13a5d | edgar_igl | /*
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2 | 1ba13a5d | edgar_igl | * QEMU ETRAX DMA Controller.
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3 | 1ba13a5d | edgar_igl | *
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4 | 1ba13a5d | edgar_igl | * Copyright (c) 2008 Edgar E. Iglesias, Axis Communications AB.
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5 | 1ba13a5d | edgar_igl | *
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6 | 1ba13a5d | edgar_igl | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | 1ba13a5d | edgar_igl | * of this software and associated documentation files (the "Software"), to deal
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8 | 1ba13a5d | edgar_igl | * in the Software without restriction, including without limitation the rights
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9 | 1ba13a5d | edgar_igl | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | 1ba13a5d | edgar_igl | * copies of the Software, and to permit persons to whom the Software is
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11 | 1ba13a5d | edgar_igl | * furnished to do so, subject to the following conditions:
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12 | 1ba13a5d | edgar_igl | *
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13 | 1ba13a5d | edgar_igl | * The above copyright notice and this permission notice shall be included in
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14 | 1ba13a5d | edgar_igl | * all copies or substantial portions of the Software.
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15 | 1ba13a5d | edgar_igl | *
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16 | 1ba13a5d | edgar_igl | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | 1ba13a5d | edgar_igl | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | 1ba13a5d | edgar_igl | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | 1ba13a5d | edgar_igl | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | 1ba13a5d | edgar_igl | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | 1ba13a5d | edgar_igl | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | 1ba13a5d | edgar_igl | * THE SOFTWARE.
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23 | 1ba13a5d | edgar_igl | */
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24 | 1ba13a5d | edgar_igl | #include <stdio.h> |
25 | 1ba13a5d | edgar_igl | #include <sys/time.h> |
26 | 1ba13a5d | edgar_igl | #include "hw.h" |
27 | 1ba13a5d | edgar_igl | |
28 | 1ba13a5d | edgar_igl | #include "etraxfs_dma.h" |
29 | 1ba13a5d | edgar_igl | |
30 | 1ba13a5d | edgar_igl | #define D(x)
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31 | 1ba13a5d | edgar_igl | |
32 | 1ba13a5d | edgar_igl | #define RW_DATA 0x0 |
33 | 1ba13a5d | edgar_igl | #define RW_SAVED_DATA 0x58 |
34 | 1ba13a5d | edgar_igl | #define RW_SAVED_DATA_BUF 0x5c |
35 | 1ba13a5d | edgar_igl | #define RW_GROUP 0x60 |
36 | 1ba13a5d | edgar_igl | #define RW_GROUP_DOWN 0x7c |
37 | 1ba13a5d | edgar_igl | #define RW_CMD 0x80 |
38 | 1ba13a5d | edgar_igl | #define RW_CFG 0x84 |
39 | 1ba13a5d | edgar_igl | #define RW_STAT 0x88 |
40 | 1ba13a5d | edgar_igl | #define RW_INTR_MASK 0x8c |
41 | 1ba13a5d | edgar_igl | #define RW_ACK_INTR 0x90 |
42 | 1ba13a5d | edgar_igl | #define R_INTR 0x94 |
43 | 1ba13a5d | edgar_igl | #define R_MASKED_INTR 0x98 |
44 | 1ba13a5d | edgar_igl | #define RW_STREAM_CMD 0x9c |
45 | 1ba13a5d | edgar_igl | |
46 | 1ba13a5d | edgar_igl | #define DMA_REG_MAX 0x100 |
47 | 1ba13a5d | edgar_igl | |
48 | 1ba13a5d | edgar_igl | /* descriptors */
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49 | 1ba13a5d | edgar_igl | |
50 | 1ba13a5d | edgar_igl | // ------------------------------------------------------------ dma_descr_group
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51 | 1ba13a5d | edgar_igl | typedef struct dma_descr_group { |
52 | 1ba13a5d | edgar_igl | struct dma_descr_group *next;
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53 | 1ba13a5d | edgar_igl | unsigned eol : 1; |
54 | 1ba13a5d | edgar_igl | unsigned tol : 1; |
55 | 1ba13a5d | edgar_igl | unsigned bol : 1; |
56 | 1ba13a5d | edgar_igl | unsigned : 1; |
57 | 1ba13a5d | edgar_igl | unsigned intr : 1; |
58 | 1ba13a5d | edgar_igl | unsigned : 2; |
59 | 1ba13a5d | edgar_igl | unsigned en : 1; |
60 | 1ba13a5d | edgar_igl | unsigned : 7; |
61 | 1ba13a5d | edgar_igl | unsigned dis : 1; |
62 | 1ba13a5d | edgar_igl | unsigned md : 16; |
63 | 1ba13a5d | edgar_igl | struct dma_descr_group *up;
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64 | 1ba13a5d | edgar_igl | union {
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65 | 1ba13a5d | edgar_igl | struct dma_descr_context *context;
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66 | 1ba13a5d | edgar_igl | struct dma_descr_group *group;
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67 | 1ba13a5d | edgar_igl | } down; |
68 | 1ba13a5d | edgar_igl | } dma_descr_group; |
69 | 1ba13a5d | edgar_igl | |
70 | 1ba13a5d | edgar_igl | // ---------------------------------------------------------- dma_descr_context
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71 | 1ba13a5d | edgar_igl | typedef struct dma_descr_context { |
72 | 1ba13a5d | edgar_igl | struct dma_descr_context *next;
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73 | 1ba13a5d | edgar_igl | unsigned eol : 1; |
74 | 1ba13a5d | edgar_igl | unsigned : 3; |
75 | 1ba13a5d | edgar_igl | unsigned intr : 1; |
76 | 1ba13a5d | edgar_igl | unsigned : 1; |
77 | 1ba13a5d | edgar_igl | unsigned store_mode : 1; |
78 | 1ba13a5d | edgar_igl | unsigned en : 1; |
79 | 1ba13a5d | edgar_igl | unsigned : 7; |
80 | 1ba13a5d | edgar_igl | unsigned dis : 1; |
81 | 1ba13a5d | edgar_igl | unsigned md0 : 16; |
82 | 1ba13a5d | edgar_igl | unsigned md1;
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83 | 1ba13a5d | edgar_igl | unsigned md2;
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84 | 1ba13a5d | edgar_igl | unsigned md3;
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85 | 1ba13a5d | edgar_igl | unsigned md4;
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86 | 1ba13a5d | edgar_igl | struct dma_descr_data *saved_data;
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87 | 1ba13a5d | edgar_igl | char *saved_data_buf;
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88 | 1ba13a5d | edgar_igl | } dma_descr_context; |
89 | 1ba13a5d | edgar_igl | |
90 | 1ba13a5d | edgar_igl | // ------------------------------------------------------------- dma_descr_data
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91 | 1ba13a5d | edgar_igl | typedef struct dma_descr_data { |
92 | 1ba13a5d | edgar_igl | struct dma_descr_data *next;
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93 | 1ba13a5d | edgar_igl | char *buf;
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94 | 1ba13a5d | edgar_igl | unsigned eol : 1; |
95 | 1ba13a5d | edgar_igl | unsigned : 2; |
96 | 1ba13a5d | edgar_igl | unsigned out_eop : 1; |
97 | 1ba13a5d | edgar_igl | unsigned intr : 1; |
98 | 1ba13a5d | edgar_igl | unsigned wait : 1; |
99 | 1ba13a5d | edgar_igl | unsigned : 2; |
100 | 1ba13a5d | edgar_igl | unsigned : 3; |
101 | 1ba13a5d | edgar_igl | unsigned in_eop : 1; |
102 | 1ba13a5d | edgar_igl | unsigned : 4; |
103 | 1ba13a5d | edgar_igl | unsigned md : 16; |
104 | 1ba13a5d | edgar_igl | char *after;
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105 | 1ba13a5d | edgar_igl | } dma_descr_data; |
106 | 1ba13a5d | edgar_igl | |
107 | 1ba13a5d | edgar_igl | /* Constants */
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108 | 1ba13a5d | edgar_igl | enum {
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109 | 1ba13a5d | edgar_igl | regk_dma_ack_pkt = 0x00000100,
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110 | 1ba13a5d | edgar_igl | regk_dma_anytime = 0x00000001,
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111 | 1ba13a5d | edgar_igl | regk_dma_array = 0x00000008,
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112 | 1ba13a5d | edgar_igl | regk_dma_burst = 0x00000020,
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113 | 1ba13a5d | edgar_igl | regk_dma_client = 0x00000002,
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114 | 1ba13a5d | edgar_igl | regk_dma_copy_next = 0x00000010,
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115 | 1ba13a5d | edgar_igl | regk_dma_copy_up = 0x00000020,
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116 | 1ba13a5d | edgar_igl | regk_dma_data_at_eol = 0x00000001,
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117 | 1ba13a5d | edgar_igl | regk_dma_dis_c = 0x00000010,
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118 | 1ba13a5d | edgar_igl | regk_dma_dis_g = 0x00000020,
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119 | 1ba13a5d | edgar_igl | regk_dma_idle = 0x00000001,
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120 | 1ba13a5d | edgar_igl | regk_dma_intern = 0x00000004,
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121 | 1ba13a5d | edgar_igl | regk_dma_load_c = 0x00000200,
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122 | 1ba13a5d | edgar_igl | regk_dma_load_c_n = 0x00000280,
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123 | 1ba13a5d | edgar_igl | regk_dma_load_c_next = 0x00000240,
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124 | 1ba13a5d | edgar_igl | regk_dma_load_d = 0x00000140,
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125 | 1ba13a5d | edgar_igl | regk_dma_load_g = 0x00000300,
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126 | 1ba13a5d | edgar_igl | regk_dma_load_g_down = 0x000003c0,
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127 | 1ba13a5d | edgar_igl | regk_dma_load_g_next = 0x00000340,
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128 | 1ba13a5d | edgar_igl | regk_dma_load_g_up = 0x00000380,
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129 | 1ba13a5d | edgar_igl | regk_dma_next_en = 0x00000010,
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130 | 1ba13a5d | edgar_igl | regk_dma_next_pkt = 0x00000010,
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131 | 1ba13a5d | edgar_igl | regk_dma_no = 0x00000000,
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132 | 1ba13a5d | edgar_igl | regk_dma_only_at_wait = 0x00000000,
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133 | 1ba13a5d | edgar_igl | regk_dma_restore = 0x00000020,
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134 | 1ba13a5d | edgar_igl | regk_dma_rst = 0x00000001,
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135 | 1ba13a5d | edgar_igl | regk_dma_running = 0x00000004,
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136 | 1ba13a5d | edgar_igl | regk_dma_rw_cfg_default = 0x00000000,
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137 | 1ba13a5d | edgar_igl | regk_dma_rw_cmd_default = 0x00000000,
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138 | 1ba13a5d | edgar_igl | regk_dma_rw_intr_mask_default = 0x00000000,
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139 | 1ba13a5d | edgar_igl | regk_dma_rw_stat_default = 0x00000101,
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140 | 1ba13a5d | edgar_igl | regk_dma_rw_stream_cmd_default = 0x00000000,
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141 | 1ba13a5d | edgar_igl | regk_dma_save_down = 0x00000020,
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142 | 1ba13a5d | edgar_igl | regk_dma_save_up = 0x00000020,
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143 | 1ba13a5d | edgar_igl | regk_dma_set_reg = 0x00000050,
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144 | 1ba13a5d | edgar_igl | regk_dma_set_w_size1 = 0x00000190,
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145 | 1ba13a5d | edgar_igl | regk_dma_set_w_size2 = 0x000001a0,
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146 | 1ba13a5d | edgar_igl | regk_dma_set_w_size4 = 0x000001c0,
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147 | 1ba13a5d | edgar_igl | regk_dma_stopped = 0x00000002,
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148 | 1ba13a5d | edgar_igl | regk_dma_store_c = 0x00000002,
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149 | 1ba13a5d | edgar_igl | regk_dma_store_descr = 0x00000000,
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150 | 1ba13a5d | edgar_igl | regk_dma_store_g = 0x00000004,
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151 | 1ba13a5d | edgar_igl | regk_dma_store_md = 0x00000001,
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152 | 1ba13a5d | edgar_igl | regk_dma_sw = 0x00000008,
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153 | 1ba13a5d | edgar_igl | regk_dma_update_down = 0x00000020,
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154 | 1ba13a5d | edgar_igl | regk_dma_yes = 0x00000001
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155 | 1ba13a5d | edgar_igl | }; |
156 | 1ba13a5d | edgar_igl | |
157 | 1ba13a5d | edgar_igl | enum dma_ch_state
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158 | 1ba13a5d | edgar_igl | { |
159 | 1ba13a5d | edgar_igl | RST = 0,
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160 | 1ba13a5d | edgar_igl | STOPPED = 2,
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161 | 1ba13a5d | edgar_igl | RUNNING = 4
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162 | 1ba13a5d | edgar_igl | }; |
163 | 1ba13a5d | edgar_igl | |
164 | 1ba13a5d | edgar_igl | struct fs_dma_channel
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165 | 1ba13a5d | edgar_igl | { |
166 | 1ba13a5d | edgar_igl | int regmap;
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167 | 1ba13a5d | edgar_igl | qemu_irq *irq; |
168 | 1ba13a5d | edgar_igl | struct etraxfs_dma_client *client;
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169 | 1ba13a5d | edgar_igl | |
170 | 1ba13a5d | edgar_igl | |
171 | 1ba13a5d | edgar_igl | /* Internal status. */
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172 | 1ba13a5d | edgar_igl | int stream_cmd_src;
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173 | 1ba13a5d | edgar_igl | enum dma_ch_state state;
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174 | 1ba13a5d | edgar_igl | |
175 | 1ba13a5d | edgar_igl | unsigned int input : 1; |
176 | 1ba13a5d | edgar_igl | unsigned int eol : 1; |
177 | 1ba13a5d | edgar_igl | |
178 | 1ba13a5d | edgar_igl | struct dma_descr_group current_g;
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179 | 1ba13a5d | edgar_igl | struct dma_descr_context current_c;
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180 | 1ba13a5d | edgar_igl | struct dma_descr_data current_d;
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181 | 1ba13a5d | edgar_igl | |
182 | 1ba13a5d | edgar_igl | /* Controll registers. */
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183 | 1ba13a5d | edgar_igl | uint32_t regs[DMA_REG_MAX]; |
184 | 1ba13a5d | edgar_igl | }; |
185 | 1ba13a5d | edgar_igl | |
186 | 1ba13a5d | edgar_igl | struct fs_dma_ctrl
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187 | 1ba13a5d | edgar_igl | { |
188 | 1ba13a5d | edgar_igl | CPUState *env; |
189 | 1ba13a5d | edgar_igl | target_phys_addr_t base; |
190 | 1ba13a5d | edgar_igl | |
191 | 1ba13a5d | edgar_igl | int nr_channels;
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192 | 1ba13a5d | edgar_igl | struct fs_dma_channel *channels;
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193 | 1ba13a5d | edgar_igl | }; |
194 | 1ba13a5d | edgar_igl | |
195 | 1ba13a5d | edgar_igl | static inline uint32_t channel_reg(struct fs_dma_ctrl *ctrl, int c, int reg) |
196 | 1ba13a5d | edgar_igl | { |
197 | 1ba13a5d | edgar_igl | return ctrl->channels[c].regs[reg];
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198 | 1ba13a5d | edgar_igl | } |
199 | 1ba13a5d | edgar_igl | |
200 | 1ba13a5d | edgar_igl | static inline int channel_stopped(struct fs_dma_ctrl *ctrl, int c) |
201 | 1ba13a5d | edgar_igl | { |
202 | 1ba13a5d | edgar_igl | return channel_reg(ctrl, c, RW_CFG) & 2; |
203 | 1ba13a5d | edgar_igl | } |
204 | 1ba13a5d | edgar_igl | |
205 | 1ba13a5d | edgar_igl | static inline int channel_en(struct fs_dma_ctrl *ctrl, int c) |
206 | 1ba13a5d | edgar_igl | { |
207 | 1ba13a5d | edgar_igl | return (channel_reg(ctrl, c, RW_CFG) & 1) |
208 | 1ba13a5d | edgar_igl | && ctrl->channels[c].client; |
209 | 1ba13a5d | edgar_igl | } |
210 | 1ba13a5d | edgar_igl | |
211 | 1ba13a5d | edgar_igl | static inline int fs_channel(target_phys_addr_t base, target_phys_addr_t addr) |
212 | 1ba13a5d | edgar_igl | { |
213 | 1ba13a5d | edgar_igl | /* Every channel has a 0x2000 ctrl register map. */
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214 | 1ba13a5d | edgar_igl | return (addr - base) >> 13; |
215 | 1ba13a5d | edgar_igl | } |
216 | 1ba13a5d | edgar_igl | |
217 | d297f464 | edgar_igl | #ifdef USE_THIS_DEAD_CODE
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218 | 1ba13a5d | edgar_igl | static void channel_load_g(struct fs_dma_ctrl *ctrl, int c) |
219 | 1ba13a5d | edgar_igl | { |
220 | 1ba13a5d | edgar_igl | target_phys_addr_t addr = channel_reg(ctrl, c, RW_GROUP); |
221 | 1ba13a5d | edgar_igl | |
222 | 1ba13a5d | edgar_igl | /* Load and decode. FIXME: handle endianness. */
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223 | 1ba13a5d | edgar_igl | cpu_physical_memory_read (addr, |
224 | 1ba13a5d | edgar_igl | (void *) &ctrl->channels[c].current_g,
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225 | 1ba13a5d | edgar_igl | sizeof ctrl->channels[c].current_g);
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226 | 1ba13a5d | edgar_igl | } |
227 | 1ba13a5d | edgar_igl | |
228 | 1ba13a5d | edgar_igl | static void dump_c(int ch, struct dma_descr_context *c) |
229 | 1ba13a5d | edgar_igl | { |
230 | 1ba13a5d | edgar_igl | printf("%s ch=%d\n", __func__, ch);
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231 | d297f464 | edgar_igl | printf("next=%p\n", c->next);
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232 | d297f464 | edgar_igl | printf("saved_data=%p\n", c->saved_data);
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233 | d297f464 | edgar_igl | printf("saved_data_buf=%p\n", c->saved_data_buf);
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234 | 1ba13a5d | edgar_igl | printf("eol=%x\n", (uint32_t) c->eol);
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235 | 1ba13a5d | edgar_igl | } |
236 | 1ba13a5d | edgar_igl | |
237 | 1ba13a5d | edgar_igl | static void dump_d(int ch, struct dma_descr_data *d) |
238 | 1ba13a5d | edgar_igl | { |
239 | 1ba13a5d | edgar_igl | printf("%s ch=%d\n", __func__, ch);
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240 | d297f464 | edgar_igl | printf("next=%p\n", d->next);
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241 | d297f464 | edgar_igl | printf("buf=%p\n", d->buf);
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242 | d297f464 | edgar_igl | printf("after=%p\n", d->after);
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243 | 1ba13a5d | edgar_igl | printf("intr=%x\n", (uint32_t) d->intr);
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244 | 1ba13a5d | edgar_igl | printf("out_eop=%x\n", (uint32_t) d->out_eop);
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245 | 1ba13a5d | edgar_igl | printf("in_eop=%x\n", (uint32_t) d->in_eop);
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246 | 1ba13a5d | edgar_igl | printf("eol=%x\n", (uint32_t) d->eol);
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247 | 1ba13a5d | edgar_igl | } |
248 | d297f464 | edgar_igl | #endif
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249 | 1ba13a5d | edgar_igl | |
250 | 1ba13a5d | edgar_igl | static void channel_load_c(struct fs_dma_ctrl *ctrl, int c) |
251 | 1ba13a5d | edgar_igl | { |
252 | 1ba13a5d | edgar_igl | target_phys_addr_t addr = channel_reg(ctrl, c, RW_GROUP_DOWN); |
253 | 1ba13a5d | edgar_igl | |
254 | 1ba13a5d | edgar_igl | /* Load and decode. FIXME: handle endianness. */
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255 | 1ba13a5d | edgar_igl | cpu_physical_memory_read (addr, |
256 | 1ba13a5d | edgar_igl | (void *) &ctrl->channels[c].current_c,
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257 | 1ba13a5d | edgar_igl | sizeof ctrl->channels[c].current_c);
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258 | 1ba13a5d | edgar_igl | |
259 | 1ba13a5d | edgar_igl | D(dump_c(c, &ctrl->channels[c].current_c)); |
260 | 1ba13a5d | edgar_igl | /* I guess this should update the current pos. */
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261 | d297f464 | edgar_igl | ctrl->channels[c].regs[RW_SAVED_DATA] = |
262 | d297f464 | edgar_igl | (uint32_t)(unsigned long)ctrl->channels[c].current_c.saved_data; |
263 | 1ba13a5d | edgar_igl | ctrl->channels[c].regs[RW_SAVED_DATA_BUF] = |
264 | d297f464 | edgar_igl | (uint32_t)(unsigned long)ctrl->channels[c].current_c.saved_data_buf; |
265 | 1ba13a5d | edgar_igl | } |
266 | 1ba13a5d | edgar_igl | |
267 | 1ba13a5d | edgar_igl | static void channel_load_d(struct fs_dma_ctrl *ctrl, int c) |
268 | 1ba13a5d | edgar_igl | { |
269 | 1ba13a5d | edgar_igl | target_phys_addr_t addr = channel_reg(ctrl, c, RW_SAVED_DATA); |
270 | 1ba13a5d | edgar_igl | |
271 | 1ba13a5d | edgar_igl | /* Load and decode. FIXME: handle endianness. */
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272 | a8303d18 | edgar_igl | D(printf("%s ch=%d addr=%x\n", __func__, c, addr));
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273 | 1ba13a5d | edgar_igl | cpu_physical_memory_read (addr, |
274 | 1ba13a5d | edgar_igl | (void *) &ctrl->channels[c].current_d,
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275 | 1ba13a5d | edgar_igl | sizeof ctrl->channels[c].current_d);
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276 | 1ba13a5d | edgar_igl | |
277 | 1ba13a5d | edgar_igl | D(dump_d(c, &ctrl->channels[c].current_d)); |
278 | fa1bdde4 | edgar_igl | ctrl->channels[c].regs[RW_DATA] = addr; |
279 | a8303d18 | edgar_igl | } |
280 | a8303d18 | edgar_igl | |
281 | a8303d18 | edgar_igl | static void channel_store_c(struct fs_dma_ctrl *ctrl, int c) |
282 | a8303d18 | edgar_igl | { |
283 | a8303d18 | edgar_igl | target_phys_addr_t addr = channel_reg(ctrl, c, RW_GROUP_DOWN); |
284 | a8303d18 | edgar_igl | |
285 | a8303d18 | edgar_igl | /* Encode and store. FIXME: handle endianness. */
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286 | a8303d18 | edgar_igl | D(printf("%s ch=%d addr=%x\n", __func__, c, addr));
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287 | a8303d18 | edgar_igl | D(dump_d(c, &ctrl->channels[c].current_d)); |
288 | a8303d18 | edgar_igl | cpu_physical_memory_write (addr, |
289 | a8303d18 | edgar_igl | (void *) &ctrl->channels[c].current_c,
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290 | a8303d18 | edgar_igl | sizeof ctrl->channels[c].current_c);
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291 | 1ba13a5d | edgar_igl | } |
292 | 1ba13a5d | edgar_igl | |
293 | 1ba13a5d | edgar_igl | static void channel_store_d(struct fs_dma_ctrl *ctrl, int c) |
294 | 1ba13a5d | edgar_igl | { |
295 | 1ba13a5d | edgar_igl | target_phys_addr_t addr = channel_reg(ctrl, c, RW_SAVED_DATA); |
296 | 1ba13a5d | edgar_igl | |
297 | a8303d18 | edgar_igl | /* Encode and store. FIXME: handle endianness. */
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298 | a8303d18 | edgar_igl | D(printf("%s ch=%d addr=%x\n", __func__, c, addr));
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299 | 1ba13a5d | edgar_igl | cpu_physical_memory_write (addr, |
300 | 1ba13a5d | edgar_igl | (void *) &ctrl->channels[c].current_d,
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301 | 1ba13a5d | edgar_igl | sizeof ctrl->channels[c].current_d);
|
302 | 1ba13a5d | edgar_igl | } |
303 | 1ba13a5d | edgar_igl | |
304 | 1ba13a5d | edgar_igl | static inline void channel_stop(struct fs_dma_ctrl *ctrl, int c) |
305 | 1ba13a5d | edgar_igl | { |
306 | 1ba13a5d | edgar_igl | /* FIXME: */
|
307 | 1ba13a5d | edgar_igl | } |
308 | 1ba13a5d | edgar_igl | |
309 | 1ba13a5d | edgar_igl | static inline void channel_start(struct fs_dma_ctrl *ctrl, int c) |
310 | 1ba13a5d | edgar_igl | { |
311 | 1ba13a5d | edgar_igl | if (ctrl->channels[c].client)
|
312 | 1ba13a5d | edgar_igl | { |
313 | 1ba13a5d | edgar_igl | ctrl->channels[c].eol = 0;
|
314 | 1ba13a5d | edgar_igl | ctrl->channels[c].state = RUNNING; |
315 | 1ba13a5d | edgar_igl | } else
|
316 | 1ba13a5d | edgar_igl | printf("WARNING: starting DMA ch %d with no client\n", c);
|
317 | 1ba13a5d | edgar_igl | } |
318 | 1ba13a5d | edgar_igl | |
319 | 1ba13a5d | edgar_igl | static void channel_continue(struct fs_dma_ctrl *ctrl, int c) |
320 | 1ba13a5d | edgar_igl | { |
321 | 1ba13a5d | edgar_igl | if (!channel_en(ctrl, c)
|
322 | 1ba13a5d | edgar_igl | || channel_stopped(ctrl, c) |
323 | 1ba13a5d | edgar_igl | || ctrl->channels[c].state != RUNNING |
324 | 1ba13a5d | edgar_igl | /* Only reload the current data descriptor if it has eol set. */
|
325 | 1ba13a5d | edgar_igl | || !ctrl->channels[c].current_d.eol) { |
326 | 1ba13a5d | edgar_igl | D(printf("continue failed ch=%d state=%d stopped=%d en=%d eol=%d\n",
|
327 | 1ba13a5d | edgar_igl | c, ctrl->channels[c].state, |
328 | 1ba13a5d | edgar_igl | channel_stopped(ctrl, c), |
329 | 1ba13a5d | edgar_igl | channel_en(ctrl,c), |
330 | 1ba13a5d | edgar_igl | ctrl->channels[c].eol)); |
331 | 1ba13a5d | edgar_igl | D(dump_d(c, &ctrl->channels[c].current_d)); |
332 | 1ba13a5d | edgar_igl | return;
|
333 | 1ba13a5d | edgar_igl | } |
334 | 1ba13a5d | edgar_igl | |
335 | 1ba13a5d | edgar_igl | /* Reload the current descriptor. */
|
336 | 1ba13a5d | edgar_igl | channel_load_d(ctrl, c); |
337 | 1ba13a5d | edgar_igl | |
338 | 1ba13a5d | edgar_igl | /* If the current descriptor cleared the eol flag and we had already
|
339 | 1ba13a5d | edgar_igl | reached eol state, do the continue. */
|
340 | 1ba13a5d | edgar_igl | if (!ctrl->channels[c].current_d.eol && ctrl->channels[c].eol) {
|
341 | a8303d18 | edgar_igl | D(printf("continue %d ok %p\n", c,
|
342 | 1ba13a5d | edgar_igl | ctrl->channels[c].current_d.next)); |
343 | 1ba13a5d | edgar_igl | ctrl->channels[c].regs[RW_SAVED_DATA] = |
344 | d297f464 | edgar_igl | (uint32_t)(unsigned long)ctrl->channels[c].current_d.next; |
345 | 1ba13a5d | edgar_igl | channel_load_d(ctrl, c); |
346 | 1ba13a5d | edgar_igl | channel_start(ctrl, c); |
347 | 1ba13a5d | edgar_igl | } |
348 | a8303d18 | edgar_igl | ctrl->channels[c].regs[RW_SAVED_DATA_BUF] = |
349 | d297f464 | edgar_igl | (uint32_t)(unsigned long)ctrl->channels[c].current_d.buf; |
350 | 1ba13a5d | edgar_igl | } |
351 | 1ba13a5d | edgar_igl | |
352 | 1ba13a5d | edgar_igl | static void channel_stream_cmd(struct fs_dma_ctrl *ctrl, int c, uint32_t v) |
353 | 1ba13a5d | edgar_igl | { |
354 | 1ba13a5d | edgar_igl | unsigned int cmd = v & ((1 << 10) - 1); |
355 | 1ba13a5d | edgar_igl | |
356 | d27b2e50 | edgar_igl | D(printf("%s ch=%d cmd=%x\n",
|
357 | d27b2e50 | edgar_igl | __func__, c, cmd)); |
358 | 1ba13a5d | edgar_igl | if (cmd & regk_dma_load_d) {
|
359 | 1ba13a5d | edgar_igl | channel_load_d(ctrl, c); |
360 | 1ba13a5d | edgar_igl | if (cmd & regk_dma_burst)
|
361 | 1ba13a5d | edgar_igl | channel_start(ctrl, c); |
362 | 1ba13a5d | edgar_igl | } |
363 | 1ba13a5d | edgar_igl | |
364 | 1ba13a5d | edgar_igl | if (cmd & regk_dma_load_c) {
|
365 | 1ba13a5d | edgar_igl | channel_load_c(ctrl, c); |
366 | a8303d18 | edgar_igl | channel_start(ctrl, c); |
367 | 1ba13a5d | edgar_igl | } |
368 | 1ba13a5d | edgar_igl | } |
369 | 1ba13a5d | edgar_igl | |
370 | 1ba13a5d | edgar_igl | static void channel_update_irq(struct fs_dma_ctrl *ctrl, int c) |
371 | 1ba13a5d | edgar_igl | { |
372 | 1ba13a5d | edgar_igl | D(printf("%s %d\n", __func__, c));
|
373 | 1ba13a5d | edgar_igl | ctrl->channels[c].regs[R_INTR] &= |
374 | 1ba13a5d | edgar_igl | ~(ctrl->channels[c].regs[RW_ACK_INTR]); |
375 | 1ba13a5d | edgar_igl | |
376 | 1ba13a5d | edgar_igl | ctrl->channels[c].regs[R_MASKED_INTR] = |
377 | 1ba13a5d | edgar_igl | ctrl->channels[c].regs[R_INTR] |
378 | 1ba13a5d | edgar_igl | & ctrl->channels[c].regs[RW_INTR_MASK]; |
379 | 1ba13a5d | edgar_igl | |
380 | 1ba13a5d | edgar_igl | D(printf("%s: chan=%d masked_intr=%x\n", __func__,
|
381 | 1ba13a5d | edgar_igl | c, |
382 | 1ba13a5d | edgar_igl | ctrl->channels[c].regs[R_MASKED_INTR])); |
383 | 1ba13a5d | edgar_igl | |
384 | 1ba13a5d | edgar_igl | if (ctrl->channels[c].regs[R_MASKED_INTR])
|
385 | 1ba13a5d | edgar_igl | qemu_irq_raise(ctrl->channels[c].irq[0]);
|
386 | 1ba13a5d | edgar_igl | else
|
387 | 1ba13a5d | edgar_igl | qemu_irq_lower(ctrl->channels[c].irq[0]);
|
388 | 1ba13a5d | edgar_igl | } |
389 | 1ba13a5d | edgar_igl | |
390 | 1ba13a5d | edgar_igl | static void channel_out_run(struct fs_dma_ctrl *ctrl, int c) |
391 | 1ba13a5d | edgar_igl | { |
392 | 1ba13a5d | edgar_igl | uint32_t len; |
393 | 1ba13a5d | edgar_igl | uint32_t saved_data_buf; |
394 | 1ba13a5d | edgar_igl | unsigned char buf[2 * 1024]; |
395 | 1ba13a5d | edgar_igl | |
396 | 1ba13a5d | edgar_igl | if (ctrl->channels[c].eol == 1) |
397 | 1ba13a5d | edgar_igl | return;
|
398 | 1ba13a5d | edgar_igl | |
399 | 1ba13a5d | edgar_igl | saved_data_buf = channel_reg(ctrl, c, RW_SAVED_DATA_BUF); |
400 | 1ba13a5d | edgar_igl | |
401 | a8303d18 | edgar_igl | D(fprintf(logfile, "ch=%d buf=%x after=%x saved_data_buf=%x\n",
|
402 | a8303d18 | edgar_igl | c, |
403 | 1ba13a5d | edgar_igl | (uint32_t)ctrl->channels[c].current_d.buf, |
404 | 1ba13a5d | edgar_igl | (uint32_t)ctrl->channels[c].current_d.after, |
405 | 1ba13a5d | edgar_igl | saved_data_buf)); |
406 | 1ba13a5d | edgar_igl | |
407 | d297f464 | edgar_igl | len = (uint32_t)(unsigned long) ctrl->channels[c].current_d.after; |
408 | a8303d18 | edgar_igl | len -= saved_data_buf; |
409 | a8303d18 | edgar_igl | |
410 | a8303d18 | edgar_igl | if (len > sizeof buf) |
411 | a8303d18 | edgar_igl | len = sizeof buf;
|
412 | a8303d18 | edgar_igl | cpu_physical_memory_read (saved_data_buf, buf, len); |
413 | a8303d18 | edgar_igl | |
414 | a8303d18 | edgar_igl | D(printf("channel %d pushes %x %u bytes\n", c,
|
415 | a8303d18 | edgar_igl | saved_data_buf, len)); |
416 | a8303d18 | edgar_igl | |
417 | a8303d18 | edgar_igl | if (ctrl->channels[c].client->client.push)
|
418 | a8303d18 | edgar_igl | ctrl->channels[c].client->client.push( |
419 | a8303d18 | edgar_igl | ctrl->channels[c].client->client.opaque, buf, len); |
420 | a8303d18 | edgar_igl | else
|
421 | a8303d18 | edgar_igl | printf("WARNING: DMA ch%d dataloss, no attached client.\n", c);
|
422 | a8303d18 | edgar_igl | |
423 | a8303d18 | edgar_igl | saved_data_buf += len; |
424 | a8303d18 | edgar_igl | |
425 | d297f464 | edgar_igl | if (saved_data_buf ==
|
426 | d297f464 | edgar_igl | (uint32_t)(unsigned long)ctrl->channels[c].current_d.after) { |
427 | 1ba13a5d | edgar_igl | /* Done. Step to next. */
|
428 | 1ba13a5d | edgar_igl | if (ctrl->channels[c].current_d.out_eop) {
|
429 | 1ba13a5d | edgar_igl | /* TODO: signal eop to the client. */
|
430 | 1ba13a5d | edgar_igl | D(printf("signal eop\n"));
|
431 | 1ba13a5d | edgar_igl | } |
432 | 1ba13a5d | edgar_igl | if (ctrl->channels[c].current_d.intr) {
|
433 | 1ba13a5d | edgar_igl | /* TODO: signal eop to the client. */
|
434 | 1ba13a5d | edgar_igl | /* data intr. */
|
435 | 1ba13a5d | edgar_igl | D(printf("signal intr\n"));
|
436 | 1ba13a5d | edgar_igl | ctrl->channels[c].regs[R_INTR] |= (1 << 2); |
437 | 1ba13a5d | edgar_igl | channel_update_irq(ctrl, c); |
438 | 1ba13a5d | edgar_igl | } |
439 | 1ba13a5d | edgar_igl | if (ctrl->channels[c].current_d.eol) {
|
440 | 1ba13a5d | edgar_igl | D(printf("channel %d EOL\n", c));
|
441 | 1ba13a5d | edgar_igl | ctrl->channels[c].eol = 1;
|
442 | a8303d18 | edgar_igl | |
443 | a8303d18 | edgar_igl | /* Mark the context as disabled. */
|
444 | a8303d18 | edgar_igl | ctrl->channels[c].current_c.dis = 1;
|
445 | a8303d18 | edgar_igl | channel_store_c(ctrl, c); |
446 | a8303d18 | edgar_igl | |
447 | 1ba13a5d | edgar_igl | channel_stop(ctrl, c); |
448 | 1ba13a5d | edgar_igl | } else {
|
449 | 1ba13a5d | edgar_igl | ctrl->channels[c].regs[RW_SAVED_DATA] = |
450 | d297f464 | edgar_igl | (uint32_t)(unsigned long) ctrl->channels[c].current_d.next; |
451 | 1ba13a5d | edgar_igl | /* Load new descriptor. */
|
452 | 1ba13a5d | edgar_igl | channel_load_d(ctrl, c); |
453 | d297f464 | edgar_igl | saved_data_buf = (uint32_t)(unsigned long) |
454 | a8303d18 | edgar_igl | ctrl->channels[c].current_d.buf; |
455 | 1ba13a5d | edgar_igl | } |
456 | 1ba13a5d | edgar_igl | |
457 | 1ba13a5d | edgar_igl | channel_store_d(ctrl, c); |
458 | a8303d18 | edgar_igl | ctrl->channels[c].regs[RW_SAVED_DATA_BUF] = saved_data_buf; |
459 | 1ba13a5d | edgar_igl | D(dump_d(c, &ctrl->channels[c].current_d)); |
460 | 1ba13a5d | edgar_igl | } |
461 | a8303d18 | edgar_igl | ctrl->channels[c].regs[RW_SAVED_DATA_BUF] = saved_data_buf; |
462 | 1ba13a5d | edgar_igl | } |
463 | 1ba13a5d | edgar_igl | |
464 | 1ba13a5d | edgar_igl | static int channel_in_process(struct fs_dma_ctrl *ctrl, int c, |
465 | 1ba13a5d | edgar_igl | unsigned char *buf, int buflen, int eop) |
466 | 1ba13a5d | edgar_igl | { |
467 | 1ba13a5d | edgar_igl | uint32_t len; |
468 | 1ba13a5d | edgar_igl | uint32_t saved_data_buf; |
469 | 1ba13a5d | edgar_igl | |
470 | 1ba13a5d | edgar_igl | if (ctrl->channels[c].eol == 1) |
471 | 1ba13a5d | edgar_igl | return 0; |
472 | 1ba13a5d | edgar_igl | |
473 | 1ba13a5d | edgar_igl | saved_data_buf = channel_reg(ctrl, c, RW_SAVED_DATA_BUF); |
474 | d297f464 | edgar_igl | len = (uint32_t)(unsigned long) ctrl->channels[c].current_d.after; |
475 | 1ba13a5d | edgar_igl | len -= saved_data_buf; |
476 | 1ba13a5d | edgar_igl | |
477 | 1ba13a5d | edgar_igl | if (len > buflen)
|
478 | 1ba13a5d | edgar_igl | len = buflen; |
479 | 1ba13a5d | edgar_igl | |
480 | 1ba13a5d | edgar_igl | cpu_physical_memory_write (saved_data_buf, buf, len); |
481 | 1ba13a5d | edgar_igl | saved_data_buf += len; |
482 | 1ba13a5d | edgar_igl | |
483 | d297f464 | edgar_igl | if (saved_data_buf ==
|
484 | d297f464 | edgar_igl | (uint32_t)(unsigned long)ctrl->channels[c].current_d.after |
485 | 1ba13a5d | edgar_igl | || eop) { |
486 | 1ba13a5d | edgar_igl | uint32_t r_intr = ctrl->channels[c].regs[R_INTR]; |
487 | 1ba13a5d | edgar_igl | |
488 | 1ba13a5d | edgar_igl | D(printf("in dscr end len=%d\n",
|
489 | 1ba13a5d | edgar_igl | ctrl->channels[c].current_d.after |
490 | 1ba13a5d | edgar_igl | - ctrl->channels[c].current_d.buf)); |
491 | 1ba13a5d | edgar_igl | ctrl->channels[c].current_d.after = |
492 | d297f464 | edgar_igl | (void *)(unsigned long) saved_data_buf; |
493 | 1ba13a5d | edgar_igl | |
494 | 1ba13a5d | edgar_igl | /* Done. Step to next. */
|
495 | 1ba13a5d | edgar_igl | if (ctrl->channels[c].current_d.intr) {
|
496 | 1ba13a5d | edgar_igl | /* TODO: signal eop to the client. */
|
497 | 1ba13a5d | edgar_igl | /* data intr. */
|
498 | 1ba13a5d | edgar_igl | ctrl->channels[c].regs[R_INTR] |= 3;
|
499 | 1ba13a5d | edgar_igl | } |
500 | 1ba13a5d | edgar_igl | if (eop) {
|
501 | 1ba13a5d | edgar_igl | ctrl->channels[c].current_d.in_eop = 1;
|
502 | 1ba13a5d | edgar_igl | ctrl->channels[c].regs[R_INTR] |= 8;
|
503 | 1ba13a5d | edgar_igl | } |
504 | 1ba13a5d | edgar_igl | if (r_intr != ctrl->channels[c].regs[R_INTR])
|
505 | 1ba13a5d | edgar_igl | channel_update_irq(ctrl, c); |
506 | 1ba13a5d | edgar_igl | |
507 | 1ba13a5d | edgar_igl | channel_store_d(ctrl, c); |
508 | 1ba13a5d | edgar_igl | D(dump_d(c, &ctrl->channels[c].current_d)); |
509 | 1ba13a5d | edgar_igl | |
510 | 1ba13a5d | edgar_igl | if (ctrl->channels[c].current_d.eol) {
|
511 | 1ba13a5d | edgar_igl | D(printf("channel %d EOL\n", c));
|
512 | 1ba13a5d | edgar_igl | ctrl->channels[c].eol = 1;
|
513 | a8303d18 | edgar_igl | |
514 | a8303d18 | edgar_igl | /* Mark the context as disabled. */
|
515 | a8303d18 | edgar_igl | ctrl->channels[c].current_c.dis = 1;
|
516 | a8303d18 | edgar_igl | channel_store_c(ctrl, c); |
517 | a8303d18 | edgar_igl | |
518 | 1ba13a5d | edgar_igl | channel_stop(ctrl, c); |
519 | 1ba13a5d | edgar_igl | } else {
|
520 | 1ba13a5d | edgar_igl | ctrl->channels[c].regs[RW_SAVED_DATA] = |
521 | d297f464 | edgar_igl | (uint32_t)(unsigned long) ctrl->channels[c].current_d.next; |
522 | 1ba13a5d | edgar_igl | /* Load new descriptor. */
|
523 | 1ba13a5d | edgar_igl | channel_load_d(ctrl, c); |
524 | d297f464 | edgar_igl | saved_data_buf = (uint32_t)(unsigned long) |
525 | a8303d18 | edgar_igl | ctrl->channels[c].current_d.buf; |
526 | 1ba13a5d | edgar_igl | } |
527 | 1ba13a5d | edgar_igl | } |
528 | 1ba13a5d | edgar_igl | |
529 | 1ba13a5d | edgar_igl | ctrl->channels[c].regs[RW_SAVED_DATA_BUF] = saved_data_buf; |
530 | 1ba13a5d | edgar_igl | return len;
|
531 | 1ba13a5d | edgar_igl | } |
532 | 1ba13a5d | edgar_igl | |
533 | 1ba13a5d | edgar_igl | static inline void channel_in_run(struct fs_dma_ctrl *ctrl, int c) |
534 | 1ba13a5d | edgar_igl | { |
535 | 1ba13a5d | edgar_igl | if (ctrl->channels[c].client->client.pull)
|
536 | 1ba13a5d | edgar_igl | ctrl->channels[c].client->client.pull( |
537 | 1ba13a5d | edgar_igl | ctrl->channels[c].client->client.opaque); |
538 | 1ba13a5d | edgar_igl | } |
539 | 1ba13a5d | edgar_igl | |
540 | 1ba13a5d | edgar_igl | static uint32_t dma_rinvalid (void *opaque, target_phys_addr_t addr) |
541 | 1ba13a5d | edgar_igl | { |
542 | 1ba13a5d | edgar_igl | struct fs_dma_ctrl *ctrl = opaque;
|
543 | 1ba13a5d | edgar_igl | CPUState *env = ctrl->env; |
544 | d27b2e50 | edgar_igl | cpu_abort(env, "Unsupported short access. reg=" TARGET_FMT_plx "\n", |
545 | d27b2e50 | edgar_igl | addr); |
546 | 1ba13a5d | edgar_igl | return 0; |
547 | 1ba13a5d | edgar_igl | } |
548 | 1ba13a5d | edgar_igl | |
549 | 1ba13a5d | edgar_igl | static uint32_t
|
550 | 1ba13a5d | edgar_igl | dma_readl (void *opaque, target_phys_addr_t addr)
|
551 | 1ba13a5d | edgar_igl | { |
552 | 1ba13a5d | edgar_igl | struct fs_dma_ctrl *ctrl = opaque;
|
553 | 1ba13a5d | edgar_igl | int c;
|
554 | 1ba13a5d | edgar_igl | uint32_t r = 0;
|
555 | 1ba13a5d | edgar_igl | |
556 | 1ba13a5d | edgar_igl | /* Make addr relative to this instances base. */
|
557 | 1ba13a5d | edgar_igl | c = fs_channel(ctrl->base, addr); |
558 | a8303d18 | edgar_igl | addr &= 0x1fff;
|
559 | 1ba13a5d | edgar_igl | switch (addr)
|
560 | a8303d18 | edgar_igl | { |
561 | 1ba13a5d | edgar_igl | case RW_STAT:
|
562 | 1ba13a5d | edgar_igl | r = ctrl->channels[c].state & 7;
|
563 | 1ba13a5d | edgar_igl | r |= ctrl->channels[c].eol << 5;
|
564 | 1ba13a5d | edgar_igl | r |= ctrl->channels[c].stream_cmd_src << 8;
|
565 | 1ba13a5d | edgar_igl | break;
|
566 | 1ba13a5d | edgar_igl | |
567 | a8303d18 | edgar_igl | default:
|
568 | 1ba13a5d | edgar_igl | r = ctrl->channels[c].regs[addr]; |
569 | d27b2e50 | edgar_igl | D(printf ("%s c=%d addr=%x\n",
|
570 | d27b2e50 | edgar_igl | __func__, c, addr)); |
571 | a8303d18 | edgar_igl | break;
|
572 | a8303d18 | edgar_igl | } |
573 | 1ba13a5d | edgar_igl | return r;
|
574 | 1ba13a5d | edgar_igl | } |
575 | 1ba13a5d | edgar_igl | |
576 | 1ba13a5d | edgar_igl | static void |
577 | 1ba13a5d | edgar_igl | dma_winvalid (void *opaque, target_phys_addr_t addr, uint32_t value)
|
578 | 1ba13a5d | edgar_igl | { |
579 | 1ba13a5d | edgar_igl | struct fs_dma_ctrl *ctrl = opaque;
|
580 | 1ba13a5d | edgar_igl | CPUState *env = ctrl->env; |
581 | d27b2e50 | edgar_igl | cpu_abort(env, "Unsupported short access. reg=" TARGET_FMT_plx "\n", |
582 | d27b2e50 | edgar_igl | addr); |
583 | 1ba13a5d | edgar_igl | } |
584 | 1ba13a5d | edgar_igl | |
585 | 1ba13a5d | edgar_igl | static void |
586 | 1ba13a5d | edgar_igl | dma_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
|
587 | 1ba13a5d | edgar_igl | { |
588 | 1ba13a5d | edgar_igl | struct fs_dma_ctrl *ctrl = opaque;
|
589 | 1ba13a5d | edgar_igl | int c;
|
590 | 1ba13a5d | edgar_igl | |
591 | 1ba13a5d | edgar_igl | /* Make addr relative to this instances base. */
|
592 | 1ba13a5d | edgar_igl | c = fs_channel(ctrl->base, addr); |
593 | 1ba13a5d | edgar_igl | addr &= 0x1fff;
|
594 | 1ba13a5d | edgar_igl | switch (addr)
|
595 | a8303d18 | edgar_igl | { |
596 | 1ba13a5d | edgar_igl | case RW_DATA:
|
597 | fa1bdde4 | edgar_igl | ctrl->channels[c].regs[addr] = value; |
598 | 1ba13a5d | edgar_igl | break;
|
599 | 1ba13a5d | edgar_igl | |
600 | 1ba13a5d | edgar_igl | case RW_CFG:
|
601 | 1ba13a5d | edgar_igl | ctrl->channels[c].regs[addr] = value; |
602 | 1ba13a5d | edgar_igl | break;
|
603 | 1ba13a5d | edgar_igl | case RW_CMD:
|
604 | 1ba13a5d | edgar_igl | /* continue. */
|
605 | 1ba13a5d | edgar_igl | ctrl->channels[c].regs[addr] = value; |
606 | 1ba13a5d | edgar_igl | channel_continue(ctrl, c); |
607 | 1ba13a5d | edgar_igl | break;
|
608 | 1ba13a5d | edgar_igl | |
609 | 1ba13a5d | edgar_igl | case RW_SAVED_DATA:
|
610 | 1ba13a5d | edgar_igl | case RW_SAVED_DATA_BUF:
|
611 | 1ba13a5d | edgar_igl | case RW_GROUP:
|
612 | 1ba13a5d | edgar_igl | case RW_GROUP_DOWN:
|
613 | 1ba13a5d | edgar_igl | ctrl->channels[c].regs[addr] = value; |
614 | 1ba13a5d | edgar_igl | break;
|
615 | 1ba13a5d | edgar_igl | |
616 | 1ba13a5d | edgar_igl | case RW_ACK_INTR:
|
617 | 1ba13a5d | edgar_igl | case RW_INTR_MASK:
|
618 | 1ba13a5d | edgar_igl | ctrl->channels[c].regs[addr] = value; |
619 | 1ba13a5d | edgar_igl | channel_update_irq(ctrl, c); |
620 | 1ba13a5d | edgar_igl | if (addr == RW_ACK_INTR)
|
621 | 1ba13a5d | edgar_igl | ctrl->channels[c].regs[RW_ACK_INTR] = 0;
|
622 | 1ba13a5d | edgar_igl | break;
|
623 | 1ba13a5d | edgar_igl | |
624 | 1ba13a5d | edgar_igl | case RW_STREAM_CMD:
|
625 | 1ba13a5d | edgar_igl | ctrl->channels[c].regs[addr] = value; |
626 | d27b2e50 | edgar_igl | D(printf("stream_cmd ch=%d\n", c));
|
627 | 1ba13a5d | edgar_igl | channel_stream_cmd(ctrl, c, value); |
628 | 1ba13a5d | edgar_igl | break;
|
629 | 1ba13a5d | edgar_igl | |
630 | a8303d18 | edgar_igl | default:
|
631 | d27b2e50 | edgar_igl | D(printf ("%s c=%d %x %x\n", __func__, c, addr));
|
632 | a8303d18 | edgar_igl | break;
|
633 | 1ba13a5d | edgar_igl | } |
634 | 1ba13a5d | edgar_igl | } |
635 | 1ba13a5d | edgar_igl | |
636 | 1ba13a5d | edgar_igl | static CPUReadMemoryFunc *dma_read[] = {
|
637 | 1ba13a5d | edgar_igl | &dma_rinvalid, |
638 | 1ba13a5d | edgar_igl | &dma_rinvalid, |
639 | 1ba13a5d | edgar_igl | &dma_readl, |
640 | 1ba13a5d | edgar_igl | }; |
641 | 1ba13a5d | edgar_igl | |
642 | 1ba13a5d | edgar_igl | static CPUWriteMemoryFunc *dma_write[] = {
|
643 | 1ba13a5d | edgar_igl | &dma_winvalid, |
644 | 1ba13a5d | edgar_igl | &dma_winvalid, |
645 | 1ba13a5d | edgar_igl | &dma_writel, |
646 | 1ba13a5d | edgar_igl | }; |
647 | 1ba13a5d | edgar_igl | |
648 | 1ba13a5d | edgar_igl | void etraxfs_dmac_run(void *opaque) |
649 | 1ba13a5d | edgar_igl | { |
650 | 1ba13a5d | edgar_igl | struct fs_dma_ctrl *ctrl = opaque;
|
651 | 1ba13a5d | edgar_igl | int i;
|
652 | 1ba13a5d | edgar_igl | int p = 0; |
653 | 1ba13a5d | edgar_igl | |
654 | 1ba13a5d | edgar_igl | for (i = 0; |
655 | 1ba13a5d | edgar_igl | i < ctrl->nr_channels; |
656 | 1ba13a5d | edgar_igl | i++) |
657 | 1ba13a5d | edgar_igl | { |
658 | 1ba13a5d | edgar_igl | if (ctrl->channels[i].state == RUNNING)
|
659 | 1ba13a5d | edgar_igl | { |
660 | 1ba13a5d | edgar_igl | p++; |
661 | 1ba13a5d | edgar_igl | if (ctrl->channels[i].input)
|
662 | 1ba13a5d | edgar_igl | channel_in_run(ctrl, i); |
663 | 1ba13a5d | edgar_igl | else
|
664 | 1ba13a5d | edgar_igl | channel_out_run(ctrl, i); |
665 | 1ba13a5d | edgar_igl | } |
666 | 1ba13a5d | edgar_igl | } |
667 | 1ba13a5d | edgar_igl | } |
668 | 1ba13a5d | edgar_igl | |
669 | 1ba13a5d | edgar_igl | int etraxfs_dmac_input(struct etraxfs_dma_client *client, |
670 | 1ba13a5d | edgar_igl | void *buf, int len, int eop) |
671 | 1ba13a5d | edgar_igl | { |
672 | 1ba13a5d | edgar_igl | return channel_in_process(client->ctrl, client->channel,
|
673 | 1ba13a5d | edgar_igl | buf, len, eop); |
674 | 1ba13a5d | edgar_igl | } |
675 | 1ba13a5d | edgar_igl | |
676 | 1ba13a5d | edgar_igl | /* Connect an IRQ line with a channel. */
|
677 | 1ba13a5d | edgar_igl | void etraxfs_dmac_connect(void *opaque, int c, qemu_irq *line, int input) |
678 | 1ba13a5d | edgar_igl | { |
679 | 1ba13a5d | edgar_igl | struct fs_dma_ctrl *ctrl = opaque;
|
680 | 1ba13a5d | edgar_igl | ctrl->channels[c].irq = line; |
681 | 1ba13a5d | edgar_igl | ctrl->channels[c].input = input; |
682 | 1ba13a5d | edgar_igl | } |
683 | 1ba13a5d | edgar_igl | |
684 | 1ba13a5d | edgar_igl | void etraxfs_dmac_connect_client(void *opaque, int c, |
685 | 1ba13a5d | edgar_igl | struct etraxfs_dma_client *cl)
|
686 | 1ba13a5d | edgar_igl | { |
687 | 1ba13a5d | edgar_igl | struct fs_dma_ctrl *ctrl = opaque;
|
688 | 1ba13a5d | edgar_igl | cl->ctrl = ctrl; |
689 | 1ba13a5d | edgar_igl | cl->channel = c; |
690 | 1ba13a5d | edgar_igl | ctrl->channels[c].client = cl; |
691 | 1ba13a5d | edgar_igl | } |
692 | 1ba13a5d | edgar_igl | |
693 | 1ba13a5d | edgar_igl | |
694 | fa1bdde4 | edgar_igl | static void *etraxfs_dmac; |
695 | fa1bdde4 | edgar_igl | void DMA_run(void) |
696 | fa1bdde4 | edgar_igl | { |
697 | fa1bdde4 | edgar_igl | if (etraxfs_dmac)
|
698 | fa1bdde4 | edgar_igl | etraxfs_dmac_run(etraxfs_dmac); |
699 | fa1bdde4 | edgar_igl | } |
700 | fa1bdde4 | edgar_igl | |
701 | 1ba13a5d | edgar_igl | void *etraxfs_dmac_init(CPUState *env,
|
702 | 1ba13a5d | edgar_igl | target_phys_addr_t base, int nr_channels)
|
703 | 1ba13a5d | edgar_igl | { |
704 | 1ba13a5d | edgar_igl | struct fs_dma_ctrl *ctrl = NULL; |
705 | 1ba13a5d | edgar_igl | int i;
|
706 | 1ba13a5d | edgar_igl | |
707 | 1ba13a5d | edgar_igl | ctrl = qemu_mallocz(sizeof *ctrl);
|
708 | 1ba13a5d | edgar_igl | if (!ctrl)
|
709 | 1ba13a5d | edgar_igl | return NULL; |
710 | 1ba13a5d | edgar_igl | |
711 | 1ba13a5d | edgar_igl | ctrl->base = base; |
712 | 1ba13a5d | edgar_igl | ctrl->env = env; |
713 | 1ba13a5d | edgar_igl | ctrl->nr_channels = nr_channels; |
714 | 1ba13a5d | edgar_igl | ctrl->channels = qemu_mallocz(sizeof ctrl->channels[0] * nr_channels); |
715 | 1ba13a5d | edgar_igl | if (!ctrl->channels)
|
716 | 1ba13a5d | edgar_igl | goto err;
|
717 | 1ba13a5d | edgar_igl | |
718 | 1ba13a5d | edgar_igl | for (i = 0; i < nr_channels; i++) |
719 | 1ba13a5d | edgar_igl | { |
720 | 1ba13a5d | edgar_igl | ctrl->channels[i].regmap = cpu_register_io_memory(0,
|
721 | 1ba13a5d | edgar_igl | dma_read, |
722 | 1ba13a5d | edgar_igl | dma_write, |
723 | 1ba13a5d | edgar_igl | ctrl); |
724 | 1ba13a5d | edgar_igl | cpu_register_physical_memory (base + i * 0x2000,
|
725 | 1ba13a5d | edgar_igl | sizeof ctrl->channels[i].regs,
|
726 | 1ba13a5d | edgar_igl | ctrl->channels[i].regmap); |
727 | 1ba13a5d | edgar_igl | } |
728 | 1ba13a5d | edgar_igl | |
729 | fa1bdde4 | edgar_igl | /* Hax, we only support one DMA controller at a time. */
|
730 | fa1bdde4 | edgar_igl | etraxfs_dmac = ctrl; |
731 | 1ba13a5d | edgar_igl | return ctrl;
|
732 | 1ba13a5d | edgar_igl | err:
|
733 | 1ba13a5d | edgar_igl | qemu_free(ctrl->channels); |
734 | 1ba13a5d | edgar_igl | qemu_free(ctrl); |
735 | 1ba13a5d | edgar_igl | return NULL; |
736 | 1ba13a5d | edgar_igl | } |