root / hw / lm32_sys.c @ 795928f6
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1 | f19410ca | Michael Walle | /*
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2 | f19410ca | Michael Walle | * QEMU model of the LatticeMico32 system control block.
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3 | f19410ca | Michael Walle | *
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4 | f19410ca | Michael Walle | * Copyright (c) 2010 Michael Walle <michael@walle.cc>
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5 | f19410ca | Michael Walle | *
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6 | f19410ca | Michael Walle | * This library is free software; you can redistribute it and/or
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7 | f19410ca | Michael Walle | * modify it under the terms of the GNU Lesser General Public
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8 | f19410ca | Michael Walle | * License as published by the Free Software Foundation; either
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9 | f19410ca | Michael Walle | * version 2 of the License, or (at your option) any later version.
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10 | f19410ca | Michael Walle | *
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11 | f19410ca | Michael Walle | * This library is distributed in the hope that it will be useful,
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12 | f19410ca | Michael Walle | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | f19410ca | Michael Walle | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | f19410ca | Michael Walle | * Lesser General Public License for more details.
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15 | f19410ca | Michael Walle | *
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16 | f19410ca | Michael Walle | * You should have received a copy of the GNU Lesser General Public
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17 | f19410ca | Michael Walle | * License along with this library; if not, see <http://www.gnu.org/licenses/>.
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18 | f19410ca | Michael Walle | */
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19 | f19410ca | Michael Walle | |
20 | f19410ca | Michael Walle | /*
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21 | f19410ca | Michael Walle | * This model is mainly intended for testing purposes and doesn't fit to any
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22 | f19410ca | Michael Walle | * real hardware. On the one hand it provides a control register (R_CTRL) on
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23 | f19410ca | Michael Walle | * the other hand it supports the lm32 tests.
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24 | f19410ca | Michael Walle | *
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25 | f19410ca | Michael Walle | * A write to the control register causes a system shutdown.
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26 | f19410ca | Michael Walle | * Tests first write the pointer to a test name to the test name register
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27 | f19410ca | Michael Walle | * (R_TESTNAME) and then write a zero to the pass/fail register (R_PASSFAIL) if
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28 | f19410ca | Michael Walle | * the test is passed or any non-zero value to it if the test is failed.
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29 | f19410ca | Michael Walle | */
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30 | f19410ca | Michael Walle | |
31 | f19410ca | Michael Walle | #include "hw.h" |
32 | f19410ca | Michael Walle | #include "sysbus.h" |
33 | f19410ca | Michael Walle | #include "trace.h" |
34 | f19410ca | Michael Walle | #include "qemu-log.h" |
35 | f19410ca | Michael Walle | #include "qemu-error.h" |
36 | f19410ca | Michael Walle | #include "sysemu.h" |
37 | f19410ca | Michael Walle | #include "qemu-log.h" |
38 | f19410ca | Michael Walle | |
39 | f19410ca | Michael Walle | enum {
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40 | f19410ca | Michael Walle | R_CTRL = 0,
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41 | f19410ca | Michael Walle | R_PASSFAIL, |
42 | f19410ca | Michael Walle | R_TESTNAME, |
43 | f19410ca | Michael Walle | R_MAX |
44 | f19410ca | Michael Walle | }; |
45 | f19410ca | Michael Walle | |
46 | f19410ca | Michael Walle | #define MAX_TESTNAME_LEN 16 |
47 | f19410ca | Michael Walle | |
48 | f19410ca | Michael Walle | struct LM32SysState {
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49 | f19410ca | Michael Walle | SysBusDevice busdev; |
50 | f19410ca | Michael Walle | uint32_t base; |
51 | f19410ca | Michael Walle | uint32_t regs[R_MAX]; |
52 | f19410ca | Michael Walle | uint8_t testname[MAX_TESTNAME_LEN]; |
53 | f19410ca | Michael Walle | }; |
54 | f19410ca | Michael Walle | typedef struct LM32SysState LM32SysState; |
55 | f19410ca | Michael Walle | |
56 | f19410ca | Michael Walle | static void copy_testname(LM32SysState *s) |
57 | f19410ca | Michael Walle | { |
58 | f19410ca | Michael Walle | cpu_physical_memory_read(s->regs[R_TESTNAME], s->testname, |
59 | f19410ca | Michael Walle | MAX_TESTNAME_LEN); |
60 | f19410ca | Michael Walle | s->testname[MAX_TESTNAME_LEN - 1] = '\0'; |
61 | f19410ca | Michael Walle | } |
62 | f19410ca | Michael Walle | |
63 | f19410ca | Michael Walle | static void sys_write(void *opaque, target_phys_addr_t addr, uint32_t value) |
64 | f19410ca | Michael Walle | { |
65 | f19410ca | Michael Walle | LM32SysState *s = opaque; |
66 | f19410ca | Michael Walle | char *testname;
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67 | f19410ca | Michael Walle | |
68 | f19410ca | Michael Walle | trace_lm32_sys_memory_write(addr, value); |
69 | f19410ca | Michael Walle | |
70 | f19410ca | Michael Walle | addr >>= 2;
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71 | f19410ca | Michael Walle | switch (addr) {
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72 | f19410ca | Michael Walle | case R_CTRL:
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73 | f19410ca | Michael Walle | qemu_system_shutdown_request(); |
74 | f19410ca | Michael Walle | break;
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75 | f19410ca | Michael Walle | case R_PASSFAIL:
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76 | f19410ca | Michael Walle | s->regs[addr] = value; |
77 | f19410ca | Michael Walle | testname = (char *)s->testname;
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78 | f19410ca | Michael Walle | qemu_log("TC %-16s %s\n", testname, (value) ? "FAILED" : "OK"); |
79 | f19410ca | Michael Walle | break;
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80 | f19410ca | Michael Walle | case R_TESTNAME:
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81 | f19410ca | Michael Walle | s->regs[addr] = value; |
82 | f19410ca | Michael Walle | copy_testname(s); |
83 | f19410ca | Michael Walle | break;
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84 | f19410ca | Michael Walle | |
85 | f19410ca | Michael Walle | default:
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86 | dd3d6775 | Markus Armbruster | error_report("lm32_sys: write access to unknown register 0x"
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87 | f19410ca | Michael Walle | TARGET_FMT_plx, addr << 2);
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88 | f19410ca | Michael Walle | break;
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89 | f19410ca | Michael Walle | } |
90 | f19410ca | Michael Walle | } |
91 | f19410ca | Michael Walle | |
92 | f19410ca | Michael Walle | static CPUReadMemoryFunc * const sys_read_fn[] = { |
93 | f19410ca | Michael Walle | NULL,
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94 | f19410ca | Michael Walle | NULL,
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95 | f19410ca | Michael Walle | NULL,
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96 | f19410ca | Michael Walle | }; |
97 | f19410ca | Michael Walle | |
98 | f19410ca | Michael Walle | static CPUWriteMemoryFunc * const sys_write_fn[] = { |
99 | f19410ca | Michael Walle | NULL,
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100 | f19410ca | Michael Walle | NULL,
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101 | f19410ca | Michael Walle | &sys_write, |
102 | f19410ca | Michael Walle | }; |
103 | f19410ca | Michael Walle | |
104 | f19410ca | Michael Walle | static void sys_reset(DeviceState *d) |
105 | f19410ca | Michael Walle | { |
106 | f19410ca | Michael Walle | LM32SysState *s = container_of(d, LM32SysState, busdev.qdev); |
107 | f19410ca | Michael Walle | int i;
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108 | f19410ca | Michael Walle | |
109 | f19410ca | Michael Walle | for (i = 0; i < R_MAX; i++) { |
110 | f19410ca | Michael Walle | s->regs[i] = 0;
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111 | f19410ca | Michael Walle | } |
112 | f19410ca | Michael Walle | memset(s->testname, 0, MAX_TESTNAME_LEN);
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113 | f19410ca | Michael Walle | } |
114 | f19410ca | Michael Walle | |
115 | f19410ca | Michael Walle | static int lm32_sys_init(SysBusDevice *dev) |
116 | f19410ca | Michael Walle | { |
117 | f19410ca | Michael Walle | LM32SysState *s = FROM_SYSBUS(typeof(*s), dev); |
118 | f19410ca | Michael Walle | int sys_regs;
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119 | f19410ca | Michael Walle | |
120 | f19410ca | Michael Walle | sys_regs = cpu_register_io_memory(sys_read_fn, sys_write_fn, s, |
121 | f19410ca | Michael Walle | DEVICE_NATIVE_ENDIAN); |
122 | f19410ca | Michael Walle | sysbus_init_mmio(dev, R_MAX * 4, sys_regs);
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123 | f19410ca | Michael Walle | |
124 | f19410ca | Michael Walle | /* Note: This device is not created in the board initialization,
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125 | f19410ca | Michael Walle | * instead it has to be added with the -device parameter. Therefore,
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126 | f19410ca | Michael Walle | * the device maps itself. */
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127 | f19410ca | Michael Walle | sysbus_mmio_map(dev, 0, s->base);
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128 | f19410ca | Michael Walle | |
129 | f19410ca | Michael Walle | return 0; |
130 | f19410ca | Michael Walle | } |
131 | f19410ca | Michael Walle | |
132 | f19410ca | Michael Walle | static const VMStateDescription vmstate_lm32_sys = { |
133 | f19410ca | Michael Walle | .name = "lm32-sys",
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134 | f19410ca | Michael Walle | .version_id = 1,
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135 | f19410ca | Michael Walle | .minimum_version_id = 1,
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136 | f19410ca | Michael Walle | .minimum_version_id_old = 1,
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137 | f19410ca | Michael Walle | .fields = (VMStateField[]) { |
138 | f19410ca | Michael Walle | VMSTATE_UINT32_ARRAY(regs, LM32SysState, R_MAX), |
139 | f19410ca | Michael Walle | VMSTATE_BUFFER(testname, LM32SysState), |
140 | f19410ca | Michael Walle | VMSTATE_END_OF_LIST() |
141 | f19410ca | Michael Walle | } |
142 | f19410ca | Michael Walle | }; |
143 | f19410ca | Michael Walle | |
144 | f19410ca | Michael Walle | static SysBusDeviceInfo lm32_sys_info = {
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145 | f19410ca | Michael Walle | .init = lm32_sys_init, |
146 | f19410ca | Michael Walle | .qdev.name = "lm32-sys",
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147 | f19410ca | Michael Walle | .qdev.size = sizeof(LM32SysState),
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148 | f19410ca | Michael Walle | .qdev.vmsd = &vmstate_lm32_sys, |
149 | f19410ca | Michael Walle | .qdev.reset = sys_reset, |
150 | f19410ca | Michael Walle | .qdev.props = (Property[]) { |
151 | f19410ca | Michael Walle | DEFINE_PROP_UINT32("base", LM32SysState, base, 0xffff0000), |
152 | f19410ca | Michael Walle | DEFINE_PROP_END_OF_LIST(), |
153 | f19410ca | Michael Walle | } |
154 | f19410ca | Michael Walle | }; |
155 | f19410ca | Michael Walle | |
156 | f19410ca | Michael Walle | static void lm32_sys_register(void) |
157 | f19410ca | Michael Walle | { |
158 | f19410ca | Michael Walle | sysbus_register_withprop(&lm32_sys_info); |
159 | f19410ca | Michael Walle | } |
160 | f19410ca | Michael Walle | |
161 | f19410ca | Michael Walle | device_init(lm32_sys_register) |